RMT

esp32p4

Struct RMT 

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pub struct RMT { /* private fields */ }
Expand description

Remote Control

Implementations§

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impl RMT

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pub const PTR: *const RegisterBlock = {0x500d4000 as *const rmt::RegisterBlock}

Pointer to the register block

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pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

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pub unsafe fn steal() -> Self

Steal an instance of this peripheral

§Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>§

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pub fn tx_chdata(&self, n: usize) -> &TX_CHDATA

0x00..0x10 - The read and write data register for CHANNEL%s by apb fifo access.

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pub fn tx_chdata_iter(&self) -> impl Iterator<Item = &TX_CHDATA>

Iterator for array of: 0x00..0x10 - The read and write data register for CHANNEL%s by apb fifo access.

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pub fn tx_ch0data(&self) -> &TX_CHDATA

0x00 - The read and write data register for CHANNEL0 by apb fifo access.

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pub fn tx_ch1data(&self) -> &TX_CHDATA

0x04 - The read and write data register for CHANNEL1 by apb fifo access.

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pub fn tx_ch2data(&self) -> &TX_CHDATA

0x08 - The read and write data register for CHANNEL2 by apb fifo access.

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pub fn tx_ch3data(&self) -> &TX_CHDATA

0x0c - The read and write data register for CHANNEL3 by apb fifo access.

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pub fn rx_chdata(&self, n: usize) -> &RX_CHDATA

0x10..0x20 - The read and write data register for CHANNEL$n by apb fifo access.

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pub fn rx_chdata_iter(&self) -> impl Iterator<Item = &RX_CHDATA>

Iterator for array of: 0x10..0x20 - The read and write data register for CHANNEL$n by apb fifo access.

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pub fn rx_ch0data(&self) -> &RX_CHDATA

0x10 - The read and write data register for CHANNEL$n by apb fifo access.

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pub fn rx_ch1data(&self) -> &RX_CHDATA

0x14 - The read and write data register for CHANNEL$n by apb fifo access.

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pub fn rx_ch2data(&self) -> &RX_CHDATA

0x18 - The read and write data register for CHANNEL$n by apb fifo access.

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pub fn rx_ch3data(&self) -> &RX_CHDATA

0x1c - The read and write data register for CHANNEL$n by apb fifo access.

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pub fn tx_chconf0(&self, n: usize) -> &TX_CHCONF0

0x20..0x30 - Channel %s configure register 0

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pub fn tx_chconf0_iter(&self) -> impl Iterator<Item = &TX_CHCONF0>

Iterator for array of: 0x20..0x30 - Channel %s configure register 0

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pub fn tx_ch0conf0(&self) -> &TX_CHCONF0

0x20 - Channel 0 configure register 0

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pub fn tx_ch1conf0(&self) -> &TX_CHCONF0

0x24 - Channel 1 configure register 0

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pub fn tx_ch2conf0(&self) -> &TX_CHCONF0

0x28 - Channel 2 configure register 0

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pub fn tx_ch3conf0(&self) -> &TX_CHCONF0

0x2c - Channel 3 configure register 0

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pub fn rx_chconf0(&self, n: usize) -> &RX_CHCONF0

0x30..0x40 - Channel %s configure register 0

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pub fn rx_chconf0_iter(&self) -> impl Iterator<Item = &RX_CHCONF0>

Iterator for array of: 0x30..0x40 - Channel %s configure register 0

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pub fn rx_ch0conf0(&self) -> &RX_CHCONF0

0x30 - Channel 0 configure register 0

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pub fn rx_ch1conf0(&self) -> &RX_CHCONF0

0x38 - Channel 1 configure register 0

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pub fn rx_ch2conf0(&self) -> &RX_CHCONF0

0x40 - Channel 2 configure register 0

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pub fn rx_ch3conf0(&self) -> &RX_CHCONF0

0x48 - Channel 3 configure register 0

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pub fn rx_chconf1(&self, n: usize) -> &RX_CHCONF1

0x34..0x44 - Channel %s configure register 1

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pub fn rx_chconf1_iter(&self) -> impl Iterator<Item = &RX_CHCONF1>

Iterator for array of: 0x34..0x44 - Channel %s configure register 1

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pub fn rx_ch0conf1(&self) -> &RX_CHCONF1

0x34 - Channel 0 configure register 1

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pub fn rx_ch1conf1(&self) -> &RX_CHCONF1

0x3c - Channel 1 configure register 1

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pub fn rx_ch2conf1(&self) -> &RX_CHCONF1

0x44 - Channel 2 configure register 1

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pub fn rx_ch3conf1(&self) -> &RX_CHCONF1

0x4c - Channel 3 configure register 1

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pub fn tx_chstatus(&self, n: usize) -> &TX_CHSTATUS

0x50..0x60 - Channel %s status register

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pub fn tx_chstatus_iter(&self) -> impl Iterator<Item = &TX_CHSTATUS>

Iterator for array of: 0x50..0x60 - Channel %s status register

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pub fn tx_ch0status(&self) -> &TX_CHSTATUS

0x50 - Channel 0 status register

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pub fn tx_ch1status(&self) -> &TX_CHSTATUS

0x54 - Channel 1 status register

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pub fn tx_ch2status(&self) -> &TX_CHSTATUS

0x58 - Channel 2 status register

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pub fn tx_ch3status(&self) -> &TX_CHSTATUS

0x5c - Channel 3 status register

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pub fn rx_chstatus(&self, n: usize) -> &RX_CHSTATUS

0x60..0x70 - Channel %s status register

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pub fn rx_chstatus_iter(&self) -> impl Iterator<Item = &RX_CHSTATUS>

Iterator for array of: 0x60..0x70 - Channel %s status register

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pub fn rx_ch0status(&self) -> &RX_CHSTATUS

0x60 - Channel 0 status register

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pub fn rx_ch1status(&self) -> &RX_CHSTATUS

0x64 - Channel 1 status register

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pub fn rx_ch2status(&self) -> &RX_CHSTATUS

0x68 - Channel 2 status register

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pub fn rx_ch3status(&self) -> &RX_CHSTATUS

0x6c - Channel 3 status register

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pub fn int_raw(&self) -> &INT_RAW

0x70 - Raw interrupt status

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pub fn int_st(&self) -> &INT_ST

0x74 - Masked interrupt status

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pub fn int_ena(&self) -> &INT_ENA

0x78 - Interrupt enable bits

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pub fn int_clr(&self) -> &INT_CLR

0x7c - Interrupt clear bits

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pub fn chcarrier_duty(&self, n: usize) -> &CHCARRIER_DUTY

0x80..0x90 - Channel %s duty cycle configuration register

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pub fn chcarrier_duty_iter(&self) -> impl Iterator<Item = &CHCARRIER_DUTY>

Iterator for array of: 0x80..0x90 - Channel %s duty cycle configuration register

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pub fn ch0carrier_duty(&self) -> &CHCARRIER_DUTY

0x80 - Channel 0 duty cycle configuration register

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pub fn ch1carrier_duty(&self) -> &CHCARRIER_DUTY

0x84 - Channel 1 duty cycle configuration register

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pub fn ch2carrier_duty(&self) -> &CHCARRIER_DUTY

0x88 - Channel 2 duty cycle configuration register

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pub fn ch3carrier_duty(&self) -> &CHCARRIER_DUTY

0x8c - Channel 3 duty cycle configuration register

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pub fn ch_rx_carrier_rm(&self, n: usize) -> &CH_RX_CARRIER_RM

0x90..0xa0 - Channel %s carrier remove register

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pub fn ch_rx_carrier_rm_iter(&self) -> impl Iterator<Item = &CH_RX_CARRIER_RM>

Iterator for array of: 0x90..0xa0 - Channel %s carrier remove register

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pub fn ch0_rx_carrier_rm(&self) -> &CH_RX_CARRIER_RM

0x90 - Channel 0 carrier remove register

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pub fn ch1_rx_carrier_rm(&self) -> &CH_RX_CARRIER_RM

0x94 - Channel 1 carrier remove register

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pub fn ch2_rx_carrier_rm(&self) -> &CH_RX_CARRIER_RM

0x98 - Channel 2 carrier remove register

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pub fn ch3_rx_carrier_rm(&self) -> &CH_RX_CARRIER_RM

0x9c - Channel 3 carrier remove register

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pub fn ch_tx_lim(&self, n: usize) -> &CH_TX_LIM

0xa0..0xb0 - Channel %s Tx event configuration register

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pub fn ch_tx_lim_iter(&self) -> impl Iterator<Item = &CH_TX_LIM>

Iterator for array of: 0xa0..0xb0 - Channel %s Tx event configuration register

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pub fn ch0_tx_lim(&self) -> &CH_TX_LIM

0xa0 - Channel 0 Tx event configuration register

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pub fn ch1_tx_lim(&self) -> &CH_TX_LIM

0xa4 - Channel 1 Tx event configuration register

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pub fn ch2_tx_lim(&self) -> &CH_TX_LIM

0xa8 - Channel 2 Tx event configuration register

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pub fn ch3_tx_lim(&self) -> &CH_TX_LIM

0xac - Channel 3 Tx event configuration register

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pub fn ch_rx_lim(&self, n: usize) -> &CH_RX_LIM

0xb0..0xc0 - Channel %s Rx event configuration register

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pub fn ch_rx_lim_iter(&self) -> impl Iterator<Item = &CH_RX_LIM>

Iterator for array of: 0xb0..0xc0 - Channel %s Rx event configuration register

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pub fn ch0_rx_lim(&self) -> &CH_RX_LIM

0xb0 - Channel 0 Rx event configuration register

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pub fn ch1_rx_lim(&self) -> &CH_RX_LIM

0xb4 - Channel 1 Rx event configuration register

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pub fn ch2_rx_lim(&self) -> &CH_RX_LIM

0xb8 - Channel 2 Rx event configuration register

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pub fn ch3_rx_lim(&self) -> &CH_RX_LIM

0xbc - Channel 3 Rx event configuration register

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pub fn sys_conf(&self) -> &SYS_CONF

0xc0 - RMT apb configuration register

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pub fn tx_sim(&self) -> &TX_SIM

0xc4 - RMT TX synchronous register

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pub fn ref_cnt_rst(&self) -> &REF_CNT_RST

0xc8 - RMT clock divider reset register

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pub fn date(&self) -> &DATE

0xcc - RMT version register

Trait Implementations§

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impl Debug for RMT

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fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
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impl Deref for RMT

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type Target = RegisterBlock

The resulting type after dereferencing.
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fn deref(&self) -> &Self::Target

Dereferences the value.
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impl Send for RMT

Auto Trait Implementations§

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impl Freeze for RMT

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impl RefUnwindSafe for RMT

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impl !Sync for RMT

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impl Unpin for RMT

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impl UnwindSafe for RMT

Blanket Implementations§

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<P, T> Receiver for P
where P: Deref<Target = T> + ?Sized, T: ?Sized,

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type Target = T

🔬This is a nightly-only experimental API. (arbitrary_self_types)
The target type on which the method may be called.
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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.