Module sys_conf

RMT apb configuration register

Structs

SYS_CONF_SPEC

RMT apb configuration register

Type Aliases

APB_FIFO_MASK_R

Field APB_FIFO_MASK reader - 1’h1: access memory directly. 1’h0: access memory by FIFO.

APB_FIFO_MASK_W

Field APB_FIFO_MASK writer - 1’h1: access memory directly. 1’h0: access memory by FIFO.

CLK_EN_R

Field CLK_EN reader - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers

CLK_EN_W

Field CLK_EN writer - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers

MEM_CLK_FORCE_ON_R

Field MEM_CLK_FORCE_ON reader - Set this bit to enable the clock for RMT memory.

MEM_CLK_FORCE_ON_W

Field MEM_CLK_FORCE_ON writer - Set this bit to enable the clock for RMT memory.

MEM_FORCE_PD_R

Field MEM_FORCE_PD reader - Set this bit to power down RMT memory.

MEM_FORCE_PD_W

Field MEM_FORCE_PD writer - Set this bit to power down RMT memory.

MEM_FORCE_PU_R

Field MEM_FORCE_PU reader - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode.

MEM_FORCE_PU_W

Field MEM_FORCE_PU writer - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode.

R

Register SYS_CONF reader

SCLK_ACTIVE_R

Field SCLK_ACTIVE reader - rmt_sclk switch

SCLK_ACTIVE_W

Field SCLK_ACTIVE writer - rmt_sclk switch

SCLK_DIV_A_R

Field SCLK_DIV_A reader - the numerator of the fractional part of the fractional divisor

SCLK_DIV_A_W

Field SCLK_DIV_A writer - the numerator of the fractional part of the fractional divisor

SCLK_DIV_B_R

Field SCLK_DIV_B reader - the denominator of the fractional part of the fractional divisor

SCLK_DIV_B_W

Field SCLK_DIV_B writer - the denominator of the fractional part of the fractional divisor

SCLK_DIV_NUM_R

Field SCLK_DIV_NUM reader - the integral part of the fractional divisor

SCLK_DIV_NUM_W

Field SCLK_DIV_NUM writer - the integral part of the fractional divisor

SCLK_SEL_R

Field SCLK_SEL reader - choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL

SCLK_SEL_W

Field SCLK_SEL writer - choose the clock source of rmt_sclk. 1:CLK_80Mhz.2:CLK_8MHz.3:XTAL

W

Register SYS_CONF writer