Type Alias W 

pub type W = W<TX_CTRL_SPEC>;

Register TX_CTRL writer

Aliased Type

pub struct W { /* private fields */ }

Implementations

impl W

pub fn tx_ena(&mut self) -> TX_ENA_W<'_, TX_CTRL_SPEC>

Bit 0 - write this bit to enable the bitscrambler tx

pub fn tx_pause(&mut self) -> TX_PAUSE_W<'_, TX_CTRL_SPEC>

Bit 1 - write this bit to pause the bitscrambler tx core

pub fn tx_halt(&mut self) -> TX_HALT_W<'_, TX_CTRL_SPEC>

Bit 2 - write this bit to halt the bitscrambler tx core

pub fn tx_eof_mode(&mut self) -> TX_EOF_MODE_W<'_, TX_CTRL_SPEC>

Bit 3 - write this bit to ser the bitscrambler tx core EOF signal generating mode which is combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 counter by write peripheral buffer

pub fn tx_cond_mode(&mut self) -> TX_COND_MODE_W<'_, TX_CTRL_SPEC>

Bit 4 - write this bit to specify the LOOP instruction condition mode of bitscrambler tx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition

pub fn tx_fetch_mode(&mut self) -> TX_FETCH_MODE_W<'_, TX_CTRL_SPEC>

Bit 5 - write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions

pub fn tx_halt_mode(&mut self) -> TX_HALT_MODE_W<'_, TX_CTRL_SPEC>

Bit 6 - write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: wait write data back done, , 1: ignore write data back

pub fn tx_rd_dummy(&mut self) -> TX_RD_DUMMY_W<'_, TX_CTRL_SPEC>

Bit 7 - write this bit to set the bitscrambler tx core read data mode when EOF received.0: wait read data, 1: ignore read data

pub fn tx_fifo_rst(&mut self) -> TX_FIFO_RST_W<'_, TX_CTRL_SPEC>

Bit 8 - write this bit to reset the bitscrambler tx fifo