Type Alias W 

pub type W = W<INT_ENA_SPEC>;

Register INT_ENA writer

Aliased Type

pub struct W { /* private fields */ }

Implementations

impl W

pub fn timer0_stop(&mut self) -> TIMER0_STOP_W<'_, INT_ENA_SPEC>

Bit 0 - Enable bit: Write 1 to enable the interrupt triggered when the timer 0 stops.

pub fn timer1_stop(&mut self) -> TIMER1_STOP_W<'_, INT_ENA_SPEC>

Bit 1 - Enable bit: Write 1 to enable the interrupt triggered when the timer 1 stops.

pub fn timer2_stop(&mut self) -> TIMER2_STOP_W<'_, INT_ENA_SPEC>

Bit 2 - Enable bit: Write 1 to enable the interrupt triggered when the timer 2 stops.

pub fn timer0_tez(&mut self) -> TIMER0_TEZ_W<'_, INT_ENA_SPEC>

Bit 3 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEZ event.

pub fn timer1_tez(&mut self) -> TIMER1_TEZ_W<'_, INT_ENA_SPEC>

Bit 4 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEZ event.

pub fn timer2_tez(&mut self) -> TIMER2_TEZ_W<'_, INT_ENA_SPEC>

Bit 5 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEZ event.

pub fn timer0_tep(&mut self) -> TIMER0_TEP_W<'_, INT_ENA_SPEC>

Bit 6 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 0 TEP event.

pub fn timer1_tep(&mut self) -> TIMER1_TEP_W<'_, INT_ENA_SPEC>

Bit 7 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 1 TEP event.

pub fn timer2_tep(&mut self) -> TIMER2_TEP_W<'_, INT_ENA_SPEC>

Bit 8 - Enable bit: Write 1 to enable the interrupt triggered by a PWM timer 2 TEP event.

pub fn fault0(&mut self) -> FAULT0_W<'_, INT_ENA_SPEC>

Bit 9 - Enable bit: Write 1 to enable the interrupt triggered when event_f0 starts.

pub fn fault1(&mut self) -> FAULT1_W<'_, INT_ENA_SPEC>

Bit 10 - Enable bit: Write 1 to enable the interrupt triggered when event_f1 starts.

pub fn fault2(&mut self) -> FAULT2_W<'_, INT_ENA_SPEC>

Bit 11 - Enable bit: Write 1 to enable the interrupt triggered when event_f2 starts.

pub fn fault0_clr(&mut self) -> FAULT0_CLR_W<'_, INT_ENA_SPEC>

Bit 12 - Enable bit: Write 1 to enable the interrupt triggered when event_f0 clears.

pub fn fault1_clr(&mut self) -> FAULT1_CLR_W<'_, INT_ENA_SPEC>

Bit 13 - Enable bit: Write 1 to enable the interrupt triggered when event_f1 clears.

pub fn fault2_clr(&mut self) -> FAULT2_CLR_W<'_, INT_ENA_SPEC>

Bit 14 - Enable bit: Write 1 to enable the interrupt triggered when event_f2 clears.

pub fn cmpr0_tea(&mut self) -> CMPR0_TEA_W<'_, INT_ENA_SPEC>

Bit 15 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEA event.

pub fn cmpr1_tea(&mut self) -> CMPR1_TEA_W<'_, INT_ENA_SPEC>

Bit 16 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEA event.

pub fn cmpr2_tea(&mut self) -> CMPR2_TEA_W<'_, INT_ENA_SPEC>

Bit 17 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEA event.

pub fn cmpr0_teb(&mut self) -> CMPR0_TEB_W<'_, INT_ENA_SPEC>

Bit 18 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 0 TEB event.

pub fn cmpr1_teb(&mut self) -> CMPR1_TEB_W<'_, INT_ENA_SPEC>

Bit 19 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 1 TEB event.

pub fn cmpr2_teb(&mut self) -> CMPR2_TEB_W<'_, INT_ENA_SPEC>

Bit 20 - Enable bit: Write 1 to enable the interrupt triggered by a PWM operator 2 TEB event.

pub fn tz0_cbc(&mut self) -> TZ0_CBC_W<'_, INT_ENA_SPEC>

Bit 21 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM0.

pub fn tz1_cbc(&mut self) -> TZ1_CBC_W<'_, INT_ENA_SPEC>

Bit 22 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM1.

pub fn tz2_cbc(&mut self) -> TZ2_CBC_W<'_, INT_ENA_SPEC>

Bit 23 - Enable bit: Write 1 to enable the interrupt triggered by a cycle-by-cycle mode action on PWM2.

pub fn tz0_ost(&mut self) -> TZ0_OST_W<'_, INT_ENA_SPEC>

Bit 24 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM0.

pub fn tz1_ost(&mut self) -> TZ1_OST_W<'_, INT_ENA_SPEC>

Bit 25 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM1.

pub fn tz2_ost(&mut self) -> TZ2_OST_W<'_, INT_ENA_SPEC>

Bit 26 - Enable bit: Write 1 to enable the interrupt triggered by a one-shot mode action on PWM2.

pub fn cap0(&mut self) -> CAP0_W<'_, INT_ENA_SPEC>

Bit 27 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP0.

pub fn cap1(&mut self) -> CAP1_W<'_, INT_ENA_SPEC>

Bit 28 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP1.

pub fn cap2(&mut self) -> CAP2_W<'_, INT_ENA_SPEC>

Bit 29 - Enable bit: Write 1 to enable the interrupt triggered by capture on CAP2.