Struct esp32p4::H264_DMA

pub struct H264_DMA { /* private fields */ }

H264 Encoder (DMA)

Implementations

impl H264_DMA

pub const PTR: *const RegisterBlock = {0x500a7000 as *const h264_dma::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> Self

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn out_conf0_ch0(&self) -> &OUT_CONF0_CH0

0x00 - TX CH0 config0 register

pub fn out_int_raw_ch0(&self) -> &OUT_INT_RAW_CH0

0x04 - TX CH0 interrupt raw register

pub fn out_int_ena_ch0(&self) -> &OUT_INT_ENA_CH0

0x08 - TX CH0 interrupt ena register

pub fn out_int_st_ch0(&self) -> &OUT_INT_ST_CH0

0x0c - TX CH0 interrupt st register

pub fn out_int_clr_ch0(&self) -> &OUT_INT_CLR_CH0

0x10 - TX CH0 interrupt clr register

pub fn outfifo_status_ch0(&self) -> &OUTFIFO_STATUS_CH0

0x14 - TX CH0 outfifo status register

pub fn out_push_ch0(&self) -> &OUT_PUSH_CH0

0x18 - TX CH0 outfifo push register

pub fn out_link_conf_ch0(&self) -> &OUT_LINK_CONF_CH0

0x1c - TX CH0 out_link dscr ctrl register

pub fn out_link_addr_ch0(&self) -> &OUT_LINK_ADDR_CH0

0x20 - TX CH0 out_link dscr addr register

pub fn out_state_ch0(&self) -> &OUT_STATE_CH0

0x24 - TX CH0 state register

pub fn out_eof_des_addr_ch0(&self) -> &OUT_EOF_DES_ADDR_CH0

0x28 - TX CH0 eof des addr register

pub fn out_dscr_ch0(&self) -> &OUT_DSCR_CH0

0x2c - TX CH0 next dscr addr register

pub fn out_dscr_bf0_ch0(&self) -> &OUT_DSCR_BF0_CH0

0x30 - TX CH0 last dscr addr register

pub fn out_dscr_bf1_ch0(&self) -> &OUT_DSCR_BF1_CH0

0x34 - TX CH0 second-to-last dscr addr register

pub fn out_arb_ch0(&self) -> &OUT_ARB_CH0

0x3c - TX CH0 arb register

pub fn out_ro_status_ch0(&self) -> &OUT_RO_STATUS_CH0

0x40 - TX CH0 reorder status register

pub fn out_ro_pd_conf_ch0(&self) -> &OUT_RO_PD_CONF_CH0

0x44 - TX CH0 reorder power config register

pub fn out_mode_enable_ch0(&self) -> &OUT_MODE_ENABLE_CH0

0x50 - tx CH0 mode enable register

pub fn out_mode_yuv_ch0(&self) -> &OUT_MODE_YUV_CH0

0x54 - tx CH0 test mode yuv value register

pub fn out_etm_conf_ch0(&self) -> &OUT_ETM_CONF_CH0

0x68 - TX CH0 ETM config register

pub fn out_buf_len_ch0(&self) -> &OUT_BUF_LEN_CH0

0x70 - tx CH0 buf len register

pub fn out_fifo_bcnt_ch0(&self) -> &OUT_FIFO_BCNT_CH0

0x74 - tx CH0 fifo byte cnt register

pub fn out_push_bytecnt_ch0(&self) -> &OUT_PUSH_BYTECNT_CH0

0x78 - tx CH0 push byte cnt register

pub fn out_xaddr_ch0(&self) -> &OUT_XADDR_CH0

0x7c - tx CH0 xaddr register

pub fn out_conf0_ch1(&self) -> &OUT_CONF0_CH1

0x100 - TX CH1 config0 register

pub fn out_int_raw_ch1(&self) -> &OUT_INT_RAW_CH1

0x104 - TX CH1 interrupt raw register

pub fn out_int_ena_ch1(&self) -> &OUT_INT_ENA_CH1

0x108 - TX CH1 interrupt ena register

pub fn out_int_st_ch1(&self) -> &OUT_INT_ST_CH1

0x10c - TX CH1 interrupt st register

pub fn out_int_clr_ch1(&self) -> &OUT_INT_CLR_CH1

0x110 - TX CH1 interrupt clr register

pub fn outfifo_status_ch1(&self) -> &OUTFIFO_STATUS_CH1

0x114 - TX CH1 outfifo status register

pub fn out_push_ch1(&self) -> &OUT_PUSH_CH1

0x118 - TX CH1 outfifo push register

pub fn out_link_conf_ch1(&self) -> &OUT_LINK_CONF_CH1

0x11c - TX CH1 out_link dscr ctrl register

pub fn out_link_addr_ch1(&self) -> &OUT_LINK_ADDR_CH1

0x120 - TX CH1 out_link dscr addr register

pub fn out_state_ch1(&self) -> &OUT_STATE_CH1

0x124 - TX CH1 state register

pub fn out_eof_des_addr_ch1(&self) -> &OUT_EOF_DES_ADDR_CH1

0x128 - TX CH1 eof des addr register

pub fn out_dscr_ch1(&self) -> &OUT_DSCR_CH1

0x12c - TX CH1 next dscr addr register

pub fn out_dscr_bf0_ch1(&self) -> &OUT_DSCR_BF0_CH1

0x130 - TX CH1 last dscr addr register

pub fn out_dscr_bf1_ch1(&self) -> &OUT_DSCR_BF1_CH1

0x134 - TX CH1 second-to-last dscr addr register

pub fn out_arb_ch1(&self) -> &OUT_ARB_CH1

0x13c - TX CH1 arb register

pub fn out_etm_conf_ch1(&self) -> &OUT_ETM_CONF_CH1

0x168 - TX CH1 ETM config register

pub fn out_buf_len_ch1(&self) -> &OUT_BUF_LEN_CH1

0x170 - tx CH1 buf len register

pub fn out_fifo_bcnt_ch1(&self) -> &OUT_FIFO_BCNT_CH1

0x174 - tx CH1 fifo byte cnt register

pub fn out_push_bytecnt_ch1(&self) -> &OUT_PUSH_BYTECNT_CH1

0x178 - tx CH1 push byte cnt register

pub fn out_xaddr_ch1(&self) -> &OUT_XADDR_CH1

0x17c - tx CH1 xaddr register

pub fn out_conf0_ch2(&self) -> &OUT_CONF0_CH2

0x200 - TX CH2 config0 register

pub fn out_int_raw_ch2(&self) -> &OUT_INT_RAW_CH2

0x204 - TX CH2 interrupt raw register

pub fn out_int_ena_ch2(&self) -> &OUT_INT_ENA_CH2

0x208 - TX CH2 interrupt ena register

pub fn out_int_st_ch2(&self) -> &OUT_INT_ST_CH2

0x20c - TX CH2 interrupt st register

pub fn out_int_clr_ch2(&self) -> &OUT_INT_CLR_CH2

0x210 - TX CH2 interrupt clr register

pub fn outfifo_status_ch2(&self) -> &OUTFIFO_STATUS_CH2

0x214 - TX CH2 outfifo status register

pub fn out_push_ch2(&self) -> &OUT_PUSH_CH2

0x218 - TX CH2 outfifo push register

pub fn out_link_conf_ch2(&self) -> &OUT_LINK_CONF_CH2

0x21c - TX CH2 out_link dscr ctrl register

pub fn out_link_addr_ch2(&self) -> &OUT_LINK_ADDR_CH2

0x220 - TX CH2 out_link dscr addr register

pub fn out_state_ch2(&self) -> &OUT_STATE_CH2

0x224 - TX CH2 state register

pub fn out_eof_des_addr_ch2(&self) -> &OUT_EOF_DES_ADDR_CH2

0x228 - TX CH2 eof des addr register

pub fn out_dscr_ch2(&self) -> &OUT_DSCR_CH2

0x22c - TX CH2 next dscr addr register

pub fn out_dscr_bf0_ch2(&self) -> &OUT_DSCR_BF0_CH2

0x230 - TX CH2 last dscr addr register

pub fn out_dscr_bf1_ch2(&self) -> &OUT_DSCR_BF1_CH2

0x234 - TX CH2 second-to-last dscr addr register

pub fn out_arb_ch2(&self) -> &OUT_ARB_CH2

0x23c - TX CH2 arb register

pub fn out_etm_conf_ch2(&self) -> &OUT_ETM_CONF_CH2

0x268 - TX CH2 ETM config register

pub fn out_buf_len_ch2(&self) -> &OUT_BUF_LEN_CH2

0x270 - tx CH2 buf len register

pub fn out_fifo_bcnt_ch2(&self) -> &OUT_FIFO_BCNT_CH2

0x274 - tx CH2 fifo byte cnt register

pub fn out_push_bytecnt_ch2(&self) -> &OUT_PUSH_BYTECNT_CH2

0x278 - tx CH2 push byte cnt register

pub fn out_xaddr_ch2(&self) -> &OUT_XADDR_CH2

0x27c - tx CH2 xaddr register

pub fn out_conf0_ch3(&self) -> &OUT_CONF0_CH3

0x300 - TX CH3 config0 register

pub fn out_int_raw_ch3(&self) -> &OUT_INT_RAW_CH3

0x304 - TX CH3 interrupt raw register

pub fn out_int_ena_ch3(&self) -> &OUT_INT_ENA_CH3

0x308 - TX CH3 interrupt ena register

pub fn out_int_st_ch3(&self) -> &OUT_INT_ST_CH3

0x30c - TX CH3 interrupt st register

pub fn out_int_clr_ch3(&self) -> &OUT_INT_CLR_CH3

0x310 - TX CH3 interrupt clr register

pub fn outfifo_status_ch3(&self) -> &OUTFIFO_STATUS_CH3

0x314 - TX CH3 outfifo status register

pub fn out_push_ch3(&self) -> &OUT_PUSH_CH3

0x318 - TX CH3 outfifo push register

pub fn out_link_conf_ch3(&self) -> &OUT_LINK_CONF_CH3

0x31c - TX CH3 out_link dscr ctrl register

pub fn out_link_addr_ch3(&self) -> &OUT_LINK_ADDR_CH3

0x320 - TX CH3 out_link dscr addr register

pub fn out_state_ch3(&self) -> &OUT_STATE_CH3

0x324 - TX CH3 state register

pub fn out_eof_des_addr_ch3(&self) -> &OUT_EOF_DES_ADDR_CH3

0x328 - TX CH3 eof des addr register

pub fn out_dscr_ch3(&self) -> &OUT_DSCR_CH3

0x32c - TX CH3 next dscr addr register

pub fn out_dscr_bf0_ch3(&self) -> &OUT_DSCR_BF0_CH3

0x330 - TX CH3 last dscr addr register

pub fn out_dscr_bf1_ch3(&self) -> &OUT_DSCR_BF1_CH3

0x334 - TX CH3 second-to-last dscr addr register

pub fn out_arb_ch3(&self) -> &OUT_ARB_CH3

0x33c - TX CH3 arb register

pub fn out_etm_conf_ch3(&self) -> &OUT_ETM_CONF_CH3

0x368 - TX CH3 ETM config register

pub fn out_buf_len_ch3(&self) -> &OUT_BUF_LEN_CH3

0x370 - tx CH3 buf len register

pub fn out_fifo_bcnt_ch3(&self) -> &OUT_FIFO_BCNT_CH3

0x374 - tx CH3 fifo byte cnt register

pub fn out_push_bytecnt_ch3(&self) -> &OUT_PUSH_BYTECNT_CH3

0x378 - tx CH3 push byte cnt register

pub fn out_xaddr_ch3(&self) -> &OUT_XADDR_CH3

0x37c - tx CH3 xaddr register

pub fn out_block_buf_len_ch3(&self) -> &OUT_BLOCK_BUF_LEN_CH3

0x380 - tx CH3 block buf len register

pub fn out_conf0_ch4(&self) -> &OUT_CONF0_CH4

0x400 - TX CH4 config0 register

pub fn out_int_raw_ch4(&self) -> &OUT_INT_RAW_CH4

0x404 - TX CH4 interrupt raw register

pub fn out_int_ena_ch4(&self) -> &OUT_INT_ENA_CH4

0x408 - TX CH4 interrupt ena register

pub fn out_int_st_ch4(&self) -> &OUT_INT_ST_CH4

0x40c - TX CH4 interrupt st register

pub fn out_int_clr_ch4(&self) -> &OUT_INT_CLR_CH4

0x410 - TX CH4 interrupt clr register

pub fn outfifo_status_ch4(&self) -> &OUTFIFO_STATUS_CH4

0x414 - TX CH4 outfifo status register

pub fn out_push_ch4(&self) -> &OUT_PUSH_CH4

0x418 - TX CH4 outfifo push register

pub fn out_link_conf_ch4(&self) -> &OUT_LINK_CONF_CH4

0x41c - TX CH4 out_link dscr ctrl register

pub fn out_link_addr_ch4(&self) -> &OUT_LINK_ADDR_CH4

0x420 - TX CH4 out_link dscr addr register

pub fn out_state_ch4(&self) -> &OUT_STATE_CH4

0x424 - TX CH4 state register

pub fn out_eof_des_addr_ch4(&self) -> &OUT_EOF_DES_ADDR_CH4

0x428 - TX CH4 eof des addr register

pub fn out_dscr_ch4(&self) -> &OUT_DSCR_CH4

0x42c - TX CH4 next dscr addr register

pub fn out_dscr_bf0_ch4(&self) -> &OUT_DSCR_BF0_CH4

0x430 - TX CH4 last dscr addr register

pub fn out_dscr_bf1_ch4(&self) -> &OUT_DSCR_BF1_CH4

0x434 - TX CH4 second-to-last dscr addr register

pub fn out_arb_ch4(&self) -> &OUT_ARB_CH4

0x43c - TX CH4 arb register

pub fn out_etm_conf_ch4(&self) -> &OUT_ETM_CONF_CH4

0x468 - TX CH4 ETM config register

pub fn out_buf_len_ch4(&self) -> &OUT_BUF_LEN_CH4

0x470 - tx CH4 buf len register

pub fn out_fifo_bcnt_ch4(&self) -> &OUT_FIFO_BCNT_CH4

0x474 - tx CH4 fifo byte cnt register

pub fn out_push_bytecnt_ch4(&self) -> &OUT_PUSH_BYTECNT_CH4

0x478 - tx CH4 push byte cnt register

pub fn out_xaddr_ch4(&self) -> &OUT_XADDR_CH4

0x47c - tx CH4 xaddr register

pub fn out_block_buf_len_ch4(&self) -> &OUT_BLOCK_BUF_LEN_CH4

0x480 - tx CH4 block buf len register

pub fn in_conf0_ch0(&self) -> &IN_CONF0_CH0

0x500 - RX CH0 config0 register

pub fn in_int_raw_ch0(&self) -> &IN_INT_RAW_CH0

0x504 - RX CH0 interrupt raw register

pub fn in_int_ena_ch0(&self) -> &IN_INT_ENA_CH0

0x508 - RX CH0 interrupt ena register

pub fn in_int_st_ch0(&self) -> &IN_INT_ST_CH0

0x50c - RX CH0 interrupt st register

pub fn in_int_clr_ch0(&self) -> &IN_INT_CLR_CH0

0x510 - RX CH0 interrupt clr register

pub fn infifo_status_ch0(&self) -> &INFIFO_STATUS_CH0

0x514 - RX CH0 INFIFO status register

pub fn in_pop_ch0(&self) -> &IN_POP_CH0

0x518 - RX CH0 INFIFO pop register

pub fn in_link_conf_ch0(&self) -> &IN_LINK_CONF_CH0

0x51c - RX CH0 in_link dscr ctrl register

pub fn in_link_addr_ch0(&self) -> &IN_LINK_ADDR_CH0

0x520 - RX CH0 in_link dscr addr register

pub fn in_state_ch0(&self) -> &IN_STATE_CH0

0x524 - RX CH0 state register

pub fn in_suc_eof_des_addr_ch0(&self) -> &IN_SUC_EOF_DES_ADDR_CH0

0x528 - RX CH0 eof des addr register

pub fn in_err_eof_des_addr_ch0(&self) -> &IN_ERR_EOF_DES_ADDR_CH0

0x52c - RX CH0 err eof des addr register

pub fn in_dscr_ch0(&self) -> &IN_DSCR_CH0

0x530 - RX CH0 next dscr addr register

pub fn in_dscr_bf0_ch0(&self) -> &IN_DSCR_BF0_CH0

0x534 - RX CH0 last dscr addr register

pub fn in_dscr_bf1_ch0(&self) -> &IN_DSCR_BF1_CH0

0x538 - RX CH0 second-to-last dscr addr register

pub fn in_arb_ch0(&self) -> &IN_ARB_CH0

0x540 - RX CH0 arb register

pub fn in_ro_pd_conf_ch0(&self) -> &IN_RO_PD_CONF_CH0

0x548 - RX CH0 reorder power config register

pub fn in_etm_conf_ch0(&self) -> &IN_ETM_CONF_CH0

0x56c - RX CH0 ETM config register

pub fn in_fifo_cnt_ch0(&self) -> &IN_FIFO_CNT_CH0

0x580 - rx CH0 fifo cnt register

pub fn in_pop_data_cnt_ch0(&self) -> &IN_POP_DATA_CNT_CH0

0x584 - rx CH0 pop data cnt register

pub fn in_xaddr_ch0(&self) -> &IN_XADDR_CH0

0x588 - rx CH0 xaddr register

pub fn in_buf_hb_rcv_ch0(&self) -> &IN_BUF_HB_RCV_CH0

0x58c - rx CH0 buf len hb rcv register

pub fn in_conf0_ch1(&self) -> &IN_CONF0_CH1

0x600 - RX CH1 config0 register

pub fn in_int_raw_ch1(&self) -> &IN_INT_RAW_CH1

0x604 - RX CH1 interrupt raw register

pub fn in_int_ena_ch1(&self) -> &IN_INT_ENA_CH1

0x608 - RX CH1 interrupt ena register

pub fn in_int_st_ch1(&self) -> &IN_INT_ST_CH1

0x60c - RX CH1 interrupt st register

pub fn in_int_clr_ch1(&self) -> &IN_INT_CLR_CH1

0x610 - RX CH1 interrupt clr register

pub fn infifo_status_ch1(&self) -> &INFIFO_STATUS_CH1

0x614 - RX CH1 INFIFO status register

pub fn in_pop_ch1(&self) -> &IN_POP_CH1

0x618 - RX CH1 INFIFO pop register

pub fn in_link_conf_ch1(&self) -> &IN_LINK_CONF_CH1

0x61c - RX CH1 in_link dscr ctrl register

pub fn in_link_addr_ch1(&self) -> &IN_LINK_ADDR_CH1

0x620 - RX CH1 in_link dscr addr register

pub fn in_state_ch1(&self) -> &IN_STATE_CH1

0x624 - RX CH1 state register

pub fn in_suc_eof_des_addr_ch1(&self) -> &IN_SUC_EOF_DES_ADDR_CH1

0x628 - RX CH1 eof des addr register

pub fn in_err_eof_des_addr_ch1(&self) -> &IN_ERR_EOF_DES_ADDR_CH1

0x62c - RX CH1 err eof des addr register

pub fn in_dscr_ch1(&self) -> &IN_DSCR_CH1

0x630 - RX CH1 next dscr addr register

pub fn in_dscr_bf0_ch1(&self) -> &IN_DSCR_BF0_CH1

0x634 - RX CH1 last dscr addr register

pub fn in_dscr_bf1_ch1(&self) -> &IN_DSCR_BF1_CH1

0x638 - RX CH1 second-to-last dscr addr register

pub fn in_arb_ch1(&self) -> &IN_ARB_CH1

0x640 - RX CH1 arb register

pub fn in_etm_conf_ch1(&self) -> &IN_ETM_CONF_CH1

0x648 - RX CH1 ETM config register

pub fn in_fifo_cnt_ch1(&self) -> &IN_FIFO_CNT_CH1

0x680 - rx CH1 fifo cnt register

pub fn in_pop_data_cnt_ch1(&self) -> &IN_POP_DATA_CNT_CH1

0x684 - rx CH1 pop data cnt register

pub fn in_xaddr_ch1(&self) -> &IN_XADDR_CH1

0x688 - rx CH1 xaddr register

pub fn in_buf_hb_rcv_ch1(&self) -> &IN_BUF_HB_RCV_CH1

0x68c - rx CH1 buf len hb rcv register

pub fn in_conf0_ch2(&self) -> &IN_CONF0_CH2

0x700 - RX CH2 config0 register

pub fn in_int_raw_ch2(&self) -> &IN_INT_RAW_CH2

0x704 - RX CH2 interrupt raw register

pub fn in_int_ena_ch2(&self) -> &IN_INT_ENA_CH2

0x708 - RX CH2 interrupt ena register

pub fn in_int_st_ch2(&self) -> &IN_INT_ST_CH2

0x70c - RX CH2 interrupt st register

pub fn in_int_clr_ch2(&self) -> &IN_INT_CLR_CH2

0x710 - RX CH2 interrupt clr register

pub fn infifo_status_ch2(&self) -> &INFIFO_STATUS_CH2

0x714 - RX CH2 INFIFO status register

pub fn in_pop_ch2(&self) -> &IN_POP_CH2

0x718 - RX CH2 INFIFO pop register

pub fn in_link_conf_ch2(&self) -> &IN_LINK_CONF_CH2

0x71c - RX CH2 in_link dscr ctrl register

pub fn in_link_addr_ch2(&self) -> &IN_LINK_ADDR_CH2

0x720 - RX CH2 in_link dscr addr register

pub fn in_state_ch2(&self) -> &IN_STATE_CH2

0x724 - RX CH2 state register

pub fn in_suc_eof_des_addr_ch2(&self) -> &IN_SUC_EOF_DES_ADDR_CH2

0x728 - RX CH2 eof des addr register

pub fn in_err_eof_des_addr_ch2(&self) -> &IN_ERR_EOF_DES_ADDR_CH2

0x72c - RX CH2 err eof des addr register

pub fn in_dscr_ch2(&self) -> &IN_DSCR_CH2

0x730 - RX CH2 next dscr addr register

pub fn in_dscr_bf0_ch2(&self) -> &IN_DSCR_BF0_CH2

0x734 - RX CH2 last dscr addr register

pub fn in_dscr_bf1_ch2(&self) -> &IN_DSCR_BF1_CH2

0x738 - RX CH2 second-to-last dscr addr register

pub fn in_arb_ch2(&self) -> &IN_ARB_CH2

0x740 - RX CH2 arb register

pub fn in_etm_conf_ch2(&self) -> &IN_ETM_CONF_CH2

0x748 - RX CH2 ETM config register

pub fn in_fifo_cnt_ch2(&self) -> &IN_FIFO_CNT_CH2

0x780 - rx CH2 fifo cnt register

pub fn in_pop_data_cnt_ch2(&self) -> &IN_POP_DATA_CNT_CH2

0x784 - rx CH2 pop data cnt register

pub fn in_xaddr_ch2(&self) -> &IN_XADDR_CH2

0x788 - rx CH2 xaddr register

pub fn in_buf_hb_rcv_ch2(&self) -> &IN_BUF_HB_RCV_CH2

0x78c - rx CH2 buf len hb rcv register

pub fn in_conf0_ch3(&self) -> &IN_CONF0_CH3

0x800 - RX CH3 config0 register

pub fn in_int_raw_ch3(&self) -> &IN_INT_RAW_CH3

0x804 - RX CH3 interrupt raw register

pub fn in_int_ena_ch3(&self) -> &IN_INT_ENA_CH3

0x808 - RX CH3 interrupt ena register

pub fn in_int_st_ch3(&self) -> &IN_INT_ST_CH3

0x80c - RX CH3 interrupt st register

pub fn in_int_clr_ch3(&self) -> &IN_INT_CLR_CH3

0x810 - RX CH3 interrupt clr register

pub fn infifo_status_ch3(&self) -> &INFIFO_STATUS_CH3

0x814 - RX CH3 INFIFO status register

pub fn in_pop_ch3(&self) -> &IN_POP_CH3

0x818 - RX CH3 INFIFO pop register

pub fn in_link_conf_ch3(&self) -> &IN_LINK_CONF_CH3

0x81c - RX CH3 in_link dscr ctrl register

pub fn in_link_addr_ch3(&self) -> &IN_LINK_ADDR_CH3

0x820 - RX CH3 in_link dscr addr register

pub fn in_state_ch3(&self) -> &IN_STATE_CH3

0x824 - RX CH3 state register

pub fn in_suc_eof_des_addr_ch3(&self) -> &IN_SUC_EOF_DES_ADDR_CH3

0x828 - RX CH3 eof des addr register

pub fn in_err_eof_des_addr_ch3(&self) -> &IN_ERR_EOF_DES_ADDR_CH3

0x82c - RX CH3 err eof des addr register

pub fn in_dscr_ch3(&self) -> &IN_DSCR_CH3

0x830 - RX CH3 next dscr addr register

pub fn in_dscr_bf0_ch3(&self) -> &IN_DSCR_BF0_CH3

0x834 - RX CH3 last dscr addr register

pub fn in_dscr_bf1_ch3(&self) -> &IN_DSCR_BF1_CH3

0x838 - RX CH3 second-to-last dscr addr register

pub fn in_arb_ch3(&self) -> &IN_ARB_CH3

0x840 - RX CH3 arb register

pub fn in_etm_conf_ch3(&self) -> &IN_ETM_CONF_CH3

0x848 - RX CH3 ETM config register

pub fn in_fifo_cnt_ch3(&self) -> &IN_FIFO_CNT_CH3

0x880 - rx CH3 fifo cnt register

pub fn in_pop_data_cnt_ch3(&self) -> &IN_POP_DATA_CNT_CH3

0x884 - rx CH3 pop data cnt register

pub fn in_xaddr_ch3(&self) -> &IN_XADDR_CH3

0x888 - rx CH3 xaddr register

pub fn in_buf_hb_rcv_ch3(&self) -> &IN_BUF_HB_RCV_CH3

0x88c - rx CH3 buf len hb rcv register

pub fn in_conf0_ch4(&self) -> &IN_CONF0_CH4

0x900 - RX CH4 config0 register

pub fn in_int_raw_ch4(&self) -> &IN_INT_RAW_CH4

0x904 - RX CH4 interrupt raw register

pub fn in_int_ena_ch4(&self) -> &IN_INT_ENA_CH4

0x908 - RX CH4 interrupt ena register

pub fn in_int_st_ch4(&self) -> &IN_INT_ST_CH4

0x90c - RX CH4 interrupt st register

pub fn in_int_clr_ch4(&self) -> &IN_INT_CLR_CH4

0x910 - RX CH4 interrupt clr register

pub fn infifo_status_ch4(&self) -> &INFIFO_STATUS_CH4

0x914 - RX CH4 INFIFO status register

pub fn in_pop_ch4(&self) -> &IN_POP_CH4

0x918 - RX CH4 INFIFO pop register

pub fn in_link_conf_ch4(&self) -> &IN_LINK_CONF_CH4

0x91c - RX CH4 in_link dscr ctrl register

pub fn in_link_addr_ch4(&self) -> &IN_LINK_ADDR_CH4

0x920 - RX CH4 in_link dscr addr register

pub fn in_state_ch4(&self) -> &IN_STATE_CH4

0x924 - RX CH4 state register

pub fn in_suc_eof_des_addr_ch4(&self) -> &IN_SUC_EOF_DES_ADDR_CH4

0x928 - RX CH4 eof des addr register

pub fn in_err_eof_des_addr_ch4(&self) -> &IN_ERR_EOF_DES_ADDR_CH4

0x92c - RX CH4 err eof des addr register

pub fn in_dscr_ch4(&self) -> &IN_DSCR_CH4

0x930 - RX CH4 next dscr addr register

pub fn in_dscr_bf0_ch4(&self) -> &IN_DSCR_BF0_CH4

0x934 - RX CH4 last dscr addr register

pub fn in_dscr_bf1_ch4(&self) -> &IN_DSCR_BF1_CH4

0x938 - RX CH4 second-to-last dscr addr register

pub fn in_arb_ch4(&self) -> &IN_ARB_CH4

0x940 - RX CH4 arb register

pub fn in_etm_conf_ch4(&self) -> &IN_ETM_CONF_CH4

0x948 - RX CH4 ETM config register

pub fn in_fifo_cnt_ch4(&self) -> &IN_FIFO_CNT_CH4

0x980 - rx CH4 fifo cnt register

pub fn in_pop_data_cnt_ch4(&self) -> &IN_POP_DATA_CNT_CH4

0x984 - rx CH4 pop data cnt register

pub fn in_xaddr_ch4(&self) -> &IN_XADDR_CH4

0x988 - rx CH4 xaddr register

pub fn in_buf_hb_rcv_ch4(&self) -> &IN_BUF_HB_RCV_CH4

0x98c - rx CH4 buf len hb rcv register

pub fn in_conf0_ch5(&self) -> &IN_CONF0_CH5

0xa00 - RX CH5 config0 register

pub fn in_conf1_ch5(&self) -> &IN_CONF1_CH5

0xa04 - RX CH5 config1 register

pub fn in_conf2_ch5(&self) -> &IN_CONF2_CH5

0xa08 - RX CH5 config2 register

pub fn in_conf3_ch5(&self) -> &IN_CONF3_CH5

0xa0c - RX CH5 config3 register

pub fn in_int_raw_ch5(&self) -> &IN_INT_RAW_CH5

0xa10 - RX CH5 interrupt raw register

pub fn in_int_ena_ch5(&self) -> &IN_INT_ENA_CH5

0xa14 - RX CH5 interrupt ena register

pub fn in_int_st_ch5(&self) -> &IN_INT_ST_CH5

0xa18 - RX CH5 interrupt st register

pub fn in_int_clr_ch5(&self) -> &IN_INT_CLR_CH5

0xa1c - RX CH5 interrupt clr register

pub fn infifo_status_ch5(&self) -> &INFIFO_STATUS_CH5

0xa20 - RX CH5 INFIFO status register

pub fn in_pop_ch5(&self) -> &IN_POP_CH5

0xa24 - RX CH5 INFIFO pop register

pub fn in_state_ch5(&self) -> &IN_STATE_CH5

0xa28 - RX CH5 state register

pub fn in_arb_ch5(&self) -> &IN_ARB_CH5

0xa40 - RX CH5 arb register

pub fn in_fifo_cnt_ch5(&self) -> &IN_FIFO_CNT_CH5

0xa80 - rx CH5 fifo cnt register

pub fn in_pop_data_cnt_ch5(&self) -> &IN_POP_DATA_CNT_CH5

0xa84 - rx CH5 pop data cnt register

pub fn in_xaddr_ch5(&self) -> &IN_XADDR_CH5

0xa88 - rx CH5 xaddr register

pub fn in_buf_hb_rcv_ch5(&self) -> &IN_BUF_HB_RCV_CH5

0xa8c - rx CH5 buf len hb rcv register

pub fn inter_axi_err(&self) -> &INTER_AXI_ERR

0xb00 - inter memory axi err register

pub fn exter_axi_err(&self) -> &EXTER_AXI_ERR

0xb04 - exter memory axi err register

pub fn rst_conf(&self) -> &RST_CONF

0xb08 - axi reset config register

pub fn inter_mem_start_addr0(&self) -> &INTER_MEM_START_ADDR0

0xb0c - Start address of inter memory range0 register

pub fn inter_mem_end_addr0(&self) -> &INTER_MEM_END_ADDR0

0xb10 - end address of inter memory range0 register

pub fn inter_mem_start_addr1(&self) -> &INTER_MEM_START_ADDR1

0xb14 - Start address of inter memory range1 register

pub fn inter_mem_end_addr1(&self) -> &INTER_MEM_END_ADDR1

0xb18 - end address of inter memory range1 register

pub fn exter_mem_start_addr0(&self) -> &EXTER_MEM_START_ADDR0

0xb20 - Start address of exter memory range0 register

pub fn exter_mem_end_addr0(&self) -> &EXTER_MEM_END_ADDR0

0xb24 - end address of exter memory range0 register

pub fn exter_mem_start_addr1(&self) -> &EXTER_MEM_START_ADDR1

0xb28 - Start address of exter memory range1 register

pub fn exter_mem_end_addr1(&self) -> &EXTER_MEM_END_ADDR1

0xb2c - end address of exter memory range1 register

pub fn out_arb_config(&self) -> &OUT_ARB_CONFIG

0xb30 - reserved

pub fn in_arb_config(&self) -> &IN_ARB_CONFIG

0xb34 - reserved

pub fn date(&self) -> &DATE

0xb3c - reserved

pub fn counter_rst(&self) -> &COUNTER_RST

0xb50 - counter reset register

pub fn rx_ch0_counter(&self) -> &RX_CH0_COUNTER

0xb54 - rx ch0 counter register

pub fn rx_ch1_counter(&self) -> &RX_CH1_COUNTER

0xb58 - rx ch1 counter register

pub fn rx_ch2_counter(&self) -> &RX_CH2_COUNTER

0xb5c - rx ch2 counter register

pub fn rx_ch5_counter(&self) -> &RX_CH5_COUNTER

0xb60 - rx ch5 counter register

Trait Implementations

impl Debug for H264_DMA

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for H264_DMA

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for H264_DMA