Struct esp32p4::AXI_DMA

pub struct AXI_DMA { /* private fields */ }

AXI_DMA Peripheral

Implementations

impl AXI_DMA

pub const PTR: *const RegisterBlock = {0x5008a000 as *const axi_dma::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> Self

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn in_int_raw_ch(&self, n: usize) -> &IN_INT_RAW_CH

0x00..0x0c - Raw status interrupt of channel 0

pub fn in_int_raw_ch_iter(&self) -> impl Iterator<Item = &IN_INT_RAW_CH>

Iterator for array of: 0x00..0x0c - Raw status interrupt of channel 0

pub fn in_int_st_ch(&self, n: usize) -> &IN_INT_ST_CH

0x04..0x10 - Masked interrupt of channel 0

pub fn in_int_st_ch_iter(&self) -> impl Iterator<Item = &IN_INT_ST_CH>

Iterator for array of: 0x04..0x10 - Masked interrupt of channel 0

pub fn in_int_ena_ch(&self, n: usize) -> &IN_INT_ENA_CH

0x08..0x14 - Interrupt enable bits of channel 0

pub fn in_int_ena_ch_iter(&self) -> impl Iterator<Item = &IN_INT_ENA_CH>

Iterator for array of: 0x08..0x14 - Interrupt enable bits of channel 0

pub fn in_int_clr_ch(&self, n: usize) -> &IN_INT_CLR_CH

0x0c..0x18 - Interrupt clear bits of channel 0

pub fn in_int_clr_ch_iter(&self) -> impl Iterator<Item = &IN_INT_CLR_CH>

Iterator for array of: 0x0c..0x18 - Interrupt clear bits of channel 0

pub fn in_conf0_ch(&self, n: usize) -> &IN_CONF0_CH

0x10..0x1c - Configure 0 register of Rx channel 0

pub fn in_conf0_ch_iter(&self) -> impl Iterator<Item = &IN_CONF0_CH>

Iterator for array of: 0x10..0x1c - Configure 0 register of Rx channel 0

pub fn in_conf1_ch(&self, n: usize) -> &IN_CONF1_CH

0x14..0x20 - Configure 1 register of Rx channel 0

pub fn in_conf1_ch_iter(&self) -> impl Iterator<Item = &IN_CONF1_CH>

Iterator for array of: 0x14..0x20 - Configure 1 register of Rx channel 0

pub fn infifo_status_ch(&self, n: usize) -> &INFIFO_STATUS_CH

0x18..0x24 - Receive FIFO status of Rx channel 0

pub fn infifo_status_ch_iter(&self) -> impl Iterator<Item = &INFIFO_STATUS_CH>

Iterator for array of: 0x18..0x24 - Receive FIFO status of Rx channel 0

pub fn in_pop_ch(&self, n: usize) -> &IN_POP_CH

0x1c..0x28 - Pop control register of Rx channel 0

pub fn in_pop_ch_iter(&self) -> impl Iterator<Item = &IN_POP_CH>

Iterator for array of: 0x1c..0x28 - Pop control register of Rx channel 0

pub fn in_link1_ch(&self, n: usize) -> &IN_LINK1_CH

0x20..0x2c - Link descriptor configure and control register of Rx channel 0

pub fn in_link1_ch_iter(&self) -> impl Iterator<Item = &IN_LINK1_CH>

Iterator for array of: 0x20..0x2c - Link descriptor configure and control register of Rx channel 0

pub fn in_link2_ch(&self, n: usize) -> &IN_LINK2_CH

0x24..0x30 - Link descriptor configure and control register of Rx channel 0

pub fn in_link2_ch_iter(&self) -> impl Iterator<Item = &IN_LINK2_CH>

Iterator for array of: 0x24..0x30 - Link descriptor configure and control register of Rx channel 0

pub fn in_state_ch(&self, n: usize) -> &IN_STATE_CH

0x28..0x34 - Receive status of Rx channel 0

pub fn in_state_ch_iter(&self) -> impl Iterator<Item = &IN_STATE_CH>

Iterator for array of: 0x28..0x34 - Receive status of Rx channel 0

pub fn in_suc_eof_des_addr_ch(&self, n: usize) -> &IN_SUC_EOF_DES_ADDR_CH

0x2c..0x38 - Inlink descriptor address when EOF occurs of Rx channel 0

pub fn in_suc_eof_des_addr_ch_iter( &self ) -> impl Iterator<Item = &IN_SUC_EOF_DES_ADDR_CH>

Iterator for array of: 0x2c..0x38 - Inlink descriptor address when EOF occurs of Rx channel 0

pub fn in_err_eof_des_addr_ch(&self, n: usize) -> &IN_ERR_EOF_DES_ADDR_CH

0x30..0x3c - Inlink descriptor address when errors occur of Rx channel 0

pub fn in_err_eof_des_addr_ch_iter( &self ) -> impl Iterator<Item = &IN_ERR_EOF_DES_ADDR_CH>

Iterator for array of: 0x30..0x3c - Inlink descriptor address when errors occur of Rx channel 0

pub fn in_dscr_ch(&self, n: usize) -> &IN_DSCR_CH

0x34..0x40 - Current inlink descriptor address of Rx channel 0

pub fn in_dscr_ch_iter(&self) -> impl Iterator<Item = &IN_DSCR_CH>

Iterator for array of: 0x34..0x40 - Current inlink descriptor address of Rx channel 0

pub fn in_dscr_bf0_ch(&self, n: usize) -> &IN_DSCR_BF0_CH

0x38..0x44 - The last inlink descriptor address of Rx channel 0

pub fn in_dscr_bf0_ch_iter(&self) -> impl Iterator<Item = &IN_DSCR_BF0_CH>

Iterator for array of: 0x38..0x44 - The last inlink descriptor address of Rx channel 0

pub fn in_dscr_bf1_ch(&self, n: usize) -> &IN_DSCR_BF1_CH

0x3c..0x48 - The second-to-last inlink descriptor address of Rx channel 0

pub fn in_dscr_bf1_ch_iter(&self) -> impl Iterator<Item = &IN_DSCR_BF1_CH>

Iterator for array of: 0x3c..0x48 - The second-to-last inlink descriptor address of Rx channel 0

pub fn in_pri_ch(&self, n: usize) -> &IN_PRI_CH

0x40..0x4c - Priority register of Rx channel 0

pub fn in_pri_ch_iter(&self) -> impl Iterator<Item = &IN_PRI_CH>

Iterator for array of: 0x40..0x4c - Priority register of Rx channel 0

pub fn in_peri_sel_ch(&self, n: usize) -> &IN_PERI_SEL_CH

0x44..0x50 - Peripheral selection of Rx channel 0

pub fn in_peri_sel_ch_iter(&self) -> impl Iterator<Item = &IN_PERI_SEL_CH>

Iterator for array of: 0x44..0x50 - Peripheral selection of Rx channel 0

pub fn in_crc_init_data_ch(&self, n: usize) -> &IN_CRC_INIT_DATA_CH

0x48..0x54 - This register is used to config ch0 crc initial data(max 32 bit)

pub fn in_crc_init_data_ch_iter( &self ) -> impl Iterator<Item = &IN_CRC_INIT_DATA_CH>

Iterator for array of: 0x48..0x54 - This register is used to config ch0 crc initial data(max 32 bit)

pub fn rx_crc_width_ch(&self, n: usize) -> &RX_CRC_WIDTH_CH

0x4c..0x58 - This register is used to confiig rx ch0 crc result width,2’b00 mean crc_width <=8bit,2’b01 8<crc_width<=16 ,2’b10 mean 16<crc_width <=24,2’b11 mean 24<crc_width<=32

pub fn rx_crc_width_ch_iter(&self) -> impl Iterator<Item = &RX_CRC_WIDTH_CH>

Iterator for array of: 0x4c..0x58 - This register is used to confiig rx ch0 crc result width,2’b00 mean crc_width <=8bit,2’b01 8<crc_width<=16 ,2’b10 mean 16<crc_width <=24,2’b11 mean 24<crc_width<=32

pub fn in_crc_clear_ch(&self, n: usize) -> &IN_CRC_CLEAR_CH

0x50..0x5c - This register is used to clear ch0 crc result

pub fn in_crc_clear_ch_iter(&self) -> impl Iterator<Item = &IN_CRC_CLEAR_CH>

Iterator for array of: 0x50..0x5c - This register is used to clear ch0 crc result

pub fn in_crc_final_result_ch(&self, n: usize) -> &IN_CRC_FINAL_RESULT_CH

0x54..0x60 - This register is used to store ch0 crc result

pub fn in_crc_final_result_ch_iter( &self ) -> impl Iterator<Item = &IN_CRC_FINAL_RESULT_CH>

Iterator for array of: 0x54..0x60 - This register is used to store ch0 crc result

pub fn rx_crc_en_wr_data_ch(&self, n: usize) -> &RX_CRC_EN_WR_DATA_CH

0x58..0x64 - This resister is used to config ch0 crc en for every bit

pub fn rx_crc_en_wr_data_ch_iter( &self ) -> impl Iterator<Item = &RX_CRC_EN_WR_DATA_CH>

Iterator for array of: 0x58..0x64 - This resister is used to config ch0 crc en for every bit

pub fn rx_crc_en_addr_ch(&self, n: usize) -> &RX_CRC_EN_ADDR_CH

0x5c..0x68 - This register is used to config ch0 crc en addr

pub fn rx_crc_en_addr_ch_iter(&self) -> impl Iterator<Item = &RX_CRC_EN_ADDR_CH>

Iterator for array of: 0x5c..0x68 - This register is used to config ch0 crc en addr

pub fn rx_crc_data_en_wr_data_ch(&self, n: usize) -> &RX_CRC_DATA_EN_WR_DATA_CH

0x60..0x6c - This register is used to config crc data_8bit en

pub fn rx_crc_data_en_wr_data_ch_iter( &self ) -> impl Iterator<Item = &RX_CRC_DATA_EN_WR_DATA_CH>

Iterator for array of: 0x60..0x6c - This register is used to config crc data_8bit en

pub fn rx_crc_data_en_addr_ch(&self, n: usize) -> &RX_CRC_DATA_EN_ADDR_CH

0x64..0x70 - This register is used to config addr of crc data_8bit en

pub fn rx_crc_data_en_addr_ch_iter( &self ) -> impl Iterator<Item = &RX_CRC_DATA_EN_ADDR_CH>

Iterator for array of: 0x64..0x70 - This register is used to config addr of crc data_8bit en

pub fn out_int_raw_ch(&self, n: usize) -> &OUT_INT_RAW_CH

0x138..0x144 - Raw status interrupt of channel0

pub fn out_int_raw_ch_iter(&self) -> impl Iterator<Item = &OUT_INT_RAW_CH>

Iterator for array of: 0x138..0x144 - Raw status interrupt of channel0

pub fn out_int_st_ch(&self, n: usize) -> &OUT_INT_ST_CH

0x13c..0x148 - Masked interrupt of channel0

pub fn out_int_st_ch_iter(&self) -> impl Iterator<Item = &OUT_INT_ST_CH>

Iterator for array of: 0x13c..0x148 - Masked interrupt of channel0

pub fn out_int_ena_ch(&self, n: usize) -> &OUT_INT_ENA_CH

0x140..0x14c - Interrupt enable bits of channel0

pub fn out_int_ena_ch_iter(&self) -> impl Iterator<Item = &OUT_INT_ENA_CH>

Iterator for array of: 0x140..0x14c - Interrupt enable bits of channel0

pub fn out_int_clr_ch(&self, n: usize) -> &OUT_INT_CLR_CH

0x144..0x150 - Interrupt clear bits of channel0

pub fn out_int_clr_ch_iter(&self) -> impl Iterator<Item = &OUT_INT_CLR_CH>

Iterator for array of: 0x144..0x150 - Interrupt clear bits of channel0

pub fn out_conf0_ch0(&self) -> &OUT_CONF0_CH0

0x148 - Configure 0 register of Tx channel0

pub fn out_conf1_ch(&self, n: usize) -> &OUT_CONF1_CH

0x14c..0x158 - Configure 1 register of Tx channel0

pub fn out_conf1_ch_iter(&self) -> impl Iterator<Item = &OUT_CONF1_CH>

Iterator for array of: 0x14c..0x158 - Configure 1 register of Tx channel0

pub fn outfifo_status_ch(&self, n: usize) -> &OUTFIFO_STATUS_CH

0x150..0x15c - Transmit FIFO status of Tx channel0

pub fn outfifo_status_ch_iter(&self) -> impl Iterator<Item = &OUTFIFO_STATUS_CH>

Iterator for array of: 0x150..0x15c - Transmit FIFO status of Tx channel0

pub fn out_push_ch(&self, n: usize) -> &OUT_PUSH_CH

0x154..0x160 - Push control register of Tx channel0

pub fn out_push_ch_iter(&self) -> impl Iterator<Item = &OUT_PUSH_CH>

Iterator for array of: 0x154..0x160 - Push control register of Tx channel0

pub fn out_link1_ch(&self, n: usize) -> &OUT_LINK1_CH

0x158..0x164 - Link descriptor configure and control register of Tx channel0

pub fn out_link1_ch_iter(&self) -> impl Iterator<Item = &OUT_LINK1_CH>

Iterator for array of: 0x158..0x164 - Link descriptor configure and control register of Tx channel0

pub fn out_link2_ch(&self, n: usize) -> &OUT_LINK2_CH

0x15c..0x168 - Link descriptor configure and control register of Tx channel0

pub fn out_link2_ch_iter(&self) -> impl Iterator<Item = &OUT_LINK2_CH>

Iterator for array of: 0x15c..0x168 - Link descriptor configure and control register of Tx channel0

pub fn out_state_ch(&self, n: usize) -> &OUT_STATE_CH

0x160..0x16c - Transmit status of Tx channel0

pub fn out_state_ch_iter(&self) -> impl Iterator<Item = &OUT_STATE_CH>

Iterator for array of: 0x160..0x16c - Transmit status of Tx channel0

pub fn out_eof_des_addr_ch(&self, n: usize) -> &OUT_EOF_DES_ADDR_CH

0x164..0x170 - Outlink descriptor address when EOF occurs of Tx channel0

pub fn out_eof_des_addr_ch_iter( &self ) -> impl Iterator<Item = &OUT_EOF_DES_ADDR_CH>

Iterator for array of: 0x164..0x170 - Outlink descriptor address when EOF occurs of Tx channel0

pub fn out_eof_bfr_des_addr_ch(&self, n: usize) -> &OUT_EOF_BFR_DES_ADDR_CH

0x168..0x174 - The last outlink descriptor address when EOF occurs of Tx channel0

pub fn out_eof_bfr_des_addr_ch_iter( &self ) -> impl Iterator<Item = &OUT_EOF_BFR_DES_ADDR_CH>

Iterator for array of: 0x168..0x174 - The last outlink descriptor address when EOF occurs of Tx channel0

pub fn out_dscr_ch(&self, n: usize) -> &OUT_DSCR_CH

0x16c..0x178 - Current outlink descriptor address of Tx channel0

pub fn out_dscr_ch_iter(&self) -> impl Iterator<Item = &OUT_DSCR_CH>

Iterator for array of: 0x16c..0x178 - Current outlink descriptor address of Tx channel0

pub fn out_dscr_bf0_ch(&self, n: usize) -> &OUT_DSCR_BF0_CH

0x170..0x17c - The last outlink descriptor address of Tx channel0

pub fn out_dscr_bf0_ch_iter(&self) -> impl Iterator<Item = &OUT_DSCR_BF0_CH>

Iterator for array of: 0x170..0x17c - The last outlink descriptor address of Tx channel0

pub fn out_dscr_bf1_ch(&self, n: usize) -> &OUT_DSCR_BF1_CH

0x174..0x180 - The second-to-last outlink descriptor address of Tx channel0

pub fn out_dscr_bf1_ch_iter(&self) -> impl Iterator<Item = &OUT_DSCR_BF1_CH>

Iterator for array of: 0x174..0x180 - The second-to-last outlink descriptor address of Tx channel0

pub fn out_pri_ch(&self, n: usize) -> &OUT_PRI_CH

0x178..0x184 - Priority register of Tx channel0.

pub fn out_pri_ch_iter(&self) -> impl Iterator<Item = &OUT_PRI_CH>

Iterator for array of: 0x178..0x184 - Priority register of Tx channel0.

pub fn out_peri_sel_ch(&self, n: usize) -> &OUT_PERI_SEL_CH

0x17c..0x188 - Peripheral selection of Tx channel0

pub fn out_peri_sel_ch_iter(&self) -> impl Iterator<Item = &OUT_PERI_SEL_CH>

Iterator for array of: 0x17c..0x188 - Peripheral selection of Tx channel0

pub fn out_crc_init_data_ch(&self, n: usize) -> &OUT_CRC_INIT_DATA_CH

0x180..0x18c - This register is used to config ch0 crc initial data(max 32 bit)

pub fn out_crc_init_data_ch_iter( &self ) -> impl Iterator<Item = &OUT_CRC_INIT_DATA_CH>

Iterator for array of: 0x180..0x18c - This register is used to config ch0 crc initial data(max 32 bit)

pub fn tx_crc_width_ch(&self, n: usize) -> &TX_CRC_WIDTH_CH

0x184..0x190 - This register is used to confiig tx ch0 crc result width,2’b00 mean crc_width <=8bit,2’b01 8<crc_width<=16 ,2’b10 mean 16<crc_width <=24,2’b11 mean 24<crc_width<=32

pub fn tx_crc_width_ch_iter(&self) -> impl Iterator<Item = &TX_CRC_WIDTH_CH>

Iterator for array of: 0x184..0x190 - This register is used to confiig tx ch0 crc result width,2’b00 mean crc_width <=8bit,2’b01 8<crc_width<=16 ,2’b10 mean 16<crc_width <=24,2’b11 mean 24<crc_width<=32

pub fn out_crc_clear_ch(&self, n: usize) -> &OUT_CRC_CLEAR_CH

0x188..0x194 - This register is used to clear ch0 crc result

pub fn out_crc_clear_ch_iter(&self) -> impl Iterator<Item = &OUT_CRC_CLEAR_CH>

Iterator for array of: 0x188..0x194 - This register is used to clear ch0 crc result

pub fn out_crc_final_result_ch(&self, n: usize) -> &OUT_CRC_FINAL_RESULT_CH

0x18c..0x198 - This register is used to store ch0 crc result

pub fn out_crc_final_result_ch_iter( &self ) -> impl Iterator<Item = &OUT_CRC_FINAL_RESULT_CH>

Iterator for array of: 0x18c..0x198 - This register is used to store ch0 crc result

pub fn tx_crc_en_wr_data_ch(&self, n: usize) -> &TX_CRC_EN_WR_DATA_CH

0x190..0x19c - This resister is used to config ch0 crc en for every bit

pub fn tx_crc_en_wr_data_ch_iter( &self ) -> impl Iterator<Item = &TX_CRC_EN_WR_DATA_CH>

Iterator for array of: 0x190..0x19c - This resister is used to config ch0 crc en for every bit

pub fn tx_crc_en_addr_ch(&self, n: usize) -> &TX_CRC_EN_ADDR_CH

0x194..0x1a0 - This register is used to config ch0 crc en addr

pub fn tx_crc_en_addr_ch_iter(&self) -> impl Iterator<Item = &TX_CRC_EN_ADDR_CH>

Iterator for array of: 0x194..0x1a0 - This register is used to config ch0 crc en addr

pub fn tx_crc_data_en_wr_data_ch(&self, n: usize) -> &TX_CRC_DATA_EN_WR_DATA_CH

0x198..0x1a4 - This register is used to config crc data_8bit en

pub fn tx_crc_data_en_wr_data_ch_iter( &self ) -> impl Iterator<Item = &TX_CRC_DATA_EN_WR_DATA_CH>

Iterator for array of: 0x198..0x1a4 - This register is used to config crc data_8bit en

pub fn tx_crc_data_en_addr_ch(&self, n: usize) -> &TX_CRC_DATA_EN_ADDR_CH

0x19c..0x1a8 - This register is used to config addr of crc data_8bit en

pub fn tx_crc_data_en_addr_ch_iter( &self ) -> impl Iterator<Item = &TX_CRC_DATA_EN_ADDR_CH>

Iterator for array of: 0x19c..0x1a8 - This register is used to config addr of crc data_8bit en

pub fn out_conf0_ch1(&self) -> &OUT_CONF0_CH1

0x1b0 - Configure 0 register of Tx channel1

pub fn out_conf0_ch2(&self) -> &OUT_CONF0_CH2

0x218 - Configure 0 register of Tx channel2

pub fn arb_timeout(&self) -> &ARB_TIMEOUT

0x270 - This retister is used to config arbiter time slice

pub fn weight_en(&self) -> &WEIGHT_EN

0x274 - This register is used to config arbiter weight function to on or off

pub fn in_mem_conf(&self) -> &IN_MEM_CONF

0x278 - Mem power configure register of Rx channel

pub fn intr_mem_start_addr(&self) -> &INTR_MEM_START_ADDR

0x27c - The start address of accessible address space.

pub fn intr_mem_end_addr(&self) -> &INTR_MEM_END_ADDR

0x280 - The end address of accessible address space. The access address beyond this range would lead to descriptor error.

pub fn extr_mem_start_addr(&self) -> &EXTR_MEM_START_ADDR

0x284 - The start address of accessible address space.

pub fn extr_mem_end_addr(&self) -> &EXTR_MEM_END_ADDR

0x288 - The end address of accessible address space. The access address beyond this range would lead to descriptor error.

pub fn in_reset_avail_ch(&self, n: usize) -> &IN_RESET_AVAIL_CH

0x28c..0x298 - The rx channel 0 reset valid_flag register.

pub fn in_reset_avail_ch_iter(&self) -> impl Iterator<Item = &IN_RESET_AVAIL_CH>

Iterator for array of: 0x28c..0x298 - The rx channel 0 reset valid_flag register.

pub fn out_reset_avail_ch(&self, n: usize) -> &OUT_RESET_AVAIL_CH

0x298..0x2a4 - The tx channel 0 reset valid_flag register.

pub fn out_reset_avail_ch_iter( &self ) -> impl Iterator<Item = &OUT_RESET_AVAIL_CH>

Iterator for array of: 0x298..0x2a4 - The tx channel 0 reset valid_flag register.

pub fn misc_conf(&self) -> &MISC_CONF

0x2a8 - MISC register

pub fn rdn_result(&self) -> &RDN_RESULT

0x2ac - reserved

pub fn rdn_eco_high(&self) -> &RDN_ECO_HIGH

0x2b0 - reserved

pub fn rdn_eco_low(&self) -> &RDN_ECO_LOW

0x2b4 - reserved

pub fn wresp_cnt(&self) -> &WRESP_CNT

0x2b8 - AXI wr responce cnt register.

pub fn rresp_cnt(&self) -> &RRESP_CNT

0x2bc - AXI wr responce cnt register.

pub fn infifo_status1_ch(&self, n: usize) -> &INFIFO_STATUS1_CH

0x2c0..0x2cc - Receive FIFO status of Rx channel 0

pub fn infifo_status1_ch_iter(&self) -> impl Iterator<Item = &INFIFO_STATUS1_CH>

Iterator for array of: 0x2c0..0x2cc - Receive FIFO status of Rx channel 0

pub fn outfifo_status1_ch(&self, n: usize) -> &OUTFIFO_STATUS1_CH

0x2cc..0x2d8 - Receive FIFO status of Tx channel 0

pub fn outfifo_status1_ch_iter( &self ) -> impl Iterator<Item = &OUTFIFO_STATUS1_CH>

Iterator for array of: 0x2cc..0x2d8 - Receive FIFO status of Tx channel 0

pub fn date(&self) -> &DATE

0x2d8 - Version control register

Trait Implementations

impl Debug for AXI_DMA

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for AXI_DMA

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for AXI_DMA