Type Alias esp32p4::spi1::spi_mem_ddr::W

pub type W = W<SPI_MEM_DDR_SPEC>;

Register SPI_MEM_DDR writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn spi_fmem_ddr_en(&mut self) -> SPI_FMEM_DDR_EN_W<'_, SPI_MEM_DDR_SPEC>

Bit 0 - 1: in ddr mode, 0 in sdr mode

pub fn spi_fmem_var_dummy( &mut self ) -> SPI_FMEM_VAR_DUMMY_W<'_, SPI_MEM_DDR_SPEC>

Bit 1 - Set the bit to enable variable dummy cycle in spi ddr mode.

pub fn spi_fmem_ddr_rdat_swp( &mut self ) -> SPI_FMEM_DDR_RDAT_SWP_W<'_, SPI_MEM_DDR_SPEC>

Bit 2 - Set the bit to reorder rx data of the word in spi ddr mode.

pub fn spi_fmem_ddr_wdat_swp( &mut self ) -> SPI_FMEM_DDR_WDAT_SWP_W<'_, SPI_MEM_DDR_SPEC>

Bit 3 - Set the bit to reorder tx data of the word in spi ddr mode.

pub fn spi_fmem_ddr_cmd_dis( &mut self ) -> SPI_FMEM_DDR_CMD_DIS_W<'_, SPI_MEM_DDR_SPEC>

Bit 4 - the bit is used to disable dual edge in command phase when ddr mode.

pub fn spi_fmem_outminbytelen( &mut self ) -> SPI_FMEM_OUTMINBYTELEN_W<'_, SPI_MEM_DDR_SPEC>

Bits 5:11 - It is the minimum output data length in the panda device.

pub fn spi_fmem_usr_ddr_dqs_thd( &mut self ) -> SPI_FMEM_USR_DDR_DQS_THD_W<'_, SPI_MEM_DDR_SPEC>

Bits 14:20 - The delay number of data strobe which from memory based on SPI clock.

pub fn spi_fmem_ddr_dqs_loop( &mut self ) -> SPI_FMEM_DDR_DQS_LOOP_W<'_, SPI_MEM_DDR_SPEC>

Bit 21 - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.

pub fn spi_fmem_clk_diff_en( &mut self ) -> SPI_FMEM_CLK_DIFF_EN_W<'_, SPI_MEM_DDR_SPEC>

Bit 24 - Set this bit to enable the differential SPI_CLK#.

pub fn spi_fmem_dqs_ca_in( &mut self ) -> SPI_FMEM_DQS_CA_IN_W<'_, SPI_MEM_DDR_SPEC>

Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.

pub fn spi_fmem_hyperbus_dummy_2x( &mut self ) -> SPI_FMEM_HYPERBUS_DUMMY_2X_W<'_, SPI_MEM_DDR_SPEC>

Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.

pub fn spi_fmem_clk_diff_inv( &mut self ) -> SPI_FMEM_CLK_DIFF_INV_W<'_, SPI_MEM_DDR_SPEC>

Bit 28 - Set this bit to invert SPI_DIFF when accesses to flash. .

pub fn spi_fmem_octa_ram_addr( &mut self ) -> SPI_FMEM_OCTA_RAM_ADDR_W<'_, SPI_MEM_DDR_SPEC>

Bit 29 - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6’d0, spi_usr_addr_value[3:1], 1’b0}.

pub fn spi_fmem_hyperbus_ca( &mut self ) -> SPI_FMEM_HYPERBUS_CA_W<'_, SPI_MEM_DDR_SPEC>

Bit 30 - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13’d0, spi_usr_addr_value[3:1]}.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual