Expand description
SPI0 external RAM control register
Structs§
- CACHE_
SCTRL_ SPEC - SPI0 external RAM control register
Type Aliases§
- CACHE_
SRAM_ USR_ RCMD_ R - Field
CACHE_SRAM_USR_RCMD
reader - For SPI0, In the external RAM mode cache read external RAM for user define command. - CACHE_
SRAM_ USR_ WCMD_ R - Field
CACHE_SRAM_USR_WCMD
reader - For SPI0, In the external RAM mode cache write sram for user define command - CACHE_
USR_ SADDR_ 4BYTE_ R - Field
CACHE_USR_SADDR_4BYTE
reader - For SPI0, In the external RAM mode, cache read flash with 4 bytes command, 1: enable, 0:disable. - R
- Register
CACHE_SCTRL
reader - SRAM_
ADDR_ BITLEN_ R - Field
SRAM_ADDR_BITLEN
reader - For SPI0, In the external RAM mode, it is the length in bits of address phase. The register value shall be (bit_num-1). - SRAM_
OCT_ R - Field
SRAM_OCT
reader - reserved - SRAM_
RDUMMY_ CYCLELEN_ R - Field
SRAM_RDUMMY_CYCLELEN
reader - For SPI0, In the external RAM mode, it is the length in bits of read dummy phase. The register value shall be (bit_num-1). - SRAM_
WDUMMY_ CYCLELEN_ R - Field
SRAM_WDUMMY_CYCLELEN
reader - For SPI0, In the external RAM mode, it is the length in bits of write dummy phase. The register value shall be (bit_num-1). - USR_
RD_ SRAM_ DUMMY_ R - Field
USR_RD_SRAM_DUMMY
reader - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for read operations. - USR_
SRAM_ DIO_ R - Field
USR_SRAM_DIO
reader - For SPI0, In the external RAM mode, spi dual I/O mode enable, 1: enable, 0:disable - USR_
SRAM_ QIO_ R - Field
USR_SRAM_QIO
reader - For SPI0, In the external RAM mode, spi quad I/O mode enable, 1: enable, 0:disable - USR_
WR_ SRAM_ DUMMY_ R - Field
USR_WR_SRAM_DUMMY
reader - For SPI0, In the external RAM mode, it is the enable bit of dummy phase for write operations.