Type Alias R

pub type R = R<CTRL2_SPEC>;

Register CTRL2 reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn cs_setup_time(&self) -> CS_SETUP_TIME_R

Bits 0:4 - (cycles-1) of prepare phase by SPI Bus clock, this bits are combined with SPI_MEM_CS_SETUP bit.

pub fn cs_hold_time(&self) -> CS_HOLD_TIME_R

Bits 5:9 - SPI CS signal is delayed to inactive by SPI bus clock, this bits are combined with SPI_MEM_CS_HOLD bit.

pub fn ecc_cs_hold_time(&self) -> ECC_CS_HOLD_TIME_R

Bits 10:12 - SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI0 CS hold cycle in ECC mode when accessed flash.

pub fn ecc_skip_page_corner(&self) -> ECC_SKIP_PAGE_CORNER_R

Bit 13 - 1: SPI0 and SPI1 skip page corner when accesses flash. 0: Not skip page corner when accesses flash.

pub fn ecc_16to18_byte_en(&self) -> ECC_16TO18_BYTE_EN_R

Bit 14 - Set this bit to enable SPI0 and SPI1 ECC 16 bytes data with 2 ECC bytes mode when accesses flash.

pub fn split_trans_en(&self) -> SPLIT_TRANS_EN_R

Bit 24 - Set this bit to enable SPI0 split one AXI read flash transfer into two SPI transfers when one transfer will cross flash or EXT_RAM page corner, valid no matter whether there is an ECC region or not.

pub fn cs_hold_delay(&self) -> CS_HOLD_DELAY_R

Bits 25:30 - These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.