Type Alias esp32h2::spi0::din_num::W

pub type W = W<DIN_NUM_SPEC>;

Register DIN_NUM writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn din0_num(&mut self) -> DIN0_NUM_W<'_, DIN_NUM_SPEC>

Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

pub fn din1_num(&mut self) -> DIN1_NUM_W<'_, DIN_NUM_SPEC>

Bits 2:3 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

pub fn din2_num(&mut self) -> DIN2_NUM_W<'_, DIN_NUM_SPEC>

Bits 4:5 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

pub fn din3_num(&mut self) -> DIN3_NUM_W<'_, DIN_NUM_SPEC>

Bits 6:7 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

pub fn din4_num(&mut self) -> DIN4_NUM_W<'_, DIN_NUM_SPEC>

Bits 8:9 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

pub fn din5_num(&mut self) -> DIN5_NUM_W<'_, DIN_NUM_SPEC>

Bits 10:11 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

pub fn din6_num(&mut self) -> DIN6_NUM_W<'_, DIN_NUM_SPEC>

Bits 12:13 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

pub fn din7_num(&mut self) -> DIN7_NUM_W<'_, DIN_NUM_SPEC>

Bits 14:15 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…

pub fn dins_num(&mut self) -> DINS_NUM_W<'_, DIN_NUM_SPEC>

Bits 16:17 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…