Type Alias esp32h2::spi0::ctrl1::W

pub type W = W<CTRL1_SPEC>;

Register CTRL1 writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn clk_mode(&mut self) -> CLK_MODE_W<'_, CTRL1_SPEC>

Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.

pub fn spi_ar_size0_1_support_en( &mut self ) -> SPI_AR_SIZE0_1_SUPPORT_EN_W<'_, CTRL1_SPEC>

Bit 21 - 1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.

pub fn spi_aw_size0_1_support_en( &mut self ) -> SPI_AW_SIZE0_1_SUPPORT_EN_W<'_, CTRL1_SPEC>

Bit 22 - 1: MSPI supports AWSIZE 0~3. 0: When AWSIZE 0~1, MSPI reply SLV_ERR.

pub fn rresp_ecc_err_en(&mut self) -> RRESP_ECC_ERR_EN_W<'_, CTRL1_SPEC>

Bit 24 - 1: RRESP is SLV_ERR when there is a ECC error in AXI read data. 0: RRESP is OKAY when there is a ECC error in AXI read data. The ECC error information is recorded in SPI_MEM_ECC_ERR_ADDR_REG.

pub fn fast_write_en(&mut self) -> FAST_WRITE_EN_W<'_, CTRL1_SPEC>

Bit 29 - Set this bit to write data faster, do not wait write data has been stored in tx_bus_fifo_l2. It will wait 4*T_clk_ctrl to insure the write data has been stored in tx_bus_fifo_l2.

pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W<'_, CTRL1_SPEC>

Bit 30 - The synchronous reset signal for SPI0 RX AFIFO and all the AES_MSPI SYNC FIFO to receive signals from AXI. Set this bit to reset these FIFO.

pub fn txfifo_rst(&mut self) -> TXFIFO_RST_W<'_, CTRL1_SPEC>

Bit 31 - The synchronous reset signal for SPI0 TX AFIFO and all the AES_MSPI SYNC FIFO to send signals to AXI. Set this bit to reset these FIFO.