Module esp32h2::mcpwm0::dt1_cfg

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dead time type selection and configuration

Structs§

Type Aliases§

  • Field DB1_A_OUTBYPASS reader - S1 in table
  • Field DB1_A_OUTBYPASS writer - S1 in table
  • Field DB1_A_OUTSWAP reader - S6 in table
  • Field DB1_A_OUTSWAP writer - S6 in table
  • Field DB1_B_OUTBYPASS reader - S0 in table
  • Field DB1_B_OUTBYPASS writer - S0 in table
  • Field DB1_B_OUTSWAP reader - S7 in table
  • Field DB1_B_OUTSWAP writer - S7 in table
  • Field DB1_CLK_SEL reader - Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk
  • Field DB1_CLK_SEL writer - Dead time generator 1 clock selection. 0: PWM_clk, 1: PT_clk
  • Field DB1_DEB_MODE reader - S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode
  • Field DB1_DEB_MODE writer - S8 in table, dual-edge B mode, 0: fed/red take effect on different path separately, 1: fed/red take effect on B path, A out is in bypass or dulpB mode
  • Field DB1_FED_INSEL reader - S5 in table
  • Field DB1_FED_INSEL writer - S5 in table
  • Field DB1_FED_OUTINVERT reader - S3 in table
  • Field DB1_FED_OUTINVERT writer - S3 in table
  • Field DB1_FED_UPMETHOD reader - Update method for FED (falling edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update
  • Field DB1_FED_UPMETHOD writer - Update method for FED (falling edge delay) active register. 0: immediate, when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update
  • Field DB1_RED_INSEL reader - S4 in table
  • Field DB1_RED_INSEL writer - S4 in table
  • Field DB1_RED_OUTINVERT reader - S2 in table
  • Field DB1_RED_OUTINVERT writer - S2 in table
  • Field DB1_RED_UPMETHOD reader - Update method for RED (rising edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update
  • Field DB1_RED_UPMETHOD writer - Update method for RED (rising edge delay) active register. 0: immediate,when bit0 is set to 1: tez, when bit1 is set to 1:tep, when bit2 is set to 1: sync, when bit3 is set to 1: disable the update
  • Register DT1_CFG reader
  • Register DT1_CFG writer