pub type R = R<INT_ENA_SPEC>;
Expand description
Register INT_ENA
reader
Aliased Type§
struct R { /* private fields */ }
Implementations§
source§impl R
impl R
sourcepub fn rxfifo_full_int_ena(&self) -> RXFIFO_FULL_INT_ENA_R
pub fn rxfifo_full_int_ena(&self) -> RXFIFO_FULL_INT_ENA_R
Bit 0 - This is the enable bit for rxfifo_full_int_st register.
sourcepub fn txfifo_empty_int_ena(&self) -> TXFIFO_EMPTY_INT_ENA_R
pub fn txfifo_empty_int_ena(&self) -> TXFIFO_EMPTY_INT_ENA_R
Bit 1 - This is the enable bit for txfifo_empty_int_st register.
sourcepub fn parity_err_int_ena(&self) -> PARITY_ERR_INT_ENA_R
pub fn parity_err_int_ena(&self) -> PARITY_ERR_INT_ENA_R
Bit 2 - This is the enable bit for parity_err_int_st register.
sourcepub fn frm_err_int_ena(&self) -> FRM_ERR_INT_ENA_R
pub fn frm_err_int_ena(&self) -> FRM_ERR_INT_ENA_R
Bit 3 - This is the enable bit for frm_err_int_st register.
sourcepub fn rxfifo_ovf_int_ena(&self) -> RXFIFO_OVF_INT_ENA_R
pub fn rxfifo_ovf_int_ena(&self) -> RXFIFO_OVF_INT_ENA_R
Bit 4 - This is the enable bit for rxfifo_ovf_int_st register.
sourcepub fn dsr_chg_int_ena(&self) -> DSR_CHG_INT_ENA_R
pub fn dsr_chg_int_ena(&self) -> DSR_CHG_INT_ENA_R
Bit 5 - This is the enable bit for dsr_chg_int_st register.
sourcepub fn cts_chg_int_ena(&self) -> CTS_CHG_INT_ENA_R
pub fn cts_chg_int_ena(&self) -> CTS_CHG_INT_ENA_R
Bit 6 - This is the enable bit for cts_chg_int_st register.
sourcepub fn brk_det_int_ena(&self) -> BRK_DET_INT_ENA_R
pub fn brk_det_int_ena(&self) -> BRK_DET_INT_ENA_R
Bit 7 - This is the enable bit for brk_det_int_st register.
sourcepub fn rxfifo_tout_int_ena(&self) -> RXFIFO_TOUT_INT_ENA_R
pub fn rxfifo_tout_int_ena(&self) -> RXFIFO_TOUT_INT_ENA_R
Bit 8 - This is the enable bit for rxfifo_tout_int_st register.
sourcepub fn sw_xon_int_ena(&self) -> SW_XON_INT_ENA_R
pub fn sw_xon_int_ena(&self) -> SW_XON_INT_ENA_R
Bit 9 - This is the enable bit for sw_xon_int_st register.
sourcepub fn sw_xoff_int_ena(&self) -> SW_XOFF_INT_ENA_R
pub fn sw_xoff_int_ena(&self) -> SW_XOFF_INT_ENA_R
Bit 10 - This is the enable bit for sw_xoff_int_st register.
sourcepub fn glitch_det_int_ena(&self) -> GLITCH_DET_INT_ENA_R
pub fn glitch_det_int_ena(&self) -> GLITCH_DET_INT_ENA_R
Bit 11 - This is the enable bit for glitch_det_int_st register.
sourcepub fn tx_brk_done_int_ena(&self) -> TX_BRK_DONE_INT_ENA_R
pub fn tx_brk_done_int_ena(&self) -> TX_BRK_DONE_INT_ENA_R
Bit 12 - This is the enable bit for tx_brk_done_int_st register.
sourcepub fn tx_brk_idle_done_int_ena(&self) -> TX_BRK_IDLE_DONE_INT_ENA_R
pub fn tx_brk_idle_done_int_ena(&self) -> TX_BRK_IDLE_DONE_INT_ENA_R
Bit 13 - This is the enable bit for tx_brk_idle_done_int_st register.
sourcepub fn tx_done_int_ena(&self) -> TX_DONE_INT_ENA_R
pub fn tx_done_int_ena(&self) -> TX_DONE_INT_ENA_R
Bit 14 - This is the enable bit for tx_done_int_st register.
sourcepub fn rs485_parity_err_int_ena(&self) -> RS485_PARITY_ERR_INT_ENA_R
pub fn rs485_parity_err_int_ena(&self) -> RS485_PARITY_ERR_INT_ENA_R
Bit 15 - This is the enable bit for rs485_parity_err_int_st register.
sourcepub fn rs485_frm_err_int_ena(&self) -> RS485_FRM_ERR_INT_ENA_R
pub fn rs485_frm_err_int_ena(&self) -> RS485_FRM_ERR_INT_ENA_R
Bit 16 - This is the enable bit for rs485_parity_err_int_st register.
sourcepub fn rs485_clash_int_ena(&self) -> RS485_CLASH_INT_ENA_R
pub fn rs485_clash_int_ena(&self) -> RS485_CLASH_INT_ENA_R
Bit 17 - This is the enable bit for rs485_clash_int_st register.
sourcepub fn at_cmd_char_det_int_ena(&self) -> AT_CMD_CHAR_DET_INT_ENA_R
pub fn at_cmd_char_det_int_ena(&self) -> AT_CMD_CHAR_DET_INT_ENA_R
Bit 18 - This is the enable bit for at_cmd_char_det_int_st register.
sourcepub fn wakeup_int_ena(&self) -> WAKEUP_INT_ENA_R
pub fn wakeup_int_ena(&self) -> WAKEUP_INT_ENA_R
Bit 19 - This is the enable bit for uart_wakeup_int_st register.