Type Alias esp32h2::uhci0::conf0::R

pub type R = R<CONF0_SPEC>;

Register CONF0 reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn tx_rst(&self) -> TX_RST_R

Bit 0 - Write 1 then write 0 to this bit to reset decode state machine.

pub fn rx_rst(&self) -> RX_RST_R

Bit 1 - Write 1 then write 0 to this bit to reset encode state machine.

pub fn uart0_ce(&self) -> UART0_CE_R

Bit 2 - Set this bit to link up HCI and UART0.

pub fn uart1_ce(&self) -> UART1_CE_R

Bit 3 - Set this bit to link up HCI and UART1.

pub fn seper_en(&self) -> SEPER_EN_R

Bit 5 - Set this bit to separate the data frame using a special char.

pub fn head_en(&self) -> HEAD_EN_R

Bit 6 - Set this bit to encode the data packet with a formatting header.

pub fn crc_rec_en(&self) -> CRC_REC_EN_R

Bit 7 - Set this bit to enable UHCI to receive the 16 bit CRC.

pub fn uart_idle_eof_en(&self) -> UART_IDLE_EOF_EN_R

Bit 8 - If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state.

pub fn len_eof_en(&self) -> LEN_EOF_EN_R

Bit 9 - If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received.

pub fn encode_crc_en(&self) -> ENCODE_CRC_EN_R

Bit 10 - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.

pub fn clk_en(&self) -> CLK_EN_R

Bit 11 - 1’b1: Force clock on for register. 1’b0: Support clock only when application writes registers.

pub fn uart_rx_brk_eof_en(&self) -> UART_RX_BRK_EOF_EN_R

Bit 12 - If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART.