Type Alias esp32h2::uart0::int_raw::W

pub type W = W<INT_RAW_SPEC>;

Register INT_RAW writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn rxfifo_full_int_raw( &mut self ) -> RXFIFO_FULL_INT_RAW_W<'_, INT_RAW_SPEC, 0>

Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.

pub fn txfifo_empty_int_raw( &mut self ) -> TXFIFO_EMPTY_INT_RAW_W<'_, INT_RAW_SPEC, 1>

Bit 1 - This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .

pub fn parity_err_int_raw( &mut self ) -> PARITY_ERR_INT_RAW_W<'_, INT_RAW_SPEC, 2>

Bit 2 - This interrupt raw bit turns to high level when receiver detects a parity error in the data.

pub fn frm_err_int_raw(&mut self) -> FRM_ERR_INT_RAW_W<'_, INT_RAW_SPEC, 3>

Bit 3 - This interrupt raw bit turns to high level when receiver detects a data frame error .

pub fn rxfifo_ovf_int_raw( &mut self ) -> RXFIFO_OVF_INT_RAW_W<'_, INT_RAW_SPEC, 4>

Bit 4 - This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.

pub fn dsr_chg_int_raw(&mut self) -> DSR_CHG_INT_RAW_W<'_, INT_RAW_SPEC, 5>

Bit 5 - This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.

pub fn cts_chg_int_raw(&mut self) -> CTS_CHG_INT_RAW_W<'_, INT_RAW_SPEC, 6>

Bit 6 - This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.

pub fn brk_det_int_raw(&mut self) -> BRK_DET_INT_RAW_W<'_, INT_RAW_SPEC, 7>

Bit 7 - This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.

pub fn rxfifo_tout_int_raw( &mut self ) -> RXFIFO_TOUT_INT_RAW_W<'_, INT_RAW_SPEC, 8>

Bit 8 - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.

pub fn sw_xon_int_raw(&mut self) -> SW_XON_INT_RAW_W<'_, INT_RAW_SPEC, 9>

Bit 9 - This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.

pub fn sw_xoff_int_raw(&mut self) -> SW_XOFF_INT_RAW_W<'_, INT_RAW_SPEC, 10>

Bit 10 - This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.

pub fn glitch_det_int_raw( &mut self ) -> GLITCH_DET_INT_RAW_W<'_, INT_RAW_SPEC, 11>

Bit 11 - This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.

pub fn tx_brk_done_int_raw( &mut self ) -> TX_BRK_DONE_INT_RAW_W<'_, INT_RAW_SPEC, 12>

Bit 12 - This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent.

pub fn tx_brk_idle_done_int_raw( &mut self ) -> TX_BRK_IDLE_DONE_INT_RAW_W<'_, INT_RAW_SPEC, 13>

Bit 13 - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data.

pub fn tx_done_int_raw(&mut self) -> TX_DONE_INT_RAW_W<'_, INT_RAW_SPEC, 14>

Bit 14 - This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.

pub fn rs485_parity_err_int_raw( &mut self ) -> RS485_PARITY_ERR_INT_RAW_W<'_, INT_RAW_SPEC, 15>

Bit 15 - This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.

pub fn rs485_frm_err_int_raw( &mut self ) -> RS485_FRM_ERR_INT_RAW_W<'_, INT_RAW_SPEC, 16>

Bit 16 - This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.

pub fn rs485_clash_int_raw( &mut self ) -> RS485_CLASH_INT_RAW_W<'_, INT_RAW_SPEC, 17>

Bit 17 - This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.

pub fn at_cmd_char_det_int_raw( &mut self ) -> AT_CMD_CHAR_DET_INT_RAW_W<'_, INT_RAW_SPEC, 18>

Bit 18 - This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.

pub fn wakeup_int_raw(&mut self) -> WAKEUP_INT_RAW_W<'_, INT_RAW_SPEC, 19>

Bit 19 - This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual