Type Alias esp32h2::mcpwm0::int_clr::W

pub type W = W<INT_CLR_SPEC>;

Register INT_CLR writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn timer0_stop_int_clr( &mut self ) -> TIMER0_STOP_INT_CLR_W<'_, INT_CLR_SPEC, 0>

Bit 0 - Set this bit to clear the interrupt triggered when the timer 0 stops.

pub fn timer1_stop_int_clr( &mut self ) -> TIMER1_STOP_INT_CLR_W<'_, INT_CLR_SPEC, 1>

Bit 1 - Set this bit to clear the interrupt triggered when the timer 1 stops.

pub fn timer2_stop_int_clr( &mut self ) -> TIMER2_STOP_INT_CLR_W<'_, INT_CLR_SPEC, 2>

Bit 2 - Set this bit to clear the interrupt triggered when the timer 2 stops.

pub fn timer0_tez_int_clr( &mut self ) -> TIMER0_TEZ_INT_CLR_W<'_, INT_CLR_SPEC, 3>

Bit 3 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEZ event.

pub fn timer1_tez_int_clr( &mut self ) -> TIMER1_TEZ_INT_CLR_W<'_, INT_CLR_SPEC, 4>

Bit 4 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEZ event.

pub fn timer2_tez_int_clr( &mut self ) -> TIMER2_TEZ_INT_CLR_W<'_, INT_CLR_SPEC, 5>

Bit 5 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEZ event.

pub fn timer0_tep_int_clr( &mut self ) -> TIMER0_TEP_INT_CLR_W<'_, INT_CLR_SPEC, 6>

Bit 6 - Set this bit to clear the interrupt triggered by a PWM timer 0 TEP event.

pub fn timer1_tep_int_clr( &mut self ) -> TIMER1_TEP_INT_CLR_W<'_, INT_CLR_SPEC, 7>

Bit 7 - Set this bit to clear the interrupt triggered by a PWM timer 1 TEP event.

pub fn timer2_tep_int_clr( &mut self ) -> TIMER2_TEP_INT_CLR_W<'_, INT_CLR_SPEC, 8>

Bit 8 - Set this bit to clear the interrupt triggered by a PWM timer 2 TEP event.

pub fn fault0_int_clr(&mut self) -> FAULT0_INT_CLR_W<'_, INT_CLR_SPEC, 9>

Bit 9 - Set this bit to clear the interrupt triggered when event_f0 starts.

pub fn fault1_int_clr(&mut self) -> FAULT1_INT_CLR_W<'_, INT_CLR_SPEC, 10>

Bit 10 - Set this bit to clear the interrupt triggered when event_f1 starts.

pub fn fault2_int_clr(&mut self) -> FAULT2_INT_CLR_W<'_, INT_CLR_SPEC, 11>

Bit 11 - Set this bit to clear the interrupt triggered when event_f2 starts.

pub fn fault0_clr_int_clr( &mut self ) -> FAULT0_CLR_INT_CLR_W<'_, INT_CLR_SPEC, 12>

Bit 12 - Set this bit to clear the interrupt triggered when event_f0 ends.

pub fn fault1_clr_int_clr( &mut self ) -> FAULT1_CLR_INT_CLR_W<'_, INT_CLR_SPEC, 13>

Bit 13 - Set this bit to clear the interrupt triggered when event_f1 ends.

pub fn fault2_clr_int_clr( &mut self ) -> FAULT2_CLR_INT_CLR_W<'_, INT_CLR_SPEC, 14>

Bit 14 - Set this bit to clear the interrupt triggered when event_f2 ends.

pub fn cmpr0_tea_int_clr(&mut self) -> CMPR0_TEA_INT_CLR_W<'_, INT_CLR_SPEC, 15>

Bit 15 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEA event

pub fn cmpr1_tea_int_clr(&mut self) -> CMPR1_TEA_INT_CLR_W<'_, INT_CLR_SPEC, 16>

Bit 16 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEA event

pub fn cmpr2_tea_int_clr(&mut self) -> CMPR2_TEA_INT_CLR_W<'_, INT_CLR_SPEC, 17>

Bit 17 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEA event

pub fn cmpr0_teb_int_clr(&mut self) -> CMPR0_TEB_INT_CLR_W<'_, INT_CLR_SPEC, 18>

Bit 18 - Set this bit to clear the interrupt triggered by a PWM operator 0 TEB event

pub fn cmpr1_teb_int_clr(&mut self) -> CMPR1_TEB_INT_CLR_W<'_, INT_CLR_SPEC, 19>

Bit 19 - Set this bit to clear the interrupt triggered by a PWM operator 1 TEB event

pub fn cmpr2_teb_int_clr(&mut self) -> CMPR2_TEB_INT_CLR_W<'_, INT_CLR_SPEC, 20>

Bit 20 - Set this bit to clear the interrupt triggered by a PWM operator 2 TEB event

pub fn tz0_cbc_int_clr(&mut self) -> TZ0_CBC_INT_CLR_W<'_, INT_CLR_SPEC, 21>

Bit 21 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM0.

pub fn tz1_cbc_int_clr(&mut self) -> TZ1_CBC_INT_CLR_W<'_, INT_CLR_SPEC, 22>

Bit 22 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM1.

pub fn tz2_cbc_int_clr(&mut self) -> TZ2_CBC_INT_CLR_W<'_, INT_CLR_SPEC, 23>

Bit 23 - Set this bit to clear the interrupt triggered by a cycle-by-cycle mode action on PWM2.

pub fn tz0_ost_int_clr(&mut self) -> TZ0_OST_INT_CLR_W<'_, INT_CLR_SPEC, 24>

Bit 24 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM0.

pub fn tz1_ost_int_clr(&mut self) -> TZ1_OST_INT_CLR_W<'_, INT_CLR_SPEC, 25>

Bit 25 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM1.

pub fn tz2_ost_int_clr(&mut self) -> TZ2_OST_INT_CLR_W<'_, INT_CLR_SPEC, 26>

Bit 26 - Set this bit to clear the interrupt triggered by a one-shot mode action on PWM2.

pub fn cap0_int_clr(&mut self) -> CAP0_INT_CLR_W<'_, INT_CLR_SPEC, 27>

Bit 27 - Set this bit to clear the interrupt triggered by capture on channel 0.

pub fn cap1_int_clr(&mut self) -> CAP1_INT_CLR_W<'_, INT_CLR_SPEC, 28>

Bit 28 - Set this bit to clear the interrupt triggered by capture on channel 1.

pub fn cap2_int_clr(&mut self) -> CAP2_INT_CLR_W<'_, INT_CLR_SPEC, 29>

Bit 29 - Set this bit to clear the interrupt triggered by capture on channel 2.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual