Type Alias esp32h2::dma::in_int_raw_ch::W

pub type W = W<IN_INT_RAW_CH_SPEC>;

Register IN_INT_RAW_CH%s writer

Implementations

impl W

pub fn in_done(&mut self) -> IN_DONE_W<'_, IN_INT_RAW_CH_SPEC, 0>

Bit 0 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.

pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<'_, IN_INT_RAW_CH_SPEC, 1>

Bit 1 - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.

pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<'_, IN_INT_RAW_CH_SPEC, 2>

Bit 2 - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved.

pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<'_, IN_INT_RAW_CH_SPEC, 3>

Bit 3 - The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error and the second and third word error of inlink descriptor for Rx channel 0.

pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<'_, IN_INT_RAW_CH_SPEC, 4>

Bit 4 - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0.

pub fn infifo_ovf(&mut self) -> INFIFO_OVF_W<'_, IN_INT_RAW_CH_SPEC, 5>

Bit 5 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.

pub fn infifo_udf(&mut self) -> INFIFO_UDF_W<'_, IN_INT_RAW_CH_SPEC, 6>

Bit 6 - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.