Module esp32h2::spi1::spi_mem_flash_waiti_ctrl

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Expand description

SPI1 wait idle control register

Structs

Type Aliases

  • R
    Register SPI_MEM_FLASH_WAITI_CTRL reader
  • SPI_MEM_WAITI_ADDR_CYCLELEN_R
    Field SPI_MEM_WAITI_ADDR_CYCLELEN reader - When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.
  • SPI_MEM_WAITI_ADDR_CYCLELEN_W
    Field SPI_MEM_WAITI_ADDR_CYCLELEN writer - When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.
  • SPI_MEM_WAITI_ADDR_EN_R
    Field SPI_MEM_WAITI_ADDR_EN reader - 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.
  • SPI_MEM_WAITI_ADDR_EN_W
    Field SPI_MEM_WAITI_ADDR_EN writer - 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.
  • SPI_MEM_WAITI_CMD_2B_R
    Field SPI_MEM_WAITI_CMD_2B reader - 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.
  • SPI_MEM_WAITI_CMD_2B_W
    Field SPI_MEM_WAITI_CMD_2B writer - 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.
  • SPI_MEM_WAITI_CMD_R
    Field SPI_MEM_WAITI_CMD reader - The command value to wait flash idle(RDSR).
  • SPI_MEM_WAITI_CMD_W
    Field SPI_MEM_WAITI_CMD writer - The command value to wait flash idle(RDSR).
  • SPI_MEM_WAITI_DUMMY_CYCLELEN_R
    Field SPI_MEM_WAITI_DUMMY_CYCLELEN reader - The dummy cycle length when wait flash idle(RDSR).
  • SPI_MEM_WAITI_DUMMY_CYCLELEN_W
    Field SPI_MEM_WAITI_DUMMY_CYCLELEN writer - The dummy cycle length when wait flash idle(RDSR).
  • SPI_MEM_WAITI_DUMMY_R
    Field SPI_MEM_WAITI_DUMMY reader - The dummy phase enable when wait flash idle (RDSR)
  • SPI_MEM_WAITI_DUMMY_W
    Field SPI_MEM_WAITI_DUMMY writer - The dummy phase enable when wait flash idle (RDSR)
  • SPI_MEM_WAITI_EN_R
    Field SPI_MEM_WAITI_EN reader - 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.
  • SPI_MEM_WAITI_EN_W
    Field SPI_MEM_WAITI_EN writer - 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.
  • W
    Register SPI_MEM_FLASH_WAITI_CTRL writer