Module esp32h2::rmt::sys_conf

source ·
Expand description

RMT apb configuration register

Structs

  • Register SYS_CONF reader
  • RMT apb configuration register
  • Register SYS_CONF writer

Type Definitions

  • Field APB_FIFO_MASK reader - 1’h1: access memory directly. 1’h0: access memory by FIFO.
  • Field APB_FIFO_MASK writer - 1’h1: access memory directly. 1’h0: access memory by FIFO.
  • Field CLK_EN reader - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers
  • Field CLK_EN writer - RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers
  • Field MEM_CLK_FORCE_ON reader - Set this bit to enable the clock for RMT memory.
  • Field MEM_CLK_FORCE_ON writer - Set this bit to enable the clock for RMT memory.
  • Field MEM_FORCE_PD reader - Set this bit to power down RMT memory.
  • Field MEM_FORCE_PD writer - Set this bit to power down RMT memory.
  • Field MEM_FORCE_PU reader - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode.
  • Field MEM_FORCE_PU writer - 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode.
  • Field SCLK_ACTIVE reader - rmt_sclk switch
  • Field SCLK_ACTIVE writer - rmt_sclk switch
  • Field SCLK_DIV_A reader - the numerator of the fractional part of the fractional divisor
  • Field SCLK_DIV_A writer - the numerator of the fractional part of the fractional divisor
  • Field SCLK_DIV_B reader - the denominator of the fractional part of the fractional divisor
  • Field SCLK_DIV_B writer - the denominator of the fractional part of the fractional divisor
  • Field SCLK_DIV_NUM reader - the integral part of the fractional divisor
  • Field SCLK_DIV_NUM writer - the integral part of the fractional divisor
  • Field SCLK_SEL reader - choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL
  • Field SCLK_SEL writer - choose the clock source of rmt_sclk. 1:CLK_80Mhz,2:CLK_FOSC, 3:XTAL