Struct esp32h2::spi0::spi_mem_sram_cmd::R
source · pub struct R(_);
Expand description
Register SPI_MEM_SRAM_CMD
reader
Implementations§
source§impl R
impl R
sourcepub fn spi_mem_sclk_mode(&self) -> SPI_MEM_SCLK_MODE_R
pub fn spi_mem_sclk_mode(&self) -> SPI_MEM_SCLK_MODE_R
Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.
sourcepub fn spi_mem_swb_mode(&self) -> SPI_MEM_SWB_MODE_R
pub fn spi_mem_swb_mode(&self) -> SPI_MEM_SWB_MODE_R
Bits 2:9 - Mode bits in the external RAM fast read mode it is combined with spi_mem_fastrd_mode bit.
sourcepub fn spi_mem_sdin_dual(&self) -> SPI_MEM_SDIN_DUAL_R
pub fn spi_mem_sdin_dual(&self) -> SPI_MEM_SDIN_DUAL_R
Bit 10 - For SPI0 external RAM , din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.
sourcepub fn spi_mem_sdout_dual(&self) -> SPI_MEM_SDOUT_DUAL_R
pub fn spi_mem_sdout_dual(&self) -> SPI_MEM_SDOUT_DUAL_R
Bit 11 - For SPI0 external RAM , dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.
sourcepub fn spi_mem_saddr_dual(&self) -> SPI_MEM_SADDR_DUAL_R
pub fn spi_mem_saddr_dual(&self) -> SPI_MEM_SADDR_DUAL_R
Bit 12 - For SPI0 external RAM , address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.
sourcepub fn spi_mem_sdin_quad(&self) -> SPI_MEM_SDIN_QUAD_R
pub fn spi_mem_sdin_quad(&self) -> SPI_MEM_SDIN_QUAD_R
Bit 14 - For SPI0 external RAM , din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.
sourcepub fn spi_mem_sdout_quad(&self) -> SPI_MEM_SDOUT_QUAD_R
pub fn spi_mem_sdout_quad(&self) -> SPI_MEM_SDOUT_QUAD_R
Bit 15 - For SPI0 external RAM , dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.
sourcepub fn spi_mem_saddr_quad(&self) -> SPI_MEM_SADDR_QUAD_R
pub fn spi_mem_saddr_quad(&self) -> SPI_MEM_SADDR_QUAD_R
Bit 16 - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.
sourcepub fn spi_mem_scmd_quad(&self) -> SPI_MEM_SCMD_QUAD_R
pub fn spi_mem_scmd_quad(&self) -> SPI_MEM_SCMD_QUAD_R
Bit 17 - For SPI0 external RAM , cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.
sourcepub fn spi_mem_sdin_oct(&self) -> SPI_MEM_SDIN_OCT_R
pub fn spi_mem_sdin_oct(&self) -> SPI_MEM_SDIN_OCT_R
Bit 18 - For SPI0 external RAM , din phase apply 8 signals. 1: enable 0: disable.
sourcepub fn spi_mem_sdout_oct(&self) -> SPI_MEM_SDOUT_OCT_R
pub fn spi_mem_sdout_oct(&self) -> SPI_MEM_SDOUT_OCT_R
Bit 19 - For SPI0 external RAM , dout phase apply 8 signals. 1: enable 0: disable.
sourcepub fn spi_mem_saddr_oct(&self) -> SPI_MEM_SADDR_OCT_R
pub fn spi_mem_saddr_oct(&self) -> SPI_MEM_SADDR_OCT_R
Bit 20 - For SPI0 external RAM , address phase apply 4 signals. 1: enable 0: disable.
sourcepub fn spi_mem_scmd_oct(&self) -> SPI_MEM_SCMD_OCT_R
pub fn spi_mem_scmd_oct(&self) -> SPI_MEM_SCMD_OCT_R
Bit 21 - For SPI0 external RAM , cmd phase apply 8 signals. 1: enable 0: disable.
sourcepub fn spi_mem_sdummy_rin(&self) -> SPI_MEM_SDUMMY_RIN_R
pub fn spi_mem_sdummy_rin(&self) -> SPI_MEM_SDUMMY_RIN_R
Bit 22 - In the dummy phase of a MSPI read data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.
sourcepub fn spi_mem_sdummy_wout(&self) -> SPI_MEM_SDUMMY_WOUT_R
pub fn spi_mem_sdummy_wout(&self) -> SPI_MEM_SDUMMY_WOUT_R
Bit 23 - In the dummy phase of a MSPI write data transfer when accesses to external RAM, the signal level of SPI bus is output by the MSPI controller.
sourcepub fn spi_smem_wdummy_dqs_always_out(&self) -> SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_R
pub fn spi_smem_wdummy_dqs_always_out(&self) -> SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_R
Bit 24 - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_DQS is output by the MSPI controller.
sourcepub fn spi_smem_wdummy_always_out(&self) -> SPI_SMEM_WDUMMY_ALWAYS_OUT_R
pub fn spi_smem_wdummy_always_out(&self) -> SPI_SMEM_WDUMMY_ALWAYS_OUT_R
Bit 25 - In the dummy phase of an MSPI write data transfer when accesses to external RAM, the level of SPI_IO[7:0] is output by the MSPI controller.
sourcepub fn spi_smem_dqs_ie_always_on(&self) -> SPI_SMEM_DQS_IE_ALWAYS_ON_R
pub fn spi_smem_dqs_ie_always_on(&self) -> SPI_SMEM_DQS_IE_ALWAYS_ON_R
Bit 30 - When accesses to external RAM, 1: the IE signals of pads connected to SPI_DQS are always 1. 0: Others.
sourcepub fn spi_smem_data_ie_always_on(&self) -> SPI_SMEM_DATA_IE_ALWAYS_ON_R
pub fn spi_smem_data_ie_always_on(&self) -> SPI_SMEM_DATA_IE_ALWAYS_ON_R
Bit 31 - When accesses to external RAM, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.