1#[doc = "Register `SR` reader"]
2pub type R = crate::R<SR_SPEC>;
3#[doc = "Field `RESP_REC` reader - The received ACK value in master mode or slave mode. 0: ACK, 1: NACK."]
4pub type RESP_REC_R = crate::BitReader;
5#[doc = "Field `SLAVE_RW` reader - When in slave mode, 1: master reads from slave, 0: master writes to slave."]
6pub type SLAVE_RW_R = crate::BitReader;
7#[doc = "Field `ARB_LOST` reader - When the I2C controller loses control of SCL line, this register changes to 1."]
8pub type ARB_LOST_R = crate::BitReader;
9#[doc = "Field `BUS_BUSY` reader - 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state."]
10pub type BUS_BUSY_R = crate::BitReader;
11#[doc = "Field `SLAVE_ADDRESSED` reader - When configured as an I2C Slave, and the address sent by the master is equal to the address of the slave, then this bit will be of high level."]
12pub type SLAVE_ADDRESSED_R = crate::BitReader;
13#[doc = "Field `RXFIFO_CNT` reader - This field represents the amount of data needed to be sent."]
14pub type RXFIFO_CNT_R = crate::FieldReader;
15#[doc = "Field `STRETCH_CAUSE` reader - The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode."]
16pub type STRETCH_CAUSE_R = crate::FieldReader;
17#[doc = "Field `TXFIFO_CNT` reader - This field stores the amount of received data in RAM."]
18pub type TXFIFO_CNT_R = crate::FieldReader;
19#[doc = "Field `SCL_MAIN_STATE_LAST` reader - This field indicates the states of the I2C module state machine. 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK"]
20pub type SCL_MAIN_STATE_LAST_R = crate::FieldReader;
21#[doc = "Field `SCL_STATE_LAST` reader - This field indicates the states of the state machine used to produce SCL. 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop"]
22pub type SCL_STATE_LAST_R = crate::FieldReader;
23impl R {
24 #[doc = "Bit 0 - The received ACK value in master mode or slave mode. 0: ACK, 1: NACK."]
25 #[inline(always)]
26 pub fn resp_rec(&self) -> RESP_REC_R {
27 RESP_REC_R::new((self.bits & 1) != 0)
28 }
29 #[doc = "Bit 1 - When in slave mode, 1: master reads from slave, 0: master writes to slave."]
30 #[inline(always)]
31 pub fn slave_rw(&self) -> SLAVE_RW_R {
32 SLAVE_RW_R::new(((self.bits >> 1) & 1) != 0)
33 }
34 #[doc = "Bit 3 - When the I2C controller loses control of SCL line, this register changes to 1."]
35 #[inline(always)]
36 pub fn arb_lost(&self) -> ARB_LOST_R {
37 ARB_LOST_R::new(((self.bits >> 3) & 1) != 0)
38 }
39 #[doc = "Bit 4 - 1: the I2C bus is busy transferring data, 0: the I2C bus is in idle state."]
40 #[inline(always)]
41 pub fn bus_busy(&self) -> BUS_BUSY_R {
42 BUS_BUSY_R::new(((self.bits >> 4) & 1) != 0)
43 }
44 #[doc = "Bit 5 - When configured as an I2C Slave, and the address sent by the master is equal to the address of the slave, then this bit will be of high level."]
45 #[inline(always)]
46 pub fn slave_addressed(&self) -> SLAVE_ADDRESSED_R {
47 SLAVE_ADDRESSED_R::new(((self.bits >> 5) & 1) != 0)
48 }
49 #[doc = "Bits 8:13 - This field represents the amount of data needed to be sent."]
50 #[inline(always)]
51 pub fn rxfifo_cnt(&self) -> RXFIFO_CNT_R {
52 RXFIFO_CNT_R::new(((self.bits >> 8) & 0x3f) as u8)
53 }
54 #[doc = "Bits 14:15 - The cause of stretching SCL low in slave mode. 0: stretching SCL low at the beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode."]
55 #[inline(always)]
56 pub fn stretch_cause(&self) -> STRETCH_CAUSE_R {
57 STRETCH_CAUSE_R::new(((self.bits >> 14) & 3) as u8)
58 }
59 #[doc = "Bits 18:23 - This field stores the amount of received data in RAM."]
60 #[inline(always)]
61 pub fn txfifo_cnt(&self) -> TXFIFO_CNT_R {
62 TXFIFO_CNT_R::new(((self.bits >> 18) & 0x3f) as u8)
63 }
64 #[doc = "Bits 24:26 - This field indicates the states of the I2C module state machine. 0: Idle, 1: Address shift, 2: ACK address, 3: Rx data, 4: Tx data, 5: Send ACK, 6: Wait ACK"]
65 #[inline(always)]
66 pub fn scl_main_state_last(&self) -> SCL_MAIN_STATE_LAST_R {
67 SCL_MAIN_STATE_LAST_R::new(((self.bits >> 24) & 7) as u8)
68 }
69 #[doc = "Bits 28:30 - This field indicates the states of the state machine used to produce SCL. 0: Idle, 1: Start, 2: Negative edge, 3: Low, 4: Positive edge, 5: High, 6: Stop"]
70 #[inline(always)]
71 pub fn scl_state_last(&self) -> SCL_STATE_LAST_R {
72 SCL_STATE_LAST_R::new(((self.bits >> 28) & 7) as u8)
73 }
74}
75#[cfg(feature = "impl-register-debug")]
76impl core::fmt::Debug for R {
77 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
78 f.debug_struct("SR")
79 .field("resp_rec", &self.resp_rec())
80 .field("slave_rw", &self.slave_rw())
81 .field("arb_lost", &self.arb_lost())
82 .field("bus_busy", &self.bus_busy())
83 .field("slave_addressed", &self.slave_addressed())
84 .field("rxfifo_cnt", &self.rxfifo_cnt())
85 .field("stretch_cause", &self.stretch_cause())
86 .field("txfifo_cnt", &self.txfifo_cnt())
87 .field("scl_main_state_last", &self.scl_main_state_last())
88 .field("scl_state_last", &self.scl_state_last())
89 .finish()
90 }
91}
92#[doc = "Describe I2C work status.\n\nYou can [`read`](crate::Reg::read) this register and get [`sr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
93pub struct SR_SPEC;
94impl crate::RegisterSpec for SR_SPEC {
95 type Ux = u32;
96}
97#[doc = "`read()` method returns [`sr::R`](R) reader structure"]
98impl crate::Readable for SR_SPEC {}
99#[doc = "`reset()` method sets SR to value 0xc000"]
100impl crate::Resettable for SR_SPEC {
101 const RESET_VALUE: u32 = 0xc000;
102}