esp32h2/apb_saradc/
thres0_ctrl.rs

1#[doc = "Register `THRES0_CTRL` reader"]
2pub type R = crate::R<THRES0_CTRL_SPEC>;
3#[doc = "Register `THRES0_CTRL` writer"]
4pub type W = crate::W<THRES0_CTRL_SPEC>;
5#[doc = "Field `THRES0_CHANNEL` reader - configure thres0 to adc channel"]
6pub type THRES0_CHANNEL_R = crate::FieldReader;
7#[doc = "Field `THRES0_CHANNEL` writer - configure thres0 to adc channel"]
8pub type THRES0_CHANNEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `THRES0_HIGH` reader - saradc thres0 monitor thres"]
10pub type THRES0_HIGH_R = crate::FieldReader<u16>;
11#[doc = "Field `THRES0_HIGH` writer - saradc thres0 monitor thres"]
12pub type THRES0_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
13#[doc = "Field `THRES0_LOW` reader - saradc thres0 monitor thres"]
14pub type THRES0_LOW_R = crate::FieldReader<u16>;
15#[doc = "Field `THRES0_LOW` writer - saradc thres0 monitor thres"]
16pub type THRES0_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
17impl R {
18    #[doc = "Bits 0:3 - configure thres0 to adc channel"]
19    #[inline(always)]
20    pub fn thres0_channel(&self) -> THRES0_CHANNEL_R {
21        THRES0_CHANNEL_R::new((self.bits & 0x0f) as u8)
22    }
23    #[doc = "Bits 5:17 - saradc thres0 monitor thres"]
24    #[inline(always)]
25    pub fn thres0_high(&self) -> THRES0_HIGH_R {
26        THRES0_HIGH_R::new(((self.bits >> 5) & 0x1fff) as u16)
27    }
28    #[doc = "Bits 18:30 - saradc thres0 monitor thres"]
29    #[inline(always)]
30    pub fn thres0_low(&self) -> THRES0_LOW_R {
31        THRES0_LOW_R::new(((self.bits >> 18) & 0x1fff) as u16)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("THRES0_CTRL")
38            .field("thres0_channel", &self.thres0_channel())
39            .field("thres0_high", &self.thres0_high())
40            .field("thres0_low", &self.thres0_low())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bits 0:3 - configure thres0 to adc channel"]
46    #[inline(always)]
47    pub fn thres0_channel(&mut self) -> THRES0_CHANNEL_W<THRES0_CTRL_SPEC> {
48        THRES0_CHANNEL_W::new(self, 0)
49    }
50    #[doc = "Bits 5:17 - saradc thres0 monitor thres"]
51    #[inline(always)]
52    pub fn thres0_high(&mut self) -> THRES0_HIGH_W<THRES0_CTRL_SPEC> {
53        THRES0_HIGH_W::new(self, 5)
54    }
55    #[doc = "Bits 18:30 - saradc thres0 monitor thres"]
56    #[inline(always)]
57    pub fn thres0_low(&mut self) -> THRES0_LOW_W<THRES0_CTRL_SPEC> {
58        THRES0_LOW_W::new(self, 18)
59    }
60}
61#[doc = "digital saradc configure register\n\nYou can [`read`](crate::Reg::read) this register and get [`thres0_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`thres0_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct THRES0_CTRL_SPEC;
63impl crate::RegisterSpec for THRES0_CTRL_SPEC {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`thres0_ctrl::R`](R) reader structure"]
67impl crate::Readable for THRES0_CTRL_SPEC {}
68#[doc = "`write(|w| ..)` method takes [`thres0_ctrl::W`](W) writer structure"]
69impl crate::Writable for THRES0_CTRL_SPEC {
70    type Safety = crate::Unsafe;
71}
72#[doc = "`reset()` method sets THRES0_CTRL to value 0x0003_ffed"]
73impl crate::Resettable for THRES0_CTRL_SPEC {
74    const RESET_VALUE: u32 = 0x0003_ffed;
75}
esp32h2/apb_saradc/thres0_ctrl.rs

esp32h2/apb_saradc/
thres0_ctrl.rs
