esp32h2/pcr/
ctrl_clk_out_en.rs

1#[doc = "Register `CTRL_CLK_OUT_EN` reader"]
2pub type R = crate::R<CTRL_CLK_OUT_EN_SPEC>;
3#[doc = "Register `CTRL_CLK_OUT_EN` writer"]
4pub type W = crate::W<CTRL_CLK_OUT_EN_SPEC>;
5#[doc = "Field `CLK8_OEN` reader - Set 1 to enable 8m clock"]
6pub type CLK8_OEN_R = crate::BitReader;
7#[doc = "Field `CLK8_OEN` writer - Set 1 to enable 8m clock"]
8pub type CLK8_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CLK16_OEN` reader - Set 1 to enable 16m clock"]
10pub type CLK16_OEN_R = crate::BitReader;
11#[doc = "Field `CLK16_OEN` writer - Set 1 to enable 16m clock"]
12pub type CLK16_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CLK32_OEN` reader - Set 1 to enable 32m clock"]
14pub type CLK32_OEN_R = crate::BitReader;
15#[doc = "Field `CLK32_OEN` writer - Set 1 to enable 32m clock"]
16pub type CLK32_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CLK_ADC_INF_OEN` reader - Reserved"]
18pub type CLK_ADC_INF_OEN_R = crate::BitReader;
19#[doc = "Field `CLK_ADC_INF_OEN` writer - Reserved"]
20pub type CLK_ADC_INF_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CLK_DFM_INF_OEN` reader - Reserved"]
22pub type CLK_DFM_INF_OEN_R = crate::BitReader;
23#[doc = "Field `CLK_DFM_INF_OEN` writer - Reserved"]
24pub type CLK_DFM_INF_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CLK_SDM_MOD_OEN` reader - Reserved"]
26pub type CLK_SDM_MOD_OEN_R = crate::BitReader;
27#[doc = "Field `CLK_SDM_MOD_OEN` writer - Reserved"]
28pub type CLK_SDM_MOD_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CLK_XTAL_OEN` reader - Set 1 to enable xtal clock"]
30pub type CLK_XTAL_OEN_R = crate::BitReader;
31#[doc = "Field `CLK_XTAL_OEN` writer - Set 1 to enable xtal clock"]
32pub type CLK_XTAL_OEN_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    #[doc = "Bit 0 - Set 1 to enable 8m clock"]
35    #[inline(always)]
36    pub fn clk8_oen(&self) -> CLK8_OEN_R {
37        CLK8_OEN_R::new((self.bits & 1) != 0)
38    }
39    #[doc = "Bit 1 - Set 1 to enable 16m clock"]
40    #[inline(always)]
41    pub fn clk16_oen(&self) -> CLK16_OEN_R {
42        CLK16_OEN_R::new(((self.bits >> 1) & 1) != 0)
43    }
44    #[doc = "Bit 2 - Set 1 to enable 32m clock"]
45    #[inline(always)]
46    pub fn clk32_oen(&self) -> CLK32_OEN_R {
47        CLK32_OEN_R::new(((self.bits >> 2) & 1) != 0)
48    }
49    #[doc = "Bit 3 - Reserved"]
50    #[inline(always)]
51    pub fn clk_adc_inf_oen(&self) -> CLK_ADC_INF_OEN_R {
52        CLK_ADC_INF_OEN_R::new(((self.bits >> 3) & 1) != 0)
53    }
54    #[doc = "Bit 4 - Reserved"]
55    #[inline(always)]
56    pub fn clk_dfm_inf_oen(&self) -> CLK_DFM_INF_OEN_R {
57        CLK_DFM_INF_OEN_R::new(((self.bits >> 4) & 1) != 0)
58    }
59    #[doc = "Bit 5 - Reserved"]
60    #[inline(always)]
61    pub fn clk_sdm_mod_oen(&self) -> CLK_SDM_MOD_OEN_R {
62        CLK_SDM_MOD_OEN_R::new(((self.bits >> 5) & 1) != 0)
63    }
64    #[doc = "Bit 6 - Set 1 to enable xtal clock"]
65    #[inline(always)]
66    pub fn clk_xtal_oen(&self) -> CLK_XTAL_OEN_R {
67        CLK_XTAL_OEN_R::new(((self.bits >> 6) & 1) != 0)
68    }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73        f.debug_struct("CTRL_CLK_OUT_EN")
74            .field("clk8_oen", &self.clk8_oen())
75            .field("clk16_oen", &self.clk16_oen())
76            .field("clk32_oen", &self.clk32_oen())
77            .field("clk_adc_inf_oen", &self.clk_adc_inf_oen())
78            .field("clk_dfm_inf_oen", &self.clk_dfm_inf_oen())
79            .field("clk_sdm_mod_oen", &self.clk_sdm_mod_oen())
80            .field("clk_xtal_oen", &self.clk_xtal_oen())
81            .finish()
82    }
83}
84impl W {
85    #[doc = "Bit 0 - Set 1 to enable 8m clock"]
86    #[inline(always)]
87    pub fn clk8_oen(&mut self) -> CLK8_OEN_W<CTRL_CLK_OUT_EN_SPEC> {
88        CLK8_OEN_W::new(self, 0)
89    }
90    #[doc = "Bit 1 - Set 1 to enable 16m clock"]
91    #[inline(always)]
92    pub fn clk16_oen(&mut self) -> CLK16_OEN_W<CTRL_CLK_OUT_EN_SPEC> {
93        CLK16_OEN_W::new(self, 1)
94    }
95    #[doc = "Bit 2 - Set 1 to enable 32m clock"]
96    #[inline(always)]
97    pub fn clk32_oen(&mut self) -> CLK32_OEN_W<CTRL_CLK_OUT_EN_SPEC> {
98        CLK32_OEN_W::new(self, 2)
99    }
100    #[doc = "Bit 3 - Reserved"]
101    #[inline(always)]
102    pub fn clk_adc_inf_oen(&mut self) -> CLK_ADC_INF_OEN_W<CTRL_CLK_OUT_EN_SPEC> {
103        CLK_ADC_INF_OEN_W::new(self, 3)
104    }
105    #[doc = "Bit 4 - Reserved"]
106    #[inline(always)]
107    pub fn clk_dfm_inf_oen(&mut self) -> CLK_DFM_INF_OEN_W<CTRL_CLK_OUT_EN_SPEC> {
108        CLK_DFM_INF_OEN_W::new(self, 4)
109    }
110    #[doc = "Bit 5 - Reserved"]
111    #[inline(always)]
112    pub fn clk_sdm_mod_oen(&mut self) -> CLK_SDM_MOD_OEN_W<CTRL_CLK_OUT_EN_SPEC> {
113        CLK_SDM_MOD_OEN_W::new(self, 5)
114    }
115    #[doc = "Bit 6 - Set 1 to enable xtal clock"]
116    #[inline(always)]
117    pub fn clk_xtal_oen(&mut self) -> CLK_XTAL_OEN_W<CTRL_CLK_OUT_EN_SPEC> {
118        CLK_XTAL_OEN_W::new(self, 6)
119    }
120}
121#[doc = "CLK_OUT_EN configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_clk_out_en::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_clk_out_en::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
122pub struct CTRL_CLK_OUT_EN_SPEC;
123impl crate::RegisterSpec for CTRL_CLK_OUT_EN_SPEC {
124    type Ux = u32;
125}
126#[doc = "`read()` method returns [`ctrl_clk_out_en::R`](R) reader structure"]
127impl crate::Readable for CTRL_CLK_OUT_EN_SPEC {}
128#[doc = "`write(|w| ..)` method takes [`ctrl_clk_out_en::W`](W) writer structure"]
129impl crate::Writable for CTRL_CLK_OUT_EN_SPEC {
130    type Safety = crate::Unsafe;
131}
132#[doc = "`reset()` method sets CTRL_CLK_OUT_EN to value 0x7f"]
133impl crate::Resettable for CTRL_CLK_OUT_EN_SPEC {
134    const RESET_VALUE: u32 = 0x7f;
135}
esp32h2/pcr/ctrl_clk_out_en.rs

esp32h2/pcr/
ctrl_clk_out_en.rs
