esp32h2/modem_lpcon/
coex_lp_clk_conf.rs

1#[doc = "Register `COEX_LP_CLK_CONF` reader"]
2pub type R = crate::R<COEX_LP_CLK_CONF_SPEC>;
3#[doc = "Register `COEX_LP_CLK_CONF` writer"]
4pub type W = crate::W<COEX_LP_CLK_CONF_SPEC>;
5#[doc = "Field `CLK_COEX_LP_SEL_OSC_SLOW` reader - "]
6pub type CLK_COEX_LP_SEL_OSC_SLOW_R = crate::BitReader;
7#[doc = "Field `CLK_COEX_LP_SEL_OSC_SLOW` writer - "]
8pub type CLK_COEX_LP_SEL_OSC_SLOW_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CLK_COEX_LP_SEL_OSC_FAST` reader - "]
10pub type CLK_COEX_LP_SEL_OSC_FAST_R = crate::BitReader;
11#[doc = "Field `CLK_COEX_LP_SEL_OSC_FAST` writer - "]
12pub type CLK_COEX_LP_SEL_OSC_FAST_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CLK_COEX_LP_SEL_XTAL` reader - "]
14pub type CLK_COEX_LP_SEL_XTAL_R = crate::BitReader;
15#[doc = "Field `CLK_COEX_LP_SEL_XTAL` writer - "]
16pub type CLK_COEX_LP_SEL_XTAL_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CLK_COEX_LP_SEL_XTAL32K` reader - "]
18pub type CLK_COEX_LP_SEL_XTAL32K_R = crate::BitReader;
19#[doc = "Field `CLK_COEX_LP_SEL_XTAL32K` writer - "]
20pub type CLK_COEX_LP_SEL_XTAL32K_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CLK_COEX_LP_DIV_NUM` reader - "]
22pub type CLK_COEX_LP_DIV_NUM_R = crate::FieldReader<u16>;
23#[doc = "Field `CLK_COEX_LP_DIV_NUM` writer - "]
24pub type CLK_COEX_LP_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
25impl R {
26    #[doc = "Bit 0"]
27    #[inline(always)]
28    pub fn clk_coex_lp_sel_osc_slow(&self) -> CLK_COEX_LP_SEL_OSC_SLOW_R {
29        CLK_COEX_LP_SEL_OSC_SLOW_R::new((self.bits & 1) != 0)
30    }
31    #[doc = "Bit 1"]
32    #[inline(always)]
33    pub fn clk_coex_lp_sel_osc_fast(&self) -> CLK_COEX_LP_SEL_OSC_FAST_R {
34        CLK_COEX_LP_SEL_OSC_FAST_R::new(((self.bits >> 1) & 1) != 0)
35    }
36    #[doc = "Bit 2"]
37    #[inline(always)]
38    pub fn clk_coex_lp_sel_xtal(&self) -> CLK_COEX_LP_SEL_XTAL_R {
39        CLK_COEX_LP_SEL_XTAL_R::new(((self.bits >> 2) & 1) != 0)
40    }
41    #[doc = "Bit 3"]
42    #[inline(always)]
43    pub fn clk_coex_lp_sel_xtal32k(&self) -> CLK_COEX_LP_SEL_XTAL32K_R {
44        CLK_COEX_LP_SEL_XTAL32K_R::new(((self.bits >> 3) & 1) != 0)
45    }
46    #[doc = "Bits 4:15"]
47    #[inline(always)]
48    pub fn clk_coex_lp_div_num(&self) -> CLK_COEX_LP_DIV_NUM_R {
49        CLK_COEX_LP_DIV_NUM_R::new(((self.bits >> 4) & 0x0fff) as u16)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("COEX_LP_CLK_CONF")
56            .field("clk_coex_lp_sel_osc_slow", &self.clk_coex_lp_sel_osc_slow())
57            .field("clk_coex_lp_sel_osc_fast", &self.clk_coex_lp_sel_osc_fast())
58            .field("clk_coex_lp_sel_xtal", &self.clk_coex_lp_sel_xtal())
59            .field("clk_coex_lp_sel_xtal32k", &self.clk_coex_lp_sel_xtal32k())
60            .field("clk_coex_lp_div_num", &self.clk_coex_lp_div_num())
61            .finish()
62    }
63}
64impl W {
65    #[doc = "Bit 0"]
66    #[inline(always)]
67    pub fn clk_coex_lp_sel_osc_slow(
68        &mut self,
69    ) -> CLK_COEX_LP_SEL_OSC_SLOW_W<COEX_LP_CLK_CONF_SPEC> {
70        CLK_COEX_LP_SEL_OSC_SLOW_W::new(self, 0)
71    }
72    #[doc = "Bit 1"]
73    #[inline(always)]
74    pub fn clk_coex_lp_sel_osc_fast(
75        &mut self,
76    ) -> CLK_COEX_LP_SEL_OSC_FAST_W<COEX_LP_CLK_CONF_SPEC> {
77        CLK_COEX_LP_SEL_OSC_FAST_W::new(self, 1)
78    }
79    #[doc = "Bit 2"]
80    #[inline(always)]
81    pub fn clk_coex_lp_sel_xtal(&mut self) -> CLK_COEX_LP_SEL_XTAL_W<COEX_LP_CLK_CONF_SPEC> {
82        CLK_COEX_LP_SEL_XTAL_W::new(self, 2)
83    }
84    #[doc = "Bit 3"]
85    #[inline(always)]
86    pub fn clk_coex_lp_sel_xtal32k(&mut self) -> CLK_COEX_LP_SEL_XTAL32K_W<COEX_LP_CLK_CONF_SPEC> {
87        CLK_COEX_LP_SEL_XTAL32K_W::new(self, 3)
88    }
89    #[doc = "Bits 4:15"]
90    #[inline(always)]
91    pub fn clk_coex_lp_div_num(&mut self) -> CLK_COEX_LP_DIV_NUM_W<COEX_LP_CLK_CONF_SPEC> {
92        CLK_COEX_LP_DIV_NUM_W::new(self, 4)
93    }
94}
95#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`coex_lp_clk_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`coex_lp_clk_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
96pub struct COEX_LP_CLK_CONF_SPEC;
97impl crate::RegisterSpec for COEX_LP_CLK_CONF_SPEC {
98    type Ux = u32;
99}
100#[doc = "`read()` method returns [`coex_lp_clk_conf::R`](R) reader structure"]
101impl crate::Readable for COEX_LP_CLK_CONF_SPEC {}
102#[doc = "`write(|w| ..)` method takes [`coex_lp_clk_conf::W`](W) writer structure"]
103impl crate::Writable for COEX_LP_CLK_CONF_SPEC {
104    type Safety = crate::Unsafe;
105    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
106    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
107}
108#[doc = "`reset()` method sets COEX_LP_CLK_CONF to value 0"]
109impl crate::Resettable for COEX_LP_CLK_CONF_SPEC {
110    const RESET_VALUE: u32 = 0;
111}
esp32h2/modem_lpcon/coex_lp_clk_conf.rs

esp32h2/modem_lpcon/
coex_lp_clk_conf.rs
