1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `CH_TX_END(0-1)` writer - Set this bit to clear theCH%s_TX_END_INT interrupt."]
4pub type CH_TX_END_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `CH_RX_END(2-3)` writer - Set this bit to clear theCH2_RX_END_INT interrupt."]
6pub type CH_RX_END_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `CH_TX_ERR(0-1)` writer - Set this bit to clear theCH4_ERR_INT interrupt."]
8pub type CH_TX_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CH_RX_ERR(2-3)` writer - Set this bit to clear theCH6_ERR_INT interrupt."]
10pub type CH_RX_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `CH_TX_THR_EVENT(0-1)` writer - Set this bit to clear theCH%s_TX_THR_EVENT_INT interrupt."]
12pub type CH_TX_THR_EVENT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CH_RX_THR_EVENT(2-3)` writer - Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt."]
14pub type CH_RX_THR_EVENT_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `CH_TX_LOOP(0-1)` writer - Set this bit to clear theCH%s_TX_LOOP_INT interrupt."]
16pub type CH_TX_LOOP_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[cfg(feature = "impl-register-debug")]
18impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
19 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
20 write!(f, "(not readable)")
21 }
22}
23impl W {
24 #[doc = "Set this bit to clear theCH(0-1)_TX_END_INT interrupt."]
25 #[doc = ""]
26 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.</div>"]
27 #[inline(always)]
28 pub fn ch_tx_end(&mut self, n: u8) -> CH_TX_END_W<INT_CLR_SPEC> {
29 #[allow(clippy::no_effect)]
30 [(); 2][n as usize];
31 CH_TX_END_W::new(self, n)
32 }
33 #[doc = "Bit 0 - Set this bit to clear theCH0_TX_END_INT interrupt."]
34 #[inline(always)]
35 pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
36 CH_TX_END_W::new(self, 0)
37 }
38 #[doc = "Bit 1 - Set this bit to clear theCH1_TX_END_INT interrupt."]
39 #[inline(always)]
40 pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<INT_CLR_SPEC> {
41 CH_TX_END_W::new(self, 1)
42 }
43 #[doc = "Set this bit to clear theCH2_RX_END_INT interrupt."]
44 #[doc = ""]
45 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH2_RX_END` field.</div>"]
46 #[inline(always)]
47 pub fn ch_rx_end(&mut self, n: u8) -> CH_RX_END_W<INT_CLR_SPEC> {
48 #[allow(clippy::no_effect)]
49 [(); 2][n as usize];
50 CH_RX_END_W::new(self, n + 2)
51 }
52 #[doc = "Bit 2 - Set this bit to clear theCH2_RX_END_INT interrupt."]
53 #[inline(always)]
54 pub fn ch2_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
55 CH_RX_END_W::new(self, 2)
56 }
57 #[doc = "Bit 3 - Set this bit to clear theCH2_RX_END_INT interrupt."]
58 #[inline(always)]
59 pub fn ch3_rx_end(&mut self) -> CH_RX_END_W<INT_CLR_SPEC> {
60 CH_RX_END_W::new(self, 3)
61 }
62 #[doc = "Set this bit to clear theCH4_ERR_INT interrupt."]
63 #[doc = ""]
64 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_ERR` field.</div>"]
65 #[inline(always)]
66 pub fn ch_tx_err(&mut self, n: u8) -> CH_TX_ERR_W<INT_CLR_SPEC> {
67 #[allow(clippy::no_effect)]
68 [(); 2][n as usize];
69 CH_TX_ERR_W::new(self, n + 4)
70 }
71 #[doc = "Bit 4 - Set this bit to clear theCH4_ERR_INT interrupt."]
72 #[inline(always)]
73 pub fn ch0_tx_err(&mut self) -> CH_TX_ERR_W<INT_CLR_SPEC> {
74 CH_TX_ERR_W::new(self, 4)
75 }
76 #[doc = "Bit 5 - Set this bit to clear theCH4_ERR_INT interrupt."]
77 #[inline(always)]
78 pub fn ch1_tx_err(&mut self) -> CH_TX_ERR_W<INT_CLR_SPEC> {
79 CH_TX_ERR_W::new(self, 5)
80 }
81 #[doc = "Set this bit to clear theCH6_ERR_INT interrupt."]
82 #[doc = ""]
83 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH2_RX_ERR` field.</div>"]
84 #[inline(always)]
85 pub fn ch_rx_err(&mut self, n: u8) -> CH_RX_ERR_W<INT_CLR_SPEC> {
86 #[allow(clippy::no_effect)]
87 [(); 2][n as usize];
88 CH_RX_ERR_W::new(self, n + 6)
89 }
90 #[doc = "Bit 6 - Set this bit to clear theCH6_ERR_INT interrupt."]
91 #[inline(always)]
92 pub fn ch2_rx_err(&mut self) -> CH_RX_ERR_W<INT_CLR_SPEC> {
93 CH_RX_ERR_W::new(self, 6)
94 }
95 #[doc = "Bit 7 - Set this bit to clear theCH6_ERR_INT interrupt."]
96 #[inline(always)]
97 pub fn ch3_rx_err(&mut self) -> CH_RX_ERR_W<INT_CLR_SPEC> {
98 CH_RX_ERR_W::new(self, 7)
99 }
100 #[doc = "Set this bit to clear theCH(0-1)_TX_THR_EVENT_INT interrupt."]
101 #[doc = ""]
102 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.</div>"]
103 #[inline(always)]
104 pub fn ch_tx_thr_event(&mut self, n: u8) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
105 #[allow(clippy::no_effect)]
106 [(); 2][n as usize];
107 CH_TX_THR_EVENT_W::new(self, n + 8)
108 }
109 #[doc = "Bit 8 - Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt."]
110 #[inline(always)]
111 pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
112 CH_TX_THR_EVENT_W::new(self, 8)
113 }
114 #[doc = "Bit 9 - Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt."]
115 #[inline(always)]
116 pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<INT_CLR_SPEC> {
117 CH_TX_THR_EVENT_W::new(self, 9)
118 }
119 #[doc = "Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt."]
120 #[doc = ""]
121 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH2_RX_THR_EVENT` field.</div>"]
122 #[inline(always)]
123 pub fn ch_rx_thr_event(&mut self, n: u8) -> CH_RX_THR_EVENT_W<INT_CLR_SPEC> {
124 #[allow(clippy::no_effect)]
125 [(); 2][n as usize];
126 CH_RX_THR_EVENT_W::new(self, n + 10)
127 }
128 #[doc = "Bit 10 - Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt."]
129 #[inline(always)]
130 pub fn ch2_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_CLR_SPEC> {
131 CH_RX_THR_EVENT_W::new(self, 10)
132 }
133 #[doc = "Bit 11 - Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt."]
134 #[inline(always)]
135 pub fn ch3_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<INT_CLR_SPEC> {
136 CH_RX_THR_EVENT_W::new(self, 11)
137 }
138 #[doc = "Set this bit to clear theCH(0-1)_TX_LOOP_INT interrupt."]
139 #[doc = ""]
140 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `CH0_TX_LOOP` field.</div>"]
141 #[inline(always)]
142 pub fn ch_tx_loop(&mut self, n: u8) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
143 #[allow(clippy::no_effect)]
144 [(); 2][n as usize];
145 CH_TX_LOOP_W::new(self, n + 12)
146 }
147 #[doc = "Bit 12 - Set this bit to clear theCH0_TX_LOOP_INT interrupt."]
148 #[inline(always)]
149 pub fn ch0_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
150 CH_TX_LOOP_W::new(self, 12)
151 }
152 #[doc = "Bit 13 - Set this bit to clear theCH1_TX_LOOP_INT interrupt."]
153 #[inline(always)]
154 pub fn ch1_tx_loop(&mut self) -> CH_TX_LOOP_W<INT_CLR_SPEC> {
155 CH_TX_LOOP_W::new(self, 13)
156 }
157}
158#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
159pub struct INT_CLR_SPEC;
160impl crate::RegisterSpec for INT_CLR_SPEC {
161 type Ux = u32;
162}
163#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
164impl crate::Writable for INT_CLR_SPEC {
165 type Safety = crate::Unsafe;
166 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
167 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
168}
169#[doc = "`reset()` method sets INT_CLR to value 0"]
170impl crate::Resettable for INT_CLR_SPEC {
171 const RESET_VALUE: u32 = 0;
172}