1#[doc = "Register `SPI_SMEM_DIN_MODE` reader"]
2pub type R = crate::R<SPI_SMEM_DIN_MODE_SPEC>;
3#[doc = "Field `SPI_SMEM_DIN0_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
4pub type SPI_SMEM_DIN0_MODE_R = crate::FieldReader;
5#[doc = "Field `SPI_SMEM_DIN1_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
6pub type SPI_SMEM_DIN1_MODE_R = crate::FieldReader;
7#[doc = "Field `SPI_SMEM_DIN2_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
8pub type SPI_SMEM_DIN2_MODE_R = crate::FieldReader;
9#[doc = "Field `SPI_SMEM_DIN3_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
10pub type SPI_SMEM_DIN3_MODE_R = crate::FieldReader;
11#[doc = "Field `SPI_SMEM_DIN4_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
12pub type SPI_SMEM_DIN4_MODE_R = crate::FieldReader;
13#[doc = "Field `SPI_SMEM_DIN5_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
14pub type SPI_SMEM_DIN5_MODE_R = crate::FieldReader;
15#[doc = "Field `SPI_SMEM_DIN6_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
16pub type SPI_SMEM_DIN6_MODE_R = crate::FieldReader;
17#[doc = "Field `SPI_SMEM_DIN7_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
18pub type SPI_SMEM_DIN7_MODE_R = crate::FieldReader;
19#[doc = "Field `SPI_SMEM_DINS_MODE` reader - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
20pub type SPI_SMEM_DINS_MODE_R = crate::FieldReader;
21impl R {
22 #[doc = "Bits 0:2 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
23 #[inline(always)]
24 pub fn spi_smem_din0_mode(&self) -> SPI_SMEM_DIN0_MODE_R {
25 SPI_SMEM_DIN0_MODE_R::new((self.bits & 7) as u8)
26 }
27 #[doc = "Bits 3:5 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
28 #[inline(always)]
29 pub fn spi_smem_din1_mode(&self) -> SPI_SMEM_DIN1_MODE_R {
30 SPI_SMEM_DIN1_MODE_R::new(((self.bits >> 3) & 7) as u8)
31 }
32 #[doc = "Bits 6:8 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
33 #[inline(always)]
34 pub fn spi_smem_din2_mode(&self) -> SPI_SMEM_DIN2_MODE_R {
35 SPI_SMEM_DIN2_MODE_R::new(((self.bits >> 6) & 7) as u8)
36 }
37 #[doc = "Bits 9:11 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
38 #[inline(always)]
39 pub fn spi_smem_din3_mode(&self) -> SPI_SMEM_DIN3_MODE_R {
40 SPI_SMEM_DIN3_MODE_R::new(((self.bits >> 9) & 7) as u8)
41 }
42 #[doc = "Bits 12:14 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
43 #[inline(always)]
44 pub fn spi_smem_din4_mode(&self) -> SPI_SMEM_DIN4_MODE_R {
45 SPI_SMEM_DIN4_MODE_R::new(((self.bits >> 12) & 7) as u8)
46 }
47 #[doc = "Bits 15:17 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
48 #[inline(always)]
49 pub fn spi_smem_din5_mode(&self) -> SPI_SMEM_DIN5_MODE_R {
50 SPI_SMEM_DIN5_MODE_R::new(((self.bits >> 15) & 7) as u8)
51 }
52 #[doc = "Bits 18:20 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
53 #[inline(always)]
54 pub fn spi_smem_din6_mode(&self) -> SPI_SMEM_DIN6_MODE_R {
55 SPI_SMEM_DIN6_MODE_R::new(((self.bits >> 18) & 7) as u8)
56 }
57 #[doc = "Bits 21:23 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
58 #[inline(always)]
59 pub fn spi_smem_din7_mode(&self) -> SPI_SMEM_DIN7_MODE_R {
60 SPI_SMEM_DIN7_MODE_R::new(((self.bits >> 21) & 7) as u8)
61 }
62 #[doc = "Bits 24:26 - the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge"]
63 #[inline(always)]
64 pub fn spi_smem_dins_mode(&self) -> SPI_SMEM_DINS_MODE_R {
65 SPI_SMEM_DINS_MODE_R::new(((self.bits >> 24) & 7) as u8)
66 }
67}
68#[cfg(feature = "impl-register-debug")]
69impl core::fmt::Debug for R {
70 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
71 f.debug_struct("SPI_SMEM_DIN_MODE")
72 .field("spi_smem_din0_mode", &self.spi_smem_din0_mode())
73 .field("spi_smem_din1_mode", &self.spi_smem_din1_mode())
74 .field("spi_smem_din2_mode", &self.spi_smem_din2_mode())
75 .field("spi_smem_din3_mode", &self.spi_smem_din3_mode())
76 .field("spi_smem_din4_mode", &self.spi_smem_din4_mode())
77 .field("spi_smem_din5_mode", &self.spi_smem_din5_mode())
78 .field("spi_smem_din6_mode", &self.spi_smem_din6_mode())
79 .field("spi_smem_din7_mode", &self.spi_smem_din7_mode())
80 .field("spi_smem_dins_mode", &self.spi_smem_dins_mode())
81 .finish()
82 }
83}
84#[doc = "MSPI external RAM input timing delay mode control register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_smem_din_mode::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
85pub struct SPI_SMEM_DIN_MODE_SPEC;
86impl crate::RegisterSpec for SPI_SMEM_DIN_MODE_SPEC {
87 type Ux = u32;
88}
89#[doc = "`read()` method returns [`spi_smem_din_mode::R`](R) reader structure"]
90impl crate::Readable for SPI_SMEM_DIN_MODE_SPEC {}
91#[doc = "`reset()` method sets SPI_SMEM_DIN_MODE to value 0"]
92impl crate::Resettable for SPI_SMEM_DIN_MODE_SPEC {
93 const RESET_VALUE: u32 = 0;
94}