pub type W = W<INT_RAW_SPEC>;Expand description
Register INT_RAW writer
Aliased Type§
struct W { /* private fields */ }Implementations§
Source§impl W
impl W
Sourcepub fn slv_st_end(&mut self) -> SLV_ST_END_W<'_, INT_RAW_SPEC>
pub fn slv_st_end(&mut self) -> SLV_ST_END_W<'_, INT_RAW_SPEC>
Bit 3 - The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi0_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others
Sourcepub fn mst_st_end(&mut self) -> MST_ST_END_W<'_, INT_RAW_SPEC>
pub fn mst_st_end(&mut self) -> MST_ST_END_W<'_, INT_RAW_SPEC>
Bit 4 - The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi0_mst_st is changed from non idle state to idle state. 0: Others.
Sourcepub fn pms_reject(&mut self) -> PMS_REJECT_W<'_, INT_RAW_SPEC>
pub fn pms_reject(&mut self) -> PMS_REJECT_W<'_, INT_RAW_SPEC>
Bit 6 - The raw bit for SPI_MEM_PMS_REJECT_INT interrupt. 1: Triggered when SPI1 access is rejected. 0: Others.
Sourcepub fn axi_raddr_err(&mut self) -> AXI_RADDR_ERR_W<'_, INT_RAW_SPEC>
pub fn axi_raddr_err(&mut self) -> AXI_RADDR_ERR_W<'_, INT_RAW_SPEC>
Bit 7 - The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.