esp32h2::spi0::cache_sctrl

Struct CACHE_SCTRL_SPEC

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pub struct CACHE_SCTRL_SPEC;
Expand description

SPI0 external RAM control register

You can read this register and get cache_sctrl::R. See API.

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impl RegisterSpec for CACHE_SCTRL_SPEC

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type Ux = u32

Raw register type (u8, u16, u32, …).
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impl Resettable for CACHE_SCTRL_SPEC

reset() method sets CACHE_SCTRL to value 0x0055_c070

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const RESET_VALUE: u32 = 5_619_824u32

Reset value of the register.
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fn reset_value() -> Self::Ux

Reset value of the register.
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impl Readable for CACHE_SCTRL_SPEC

read() method returns cache_sctrl::R reader structure

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