esp32h2::rmt

Struct RegisterBlock

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#[repr(C)]
pub struct RegisterBlock { /* private fields */ }
Expand description

Register block

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impl RegisterBlock

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pub const fn chdata(&self, n: usize) -> &CHDATA

0x00..0x10 - The read and write data register for CHANNEL%s by apb fifo access.

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pub fn chdata_iter(&self) -> impl Iterator<Item = &CHDATA>

Iterator for array of: 0x00..0x10 - The read and write data register for CHANNEL%s by apb fifo access.

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pub const fn ch0data(&self) -> &CHDATA

0x00 - The read and write data register for CHANNEL0 by apb fifo access.

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pub const fn ch1data(&self) -> &CHDATA

0x04 - The read and write data register for CHANNEL1 by apb fifo access.

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pub const fn ch2data(&self) -> &CHDATA

0x08 - The read and write data register for CHANNEL2 by apb fifo access.

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pub const fn ch3data(&self) -> &CHDATA

0x0c - The read and write data register for CHANNEL3 by apb fifo access.

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pub const fn ch_tx_conf0(&self, n: usize) -> &CH_TX_CONF0

0x10..0x18 - Channel %s configure register 0

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pub fn ch_tx_conf0_iter(&self) -> impl Iterator<Item = &CH_TX_CONF0>

Iterator for array of: 0x10..0x18 - Channel %s configure register 0

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pub const fn ch0_tx_conf0(&self) -> &CH_TX_CONF0

0x10 - Channel 0 configure register 0

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pub const fn ch1_tx_conf0(&self) -> &CH_TX_CONF0

0x14 - Channel 1 configure register 0

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pub const fn ch_rx_conf0(&self, n: usize) -> &CH_RX_CONF0

0x18..0x20 - Channel %s configure register 0

`n` is the index of register in the array. `n == 0` corresponds to `CH2_RX_CONF0` register.
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pub fn ch_rx_conf0_iter(&self) -> impl Iterator<Item = &CH_RX_CONF0>

Iterator for array of: 0x18..0x20 - Channel %s configure register 0

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pub const fn ch2_rx_conf0(&self) -> &CH_RX_CONF0

0x18 - Channel 2 configure register 0

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pub const fn ch3_rx_conf0(&self) -> &CH_RX_CONF0

0x20 - Channel 3 configure register 0

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pub const fn ch_rx_conf1(&self, n: usize) -> &CH_RX_CONF1

0x1c..0x24 - Channel %s configure register 1

`n` is the index of register in the array. `n == 0` corresponds to `CH2_RX_CONF1` register.
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pub fn ch_rx_conf1_iter(&self) -> impl Iterator<Item = &CH_RX_CONF1>

Iterator for array of: 0x1c..0x24 - Channel %s configure register 1

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pub const fn ch2_rx_conf1(&self) -> &CH_RX_CONF1

0x1c - Channel 2 configure register 1

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pub const fn ch3_rx_conf1(&self) -> &CH_RX_CONF1

0x24 - Channel 3 configure register 1

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pub const fn ch_tx_status(&self, n: usize) -> &CH_TX_STATUS

0x28..0x30 - Channel %s status register

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pub fn ch_tx_status_iter(&self) -> impl Iterator<Item = &CH_TX_STATUS>

Iterator for array of: 0x28..0x30 - Channel %s status register

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pub const fn ch0_tx_status(&self) -> &CH_TX_STATUS

0x28 - Channel 0 status register

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pub const fn ch1_tx_status(&self) -> &CH_TX_STATUS

0x2c - Channel 1 status register

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pub const fn ch_rx_status(&self, n: usize) -> &CH_RX_STATUS

0x30..0x38 - Channel %s status register

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pub fn ch_rx_status_iter(&self) -> impl Iterator<Item = &CH_RX_STATUS>

Iterator for array of: 0x30..0x38 - Channel %s status register

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pub const fn ch0_rx_status(&self) -> &CH_RX_STATUS

0x30 - Channel 0 status register

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pub const fn ch1_rx_status(&self) -> &CH_RX_STATUS

0x34 - Channel 1 status register

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pub const fn int_raw(&self) -> &INT_RAW

0x38 - Raw interrupt status

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pub const fn int_st(&self) -> &INT_ST

0x3c - Masked interrupt status

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pub const fn int_ena(&self) -> &INT_ENA

0x40 - Interrupt enable bits

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pub const fn int_clr(&self) -> &INT_CLR

0x44 - Interrupt clear bits

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pub const fn chcarrier_duty(&self, n: usize) -> &CHCARRIER_DUTY

0x48..0x50 - Channel %s duty cycle configuration register

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pub fn chcarrier_duty_iter(&self) -> impl Iterator<Item = &CHCARRIER_DUTY>

Iterator for array of: 0x48..0x50 - Channel %s duty cycle configuration register

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pub const fn ch0carrier_duty(&self) -> &CHCARRIER_DUTY

0x48 - Channel 0 duty cycle configuration register

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pub const fn ch1carrier_duty(&self) -> &CHCARRIER_DUTY

0x4c - Channel 1 duty cycle configuration register

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pub const fn ch_rx_carrier_rm(&self, n: usize) -> &CH_RX_CARRIER_RM

0x50..0x58 - Channel %s carrier remove register

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pub fn ch_rx_carrier_rm_iter(&self) -> impl Iterator<Item = &CH_RX_CARRIER_RM>

Iterator for array of: 0x50..0x58 - Channel %s carrier remove register

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pub const fn ch0_rx_carrier_rm(&self) -> &CH_RX_CARRIER_RM

0x50 - Channel 0 carrier remove register

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pub const fn ch1_rx_carrier_rm(&self) -> &CH_RX_CARRIER_RM

0x54 - Channel 1 carrier remove register

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pub const fn ch_tx_lim(&self, n: usize) -> &CH_TX_LIM

0x58..0x60 - Channel %s Tx event configuration register

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pub fn ch_tx_lim_iter(&self) -> impl Iterator<Item = &CH_TX_LIM>

Iterator for array of: 0x58..0x60 - Channel %s Tx event configuration register

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pub const fn ch0_tx_lim(&self) -> &CH_TX_LIM

0x58 - Channel 0 Tx event configuration register

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pub const fn ch1_tx_lim(&self) -> &CH_TX_LIM

0x5c - Channel 1 Tx event configuration register

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pub const fn ch_rx_lim(&self, n: usize) -> &CH_RX_LIM

0x60..0x68 - Channel %s Rx event configuration register

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pub fn ch_rx_lim_iter(&self) -> impl Iterator<Item = &CH_RX_LIM>

Iterator for array of: 0x60..0x68 - Channel %s Rx event configuration register

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pub const fn ch0_rx_lim(&self) -> &CH_RX_LIM

0x60 - Channel 0 Rx event configuration register

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pub const fn ch1_rx_lim(&self) -> &CH_RX_LIM

0x64 - Channel 1 Rx event configuration register

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pub const fn sys_conf(&self) -> &SYS_CONF

0x68 - RMT apb configuration register

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pub const fn tx_sim(&self) -> &TX_SIM

0x6c - RMT TX synchronous register

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pub const fn ref_cnt_rst(&self) -> &REF_CNT_RST

0x70 - RMT clock divider reset register

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pub const fn date(&self) -> &DATE

0xcc - RMT version register

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