esp32h2/i2c_ana_mst/
i2c_ctrl1.rs

1#[doc = "Register `I2C%s_CTRL1` reader"]
2pub type R = crate::R<I2C_CTRL1_SPEC>;
3#[doc = "Register `I2C%s_CTRL1` writer"]
4pub type W = crate::W<I2C_CTRL1_SPEC>;
5#[doc = "Field `SCL_PULSE_DUR` reader - Configures the duration of the high-level period of the SCL driven by I2C0"]
6pub type SCL_PULSE_DUR_R = crate::FieldReader;
7#[doc = "Field `SCL_PULSE_DUR` writer - Configures the duration of the high-level period of the SCL driven by I2C0"]
8pub type SCL_PULSE_DUR_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `SDA_SIDE_GUARD` reader - Configures the duration of the low-level period of the SCL driven by I2C0"]
10pub type SDA_SIDE_GUARD_R = crate::FieldReader;
11#[doc = "Field `SDA_SIDE_GUARD` writer - Configures the duration of the low-level period of the SCL driven by I2C0"]
12pub type SDA_SIDE_GUARD_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13impl R {
14    #[doc = "Bits 0:5 - Configures the duration of the high-level period of the SCL driven by I2C0"]
15    #[inline(always)]
16    pub fn scl_pulse_dur(&self) -> SCL_PULSE_DUR_R {
17        SCL_PULSE_DUR_R::new((self.bits & 0x3f) as u8)
18    }
19    #[doc = "Bits 6:10 - Configures the duration of the low-level period of the SCL driven by I2C0"]
20    #[inline(always)]
21    pub fn sda_side_guard(&self) -> SDA_SIDE_GUARD_R {
22        SDA_SIDE_GUARD_R::new(((self.bits >> 6) & 0x1f) as u8)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("I2C_CTRL1")
29            .field("scl_pulse_dur", &self.scl_pulse_dur())
30            .field("sda_side_guard", &self.sda_side_guard())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 0:5 - Configures the duration of the high-level period of the SCL driven by I2C0"]
36    #[inline(always)]
37    pub fn scl_pulse_dur(&mut self) -> SCL_PULSE_DUR_W<I2C_CTRL1_SPEC> {
38        SCL_PULSE_DUR_W::new(self, 0)
39    }
40    #[doc = "Bits 6:10 - Configures the duration of the low-level period of the SCL driven by I2C0"]
41    #[inline(always)]
42    pub fn sda_side_guard(&mut self) -> SDA_SIDE_GUARD_W<I2C_CTRL1_SPEC> {
43        SDA_SIDE_GUARD_W::new(self, 6)
44    }
45}
46#[doc = "I2C%s_CTRL1 register\n\nYou can [`read`](crate::Reg::read) this register and get [`i2c_ctrl1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`i2c_ctrl1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct I2C_CTRL1_SPEC;
48impl crate::RegisterSpec for I2C_CTRL1_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`i2c_ctrl1::R`](R) reader structure"]
52impl crate::Readable for I2C_CTRL1_SPEC {}
53#[doc = "`write(|w| ..)` method takes [`i2c_ctrl1::W`](W) writer structure"]
54impl crate::Writable for I2C_CTRL1_SPEC {
55    type Safety = crate::Unsafe;
56    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
57    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
58}
59#[doc = "`reset()` method sets I2C%s_CTRL1 to value 0x42"]
60impl crate::Resettable for I2C_CTRL1_SPEC {
61    const RESET_VALUE: u32 = 0x42;
62}
esp32h2/i2c_ana_mst/i2c_ctrl1.rs

esp32h2/i2c_ana_mst/
i2c_ctrl1.rs
