esp32h2/clint/
mtimectl.rs

1#[doc = "Register `MTIMECTL` reader"]
2pub type R = crate::R<MTIMECTL_SPEC>;
3#[doc = "Register `MTIMECTL` writer"]
4pub type W = crate::W<MTIMECTL_SPEC>;
5#[doc = "Field `MTCE` reader - Configures whether to enable the CLINT timer counter."]
6pub type MTCE_R = crate::BitReader;
7#[doc = "Field `MTCE` writer - Configures whether to enable the CLINT timer counter."]
8pub type MTCE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `MTIE` reader - Write 1 to enable the machine timer interrupt."]
10pub type MTIE_R = crate::BitReader;
11#[doc = "Field `MTIE` writer - Write 1 to enable the machine timer interrupt."]
12pub type MTIE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MTIP` reader - Represents the pending status of the machine timer interrupt."]
14pub type MTIP_R = crate::BitReader;
15#[doc = "Field `MTOF` reader - Configures whether the machine timer overflows."]
16pub type MTOF_R = crate::BitReader;
17#[doc = "Field `MTOF` writer - Configures whether the machine timer overflows."]
18pub type MTOF_W<'a, REG> = crate::BitWriter<'a, REG>;
19impl R {
20    #[doc = "Bit 0 - Configures whether to enable the CLINT timer counter."]
21    #[inline(always)]
22    pub fn mtce(&self) -> MTCE_R {
23        MTCE_R::new((self.bits & 1) != 0)
24    }
25    #[doc = "Bit 1 - Write 1 to enable the machine timer interrupt."]
26    #[inline(always)]
27    pub fn mtie(&self) -> MTIE_R {
28        MTIE_R::new(((self.bits >> 1) & 1) != 0)
29    }
30    #[doc = "Bit 2 - Represents the pending status of the machine timer interrupt."]
31    #[inline(always)]
32    pub fn mtip(&self) -> MTIP_R {
33        MTIP_R::new(((self.bits >> 2) & 1) != 0)
34    }
35    #[doc = "Bit 3 - Configures whether the machine timer overflows."]
36    #[inline(always)]
37    pub fn mtof(&self) -> MTOF_R {
38        MTOF_R::new(((self.bits >> 3) & 1) != 0)
39    }
40}
41#[cfg(feature = "impl-register-debug")]
42impl core::fmt::Debug for R {
43    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
44        f.debug_struct("MTIMECTL")
45            .field("mtce", &self.mtce())
46            .field("mtie", &self.mtie())
47            .field("mtip", &self.mtip())
48            .field("mtof", &self.mtof())
49            .finish()
50    }
51}
52impl W {
53    #[doc = "Bit 0 - Configures whether to enable the CLINT timer counter."]
54    #[inline(always)]
55    pub fn mtce(&mut self) -> MTCE_W<MTIMECTL_SPEC> {
56        MTCE_W::new(self, 0)
57    }
58    #[doc = "Bit 1 - Write 1 to enable the machine timer interrupt."]
59    #[inline(always)]
60    pub fn mtie(&mut self) -> MTIE_W<MTIMECTL_SPEC> {
61        MTIE_W::new(self, 1)
62    }
63    #[doc = "Bit 3 - Configures whether the machine timer overflows."]
64    #[inline(always)]
65    pub fn mtof(&mut self) -> MTOF_W<MTIMECTL_SPEC> {
66        MTOF_W::new(self, 3)
67    }
68}
69#[doc = "\n\nYou can [`read`](crate::Reg::read) this register and get [`mtimectl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mtimectl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
70pub struct MTIMECTL_SPEC;
71impl crate::RegisterSpec for MTIMECTL_SPEC {
72    type Ux = u32;
73}
74#[doc = "`read()` method returns [`mtimectl::R`](R) reader structure"]
75impl crate::Readable for MTIMECTL_SPEC {}
76#[doc = "`write(|w| ..)` method takes [`mtimectl::W`](W) writer structure"]
77impl crate::Writable for MTIMECTL_SPEC {
78    type Safety = crate::Unsafe;
79    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
80    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
81}
82#[doc = "`reset()` method sets MTIMECTL to value 0"]
83impl crate::Resettable for MTIMECTL_SPEC {
84    const RESET_VALUE: u32 = 0;
85}
esp32h2/clint/mtimectl.rs

esp32h2/clint/
mtimectl.rs
