1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5 sigmadelta: [SIGMADELTA; 4],
6 _reserved1: [u8; 0x10],
7 clock_gate: CLOCK_GATE,
8 sigmadelta_misc: SIGMADELTA_MISC,
9 pad_comp_config: PAD_COMP_CONFIG,
10 pad_comp_filter: PAD_COMP_FILTER,
11 glitch_filter_ch: [GLITCH_FILTER_CH; 8],
12 _reserved6: [u8; 0x10],
13 etm_event_ch_cfg: [ETM_EVENT_CH_CFG; 8],
14 _reserved7: [u8; 0x20],
15 etm_task_p0_cfg: ETM_TASK_P0_CFG,
16 etm_task_p1_cfg: ETM_TASK_P1_CFG,
17 etm_task_p2_cfg: ETM_TASK_P2_CFG,
18 etm_task_p3_cfg: ETM_TASK_P3_CFG,
19 etm_task_p4_cfg: ETM_TASK_P4_CFG,
20 etm_task_p5_cfg: ETM_TASK_P5_CFG,
21 etm_task_p6_cfg: ETM_TASK_P6_CFG,
22 _reserved14: [u8; 0x24],
23 int_raw: INT_RAW,
24 int_st: INT_ST,
25 int_ena: INT_ENA,
26 int_clr: INT_CLR,
27 _reserved18: [u8; 0x0c],
28 version: VERSION,
29}
30impl RegisterBlock {
31 #[doc = "0x00..0x10 - Duty Cycle Configure Register of SDM%s"]
32 #[inline(always)]
33 pub const fn sigmadelta(&self, n: usize) -> &SIGMADELTA {
34 &self.sigmadelta[n]
35 }
36 #[doc = "Iterator for array of:"]
37 #[doc = "0x00..0x10 - Duty Cycle Configure Register of SDM%s"]
38 #[inline(always)]
39 pub fn sigmadelta_iter(&self) -> impl Iterator<Item = &SIGMADELTA> {
40 self.sigmadelta.iter()
41 }
42 #[doc = "0x20 - Clock Gating Configure Register"]
43 #[inline(always)]
44 pub const fn clock_gate(&self) -> &CLOCK_GATE {
45 &self.clock_gate
46 }
47 #[doc = "0x24 - MISC Register"]
48 #[inline(always)]
49 pub const fn sigmadelta_misc(&self) -> &SIGMADELTA_MISC {
50 &self.sigmadelta_misc
51 }
52 #[doc = "0x28 - PAD Compare configure Register"]
53 #[inline(always)]
54 pub const fn pad_comp_config(&self) -> &PAD_COMP_CONFIG {
55 &self.pad_comp_config
56 }
57 #[doc = "0x2c - Zero Detect filter Register"]
58 #[inline(always)]
59 pub const fn pad_comp_filter(&self) -> &PAD_COMP_FILTER {
60 &self.pad_comp_filter
61 }
62 #[doc = "0x30..0x50 - Glitch Filter Configure Register of Channel%s"]
63 #[inline(always)]
64 pub const fn glitch_filter_ch(&self, n: usize) -> &GLITCH_FILTER_CH {
65 &self.glitch_filter_ch[n]
66 }
67 #[doc = "Iterator for array of:"]
68 #[doc = "0x30..0x50 - Glitch Filter Configure Register of Channel%s"]
69 #[inline(always)]
70 pub fn glitch_filter_ch_iter(&self) -> impl Iterator<Item = &GLITCH_FILTER_CH> {
71 self.glitch_filter_ch.iter()
72 }
73 #[doc = "0x60..0x80 - Etm Config register of Channel%s"]
74 #[inline(always)]
75 pub const fn etm_event_ch_cfg(&self, n: usize) -> &ETM_EVENT_CH_CFG {
76 &self.etm_event_ch_cfg[n]
77 }
78 #[doc = "Iterator for array of:"]
79 #[doc = "0x60..0x80 - Etm Config register of Channel%s"]
80 #[inline(always)]
81 pub fn etm_event_ch_cfg_iter(&self) -> impl Iterator<Item = &ETM_EVENT_CH_CFG> {
82 self.etm_event_ch_cfg.iter()
83 }
84 #[doc = "0x60 - Etm Config register of Channel0"]
85 #[inline(always)]
86 pub const fn etm_event_ch0_cfg(&self) -> &ETM_EVENT_CH_CFG {
87 self.etm_event_ch_cfg(0)
88 }
89 #[doc = "0x64 - Etm Config register of Channel1"]
90 #[inline(always)]
91 pub const fn etm_event_ch1_cfg(&self) -> &ETM_EVENT_CH_CFG {
92 self.etm_event_ch_cfg(1)
93 }
94 #[doc = "0x68 - Etm Config register of Channel2"]
95 #[inline(always)]
96 pub const fn etm_event_ch2_cfg(&self) -> &ETM_EVENT_CH_CFG {
97 self.etm_event_ch_cfg(2)
98 }
99 #[doc = "0x6c - Etm Config register of Channel3"]
100 #[inline(always)]
101 pub const fn etm_event_ch3_cfg(&self) -> &ETM_EVENT_CH_CFG {
102 self.etm_event_ch_cfg(3)
103 }
104 #[doc = "0x70 - Etm Config register of Channel4"]
105 #[inline(always)]
106 pub const fn etm_event_ch4_cfg(&self) -> &ETM_EVENT_CH_CFG {
107 self.etm_event_ch_cfg(4)
108 }
109 #[doc = "0x74 - Etm Config register of Channel5"]
110 #[inline(always)]
111 pub const fn etm_event_ch5_cfg(&self) -> &ETM_EVENT_CH_CFG {
112 self.etm_event_ch_cfg(5)
113 }
114 #[doc = "0x78 - Etm Config register of Channel6"]
115 #[inline(always)]
116 pub const fn etm_event_ch6_cfg(&self) -> &ETM_EVENT_CH_CFG {
117 self.etm_event_ch_cfg(6)
118 }
119 #[doc = "0x7c - Etm Config register of Channel7"]
120 #[inline(always)]
121 pub const fn etm_event_ch7_cfg(&self) -> &ETM_EVENT_CH_CFG {
122 self.etm_event_ch_cfg(7)
123 }
124 #[doc = "0xa0 - Etm Configure Register to decide which GPIO been chosen"]
125 #[inline(always)]
126 pub const fn etm_task_p0_cfg(&self) -> &ETM_TASK_P0_CFG {
127 &self.etm_task_p0_cfg
128 }
129 #[doc = "0xa4 - Etm Configure Register to decide which GPIO been chosen"]
130 #[inline(always)]
131 pub const fn etm_task_p1_cfg(&self) -> &ETM_TASK_P1_CFG {
132 &self.etm_task_p1_cfg
133 }
134 #[doc = "0xa8 - Etm Configure Register to decide which GPIO been chosen"]
135 #[inline(always)]
136 pub const fn etm_task_p2_cfg(&self) -> &ETM_TASK_P2_CFG {
137 &self.etm_task_p2_cfg
138 }
139 #[doc = "0xac - Etm Configure Register to decide which GPIO been chosen"]
140 #[inline(always)]
141 pub const fn etm_task_p3_cfg(&self) -> &ETM_TASK_P3_CFG {
142 &self.etm_task_p3_cfg
143 }
144 #[doc = "0xb0 - Etm Configure Register to decide which GPIO been chosen"]
145 #[inline(always)]
146 pub const fn etm_task_p4_cfg(&self) -> &ETM_TASK_P4_CFG {
147 &self.etm_task_p4_cfg
148 }
149 #[doc = "0xb4 - Etm Configure Register to decide which GPIO been chosen"]
150 #[inline(always)]
151 pub const fn etm_task_p5_cfg(&self) -> &ETM_TASK_P5_CFG {
152 &self.etm_task_p5_cfg
153 }
154 #[doc = "0xb8 - Etm Configure Register to decide which GPIO been chosen"]
155 #[inline(always)]
156 pub const fn etm_task_p6_cfg(&self) -> &ETM_TASK_P6_CFG {
157 &self.etm_task_p6_cfg
158 }
159 #[doc = "0xe0 - GPIOSD interrupt raw register"]
160 #[inline(always)]
161 pub const fn int_raw(&self) -> &INT_RAW {
162 &self.int_raw
163 }
164 #[doc = "0xe4 - GPIOSD interrupt masked register"]
165 #[inline(always)]
166 pub const fn int_st(&self) -> &INT_ST {
167 &self.int_st
168 }
169 #[doc = "0xe8 - GPIOSD interrupt enable register"]
170 #[inline(always)]
171 pub const fn int_ena(&self) -> &INT_ENA {
172 &self.int_ena
173 }
174 #[doc = "0xec - GPIOSD interrupt clear register"]
175 #[inline(always)]
176 pub const fn int_clr(&self) -> &INT_CLR {
177 &self.int_clr
178 }
179 #[doc = "0xfc - Version Control Register"]
180 #[inline(always)]
181 pub const fn version(&self) -> &VERSION {
182 &self.version
183 }
184}
185#[doc = "SIGMADELTA (rw) register accessor: Duty Cycle Configure Register of SDM%s\n\nYou can [`read`](crate::Reg::read) this register and get [`sigmadelta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigmadelta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigmadelta`] module"]
186pub type SIGMADELTA = crate::Reg<sigmadelta::SIGMADELTA_SPEC>;
187#[doc = "Duty Cycle Configure Register of SDM%s"]
188pub mod sigmadelta;
189#[doc = "CLOCK_GATE (rw) register accessor: Clock Gating Configure Register\n\nYou can [`read`](crate::Reg::read) this register and get [`clock_gate::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clock_gate::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clock_gate`] module"]
190pub type CLOCK_GATE = crate::Reg<clock_gate::CLOCK_GATE_SPEC>;
191#[doc = "Clock Gating Configure Register"]
192pub mod clock_gate;
193#[doc = "SIGMADELTA_MISC (rw) register accessor: MISC Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sigmadelta_misc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sigmadelta_misc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sigmadelta_misc`] module"]
194pub type SIGMADELTA_MISC = crate::Reg<sigmadelta_misc::SIGMADELTA_MISC_SPEC>;
195#[doc = "MISC Register"]
196pub mod sigmadelta_misc;
197#[doc = "PAD_COMP_CONFIG (rw) register accessor: PAD Compare configure Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_comp_config::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_comp_config::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_comp_config`] module"]
198pub type PAD_COMP_CONFIG = crate::Reg<pad_comp_config::PAD_COMP_CONFIG_SPEC>;
199#[doc = "PAD Compare configure Register"]
200pub mod pad_comp_config;
201#[doc = "PAD_COMP_FILTER (rw) register accessor: Zero Detect filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`pad_comp_filter::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pad_comp_filter::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pad_comp_filter`] module"]
202pub type PAD_COMP_FILTER = crate::Reg<pad_comp_filter::PAD_COMP_FILTER_SPEC>;
203#[doc = "Zero Detect filter Register"]
204pub mod pad_comp_filter;
205#[doc = "GLITCH_FILTER_CH (rw) register accessor: Glitch Filter Configure Register of Channel%s\n\nYou can [`read`](crate::Reg::read) this register and get [`glitch_filter_ch::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`glitch_filter_ch::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@glitch_filter_ch`] module"]
206pub type GLITCH_FILTER_CH = crate::Reg<glitch_filter_ch::GLITCH_FILTER_CH_SPEC>;
207#[doc = "Glitch Filter Configure Register of Channel%s"]
208pub mod glitch_filter_ch;
209#[doc = "ETM_EVENT_CH_CFG (rw) register accessor: Etm Config register of Channel%s\n\nYou can [`read`](crate::Reg::read) this register and get [`etm_event_ch_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etm_event_ch_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_event_ch_cfg`] module"]
210pub type ETM_EVENT_CH_CFG = crate::Reg<etm_event_ch_cfg::ETM_EVENT_CH_CFG_SPEC>;
211#[doc = "Etm Config register of Channel%s"]
212pub mod etm_event_ch_cfg;
213#[doc = "ETM_TASK_P0_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::Reg::read) this register and get [`etm_task_p0_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etm_task_p0_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p0_cfg`] module"]
214pub type ETM_TASK_P0_CFG = crate::Reg<etm_task_p0_cfg::ETM_TASK_P0_CFG_SPEC>;
215#[doc = "Etm Configure Register to decide which GPIO been chosen"]
216pub mod etm_task_p0_cfg;
217#[doc = "ETM_TASK_P1_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::Reg::read) this register and get [`etm_task_p1_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etm_task_p1_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p1_cfg`] module"]
218pub type ETM_TASK_P1_CFG = crate::Reg<etm_task_p1_cfg::ETM_TASK_P1_CFG_SPEC>;
219#[doc = "Etm Configure Register to decide which GPIO been chosen"]
220pub mod etm_task_p1_cfg;
221#[doc = "ETM_TASK_P2_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::Reg::read) this register and get [`etm_task_p2_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etm_task_p2_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p2_cfg`] module"]
222pub type ETM_TASK_P2_CFG = crate::Reg<etm_task_p2_cfg::ETM_TASK_P2_CFG_SPEC>;
223#[doc = "Etm Configure Register to decide which GPIO been chosen"]
224pub mod etm_task_p2_cfg;
225#[doc = "ETM_TASK_P3_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::Reg::read) this register and get [`etm_task_p3_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etm_task_p3_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p3_cfg`] module"]
226pub type ETM_TASK_P3_CFG = crate::Reg<etm_task_p3_cfg::ETM_TASK_P3_CFG_SPEC>;
227#[doc = "Etm Configure Register to decide which GPIO been chosen"]
228pub mod etm_task_p3_cfg;
229#[doc = "ETM_TASK_P4_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::Reg::read) this register and get [`etm_task_p4_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etm_task_p4_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p4_cfg`] module"]
230pub type ETM_TASK_P4_CFG = crate::Reg<etm_task_p4_cfg::ETM_TASK_P4_CFG_SPEC>;
231#[doc = "Etm Configure Register to decide which GPIO been chosen"]
232pub mod etm_task_p4_cfg;
233#[doc = "ETM_TASK_P5_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::Reg::read) this register and get [`etm_task_p5_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etm_task_p5_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p5_cfg`] module"]
234pub type ETM_TASK_P5_CFG = crate::Reg<etm_task_p5_cfg::ETM_TASK_P5_CFG_SPEC>;
235#[doc = "Etm Configure Register to decide which GPIO been chosen"]
236pub mod etm_task_p5_cfg;
237#[doc = "ETM_TASK_P6_CFG (rw) register accessor: Etm Configure Register to decide which GPIO been chosen\n\nYou can [`read`](crate::Reg::read) this register and get [`etm_task_p6_cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`etm_task_p6_cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@etm_task_p6_cfg`] module"]
238pub type ETM_TASK_P6_CFG = crate::Reg<etm_task_p6_cfg::ETM_TASK_P6_CFG_SPEC>;
239#[doc = "Etm Configure Register to decide which GPIO been chosen"]
240pub mod etm_task_p6_cfg;
241#[doc = "INT_RAW (r) register accessor: GPIOSD interrupt raw register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_raw`] module"]
242pub type INT_RAW = crate::Reg<int_raw::INT_RAW_SPEC>;
243#[doc = "GPIOSD interrupt raw register"]
244pub mod int_raw;
245#[doc = "INT_ST (r) register accessor: GPIOSD interrupt masked register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_st`] module"]
246pub type INT_ST = crate::Reg<int_st::INT_ST_SPEC>;
247#[doc = "GPIOSD interrupt masked register"]
248pub mod int_st;
249#[doc = "INT_ENA (rw) register accessor: GPIOSD interrupt enable register\n\nYou can [`read`](crate::Reg::read) this register and get [`int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_ena`] module"]
250pub type INT_ENA = crate::Reg<int_ena::INT_ENA_SPEC>;
251#[doc = "GPIOSD interrupt enable register"]
252pub mod int_ena;
253#[doc = "INT_CLR (w) register accessor: GPIOSD interrupt clear register\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@int_clr`] module"]
254pub type INT_CLR = crate::Reg<int_clr::INT_CLR_SPEC>;
255#[doc = "GPIOSD interrupt clear register"]
256pub mod int_clr;
257#[doc = "VERSION (rw) register accessor: Version Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`version::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`version::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@version`] module"]
258pub type VERSION = crate::Reg<version::VERSION_SPEC>;
259#[doc = "Version Control Register"]
260pub mod version;