esp32h2/dma/out_int_ch/
clr.rs

1#[doc = "Register `CLR` writer"]
2pub type W = crate::W<CLR_SPEC>;
3#[doc = "Field `OUT_DONE` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."]
4pub type OUT_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `OUT_EOF` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."]
6pub type OUT_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `OUT_DSCR_ERR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."]
8pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `OUT_TOTAL_EOF` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."]
10pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `OUTFIFO_OVF` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."]
12pub type OUTFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `OUTFIFO_UDF` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."]
14pub type OUTFIFO_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[cfg(feature = "impl-register-debug")]
16impl core::fmt::Debug for crate::generic::Reg<CLR_SPEC> {
17    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
18        write!(f, "(not readable)")
19    }
20}
21impl W {
22    #[doc = "Bit 0 - Set this bit to clear the OUT_DONE_CH_INT interrupt."]
23    #[inline(always)]
24    pub fn out_done(&mut self) -> OUT_DONE_W<CLR_SPEC> {
25        OUT_DONE_W::new(self, 0)
26    }
27    #[doc = "Bit 1 - Set this bit to clear the OUT_EOF_CH_INT interrupt."]
28    #[inline(always)]
29    pub fn out_eof(&mut self) -> OUT_EOF_W<CLR_SPEC> {
30        OUT_EOF_W::new(self, 1)
31    }
32    #[doc = "Bit 2 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."]
33    #[inline(always)]
34    pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<CLR_SPEC> {
35        OUT_DSCR_ERR_W::new(self, 2)
36    }
37    #[doc = "Bit 3 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."]
38    #[inline(always)]
39    pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<CLR_SPEC> {
40        OUT_TOTAL_EOF_W::new(self, 3)
41    }
42    #[doc = "Bit 4 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."]
43    #[inline(always)]
44    pub fn outfifo_ovf(&mut self) -> OUTFIFO_OVF_W<CLR_SPEC> {
45        OUTFIFO_OVF_W::new(self, 4)
46    }
47    #[doc = "Bit 5 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."]
48    #[inline(always)]
49    pub fn outfifo_udf(&mut self) -> OUTFIFO_UDF_W<CLR_SPEC> {
50        OUTFIFO_UDF_W::new(self, 5)
51    }
52}
53#[doc = "Interrupt clear bits of channel 0\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
54pub struct CLR_SPEC;
55impl crate::RegisterSpec for CLR_SPEC {
56    type Ux = u32;
57}
58#[doc = "`write(|w| ..)` method takes [`clr::W`](W) writer structure"]
59impl crate::Writable for CLR_SPEC {
60    type Safety = crate::Unsafe;
61    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
62    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3f;
63}
64#[doc = "`reset()` method sets CLR to value 0"]
65impl crate::Resettable for CLR_SPEC {
66    const RESET_VALUE: u32 = 0;
67}
esp32h2/dma/out_int_ch/clr.rs

esp32h2/dma/out_int_ch/
clr.rs
