esp32h2::twai0::interrupt

Type Alias R

Source
pub type R = R<INTERRUPT_SPEC>;
Expand description

Register INTERRUPT reader

Aliased Type§

struct R { /* private fields */ }

Implementations§

Source§

impl R

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pub fn receive_int_st(&self) -> RECEIVE_INT_ST_R

Bit 0 - 1: this bit is set while the receive FIFO is not empty and the RIE bit is set within the interrupt enable register. 0: reset

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pub fn transmit_int_st(&self) -> TRANSMIT_INT_ST_R

Bit 1 - 1: this bit is set whenever the transmit buffer status changes from ‘0-to-1’ (released) and the TIE bit is set within the interrupt enable register. 0: reset

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pub fn err_warning_int_st(&self) -> ERR_WARNING_INT_ST_R

Bit 2 - 1: this bit is set on every change (set and clear) of either the error status or bus status bits and the EIE bit is set within the interrupt enable register. 0: reset

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pub fn data_overrun_int_st(&self) -> DATA_OVERRUN_INT_ST_R

Bit 3 - 1: this bit is set on a ‘0-to-1’ transition of the data overrun status bit and the DOIE bit is set within the interrupt enable register. 0: reset

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pub fn err_passive_int_st(&self) -> ERR_PASSIVE_INT_ST_R

Bit 5 - 1: this bit is set whenever the TWAI controller has reached the error passive status (at least one error counter exceeds the protocol-defined level of 127) or if the TWAI controller is in the error passive status and enters the error active status again and the EPIE bit is set within the interrupt enable register. 0: reset

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pub fn arbitration_lost_int_st(&self) -> ARBITRATION_LOST_INT_ST_R

Bit 6 - 1: this bit is set when the TWAI controller lost the arbitration and becomes a receiver and the ALIE bit is set within the interrupt enable register. 0: reset

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pub fn bus_err_int_st(&self) -> BUS_ERR_INT_ST_R

Bit 7 - 1: this bit is set when the TWAI controller detects an error on the TWAI-bus and the BEIE bit is set within the interrupt enable register. 0: reset

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pub fn idle_int_st(&self) -> IDLE_INT_ST_R

Bit 8 - 1: this bit is set when the TWAI controller detects state of TWAI become IDLE and this interrupt enable bit is set within the interrupt enable register. 0: reset