Struct esp32h2::gpio_sd::RegisterBlock

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#[repr(C)]
pub struct RegisterBlock { /* private fields */ }
Expand description

Register block

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impl RegisterBlock

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pub const fn sigmadelta(&self, n: usize) -> &SIGMADELTA

0x00..0x10 - Duty Cycle Configure Register of SDM%s

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pub fn sigmadelta_iter(&self) -> impl Iterator<Item = &SIGMADELTA>

Iterator for array of: 0x00..0x10 - Duty Cycle Configure Register of SDM%s

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pub const fn clock_gate(&self) -> &CLOCK_GATE

0x20 - Clock Gating Configure Register

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pub const fn sigmadelta_misc(&self) -> &SIGMADELTA_MISC

0x24 - MISC Register

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pub const fn pad_comp_config(&self) -> &PAD_COMP_CONFIG

0x28 - PAD Compare configure Register

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pub const fn pad_comp_filter(&self) -> &PAD_COMP_FILTER

0x2c - Zero Detect filter Register

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pub const fn glitch_filter_ch(&self, n: usize) -> &GLITCH_FILTER_CH

0x30..0x50 - Glitch Filter Configure Register of Channel%s

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pub fn glitch_filter_ch_iter(&self) -> impl Iterator<Item = &GLITCH_FILTER_CH>

Iterator for array of: 0x30..0x50 - Glitch Filter Configure Register of Channel%s

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pub const fn etm_event_ch_cfg(&self, n: usize) -> &ETM_EVENT_CH_CFG

0x60..0x80 - Etm Config register of Channel%s

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pub fn etm_event_ch_cfg_iter(&self) -> impl Iterator<Item = &ETM_EVENT_CH_CFG>

Iterator for array of: 0x60..0x80 - Etm Config register of Channel%s

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pub const fn etm_event_ch0_cfg(&self) -> &ETM_EVENT_CH_CFG

0x60 - Etm Config register of Channel0

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pub const fn etm_event_ch1_cfg(&self) -> &ETM_EVENT_CH_CFG

0x64 - Etm Config register of Channel1

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pub const fn etm_event_ch2_cfg(&self) -> &ETM_EVENT_CH_CFG

0x68 - Etm Config register of Channel2

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pub const fn etm_event_ch3_cfg(&self) -> &ETM_EVENT_CH_CFG

0x6c - Etm Config register of Channel3

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pub const fn etm_event_ch4_cfg(&self) -> &ETM_EVENT_CH_CFG

0x70 - Etm Config register of Channel4

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pub const fn etm_event_ch5_cfg(&self) -> &ETM_EVENT_CH_CFG

0x74 - Etm Config register of Channel5

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pub const fn etm_event_ch6_cfg(&self) -> &ETM_EVENT_CH_CFG

0x78 - Etm Config register of Channel6

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pub const fn etm_event_ch7_cfg(&self) -> &ETM_EVENT_CH_CFG

0x7c - Etm Config register of Channel7

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pub const fn etm_task_p0_cfg(&self) -> &ETM_TASK_P0_CFG

0xa0 - Etm Configure Register to decide which GPIO been chosen

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pub const fn etm_task_p1_cfg(&self) -> &ETM_TASK_P1_CFG

0xa4 - Etm Configure Register to decide which GPIO been chosen

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pub const fn etm_task_p2_cfg(&self) -> &ETM_TASK_P2_CFG

0xa8 - Etm Configure Register to decide which GPIO been chosen

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pub const fn etm_task_p3_cfg(&self) -> &ETM_TASK_P3_CFG

0xac - Etm Configure Register to decide which GPIO been chosen

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pub const fn etm_task_p4_cfg(&self) -> &ETM_TASK_P4_CFG

0xb0 - Etm Configure Register to decide which GPIO been chosen

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pub const fn etm_task_p5_cfg(&self) -> &ETM_TASK_P5_CFG

0xb4 - Etm Configure Register to decide which GPIO been chosen

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pub const fn etm_task_p6_cfg(&self) -> &ETM_TASK_P6_CFG

0xb8 - Etm Configure Register to decide which GPIO been chosen

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pub const fn int_raw(&self) -> &INT_RAW

0xe0 - GPIOSD interrupt raw register

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pub const fn int_st(&self) -> &INT_ST

0xe4 - GPIOSD interrupt masked register

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pub const fn int_ena(&self) -> &INT_ENA

0xe8 - GPIOSD interrupt enable register

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pub const fn int_clr(&self) -> &INT_CLR

0xec - GPIOSD interrupt clear register

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pub const fn version(&self) -> &VERSION

0xfc - Version Control Register

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