Type Alias esp32h2::spi1::cache_fctrl::R

pub type R = R<CACHE_FCTRL_SPEC>;

Register CACHE_FCTRL reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn cache_usr_addr_4byte(&self) -> CACHE_USR_ADDR_4BYTE_R

Bit 1 - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.

pub fn fdin_dual(&self) -> FDIN_DUAL_R

Bit 3 - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

pub fn fdout_dual(&self) -> FDOUT_DUAL_R

Bit 4 - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

pub fn faddr_dual(&self) -> FADDR_DUAL_R

Bit 5 - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

pub fn fdin_quad(&self) -> FDIN_QUAD_R

Bit 6 - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

pub fn fdout_quad(&self) -> FDOUT_QUAD_R

Bit 7 - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

pub fn faddr_quad(&self) -> FADDR_QUAD_R

Bit 8 - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.