Type Alias esp32h2::rmt::int_st::R

pub type R = R<INT_ST_SPEC>;

Register INT_ST reader

Aliased Type

struct R { /* private fields */ }

Implementations

impl R

pub fn ch_tx_end(&self, n: u8) -> CH_TX_END_R

The masked interrupt status bit for CH(0-1)_TX_END_INT.

`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.

pub fn ch_tx_end_iter(&self) -> impl Iterator<Item = CH_TX_END_R> + '_

Iterator for array of: The masked interrupt status bit for CH(0-1)_TX_END_INT.

pub fn ch0_tx_end(&self) -> CH_TX_END_R

Bit 0 - The masked interrupt status bit for CH0_TX_END_INT.

pub fn ch1_tx_end(&self) -> CH_TX_END_R

Bit 1 - The masked interrupt status bit for CH1_TX_END_INT.

pub fn ch_rx_end(&self, n: u8) -> CH_RX_END_R

The masked interrupt status bit for CH2_RX_END_INT.

`n` is number of field in register. `n == 0` corresponds to `CH2_RX_END` field.

pub fn ch_rx_end_iter(&self) -> impl Iterator<Item = CH_RX_END_R> + '_

Iterator for array of: The masked interrupt status bit for CH2_RX_END_INT.

pub fn ch2_rx_end(&self) -> CH_RX_END_R

Bit 2 - The masked interrupt status bit for CH2_RX_END_INT.

pub fn ch3_rx_end(&self) -> CH_RX_END_R

Bit 3 - The masked interrupt status bit for CH2_RX_END_INT.

pub fn ch_tx_err(&self, n: u8) -> CH_TX_ERR_R

The masked interrupt status bit for CH4_ERR_INT.

`n` is number of field in register. `n == 0` corresponds to `CH0_TX_ERR` field.

pub fn ch_tx_err_iter(&self) -> impl Iterator<Item = CH_TX_ERR_R> + '_

Iterator for array of: The masked interrupt status bit for CH4_ERR_INT.

pub fn ch0_tx_err(&self) -> CH_TX_ERR_R

Bit 4 - The masked interrupt status bit for CH4_ERR_INT.

pub fn ch1_tx_err(&self) -> CH_TX_ERR_R

Bit 5 - The masked interrupt status bit for CH4_ERR_INT.

pub fn ch_rx_err(&self, n: u8) -> CH_RX_ERR_R

The masked interrupt status bit for CH6_ERR_INT.

`n` is number of field in register. `n == 0` corresponds to `CH2_RX_ERR` field.

pub fn ch_rx_err_iter(&self) -> impl Iterator<Item = CH_RX_ERR_R> + '_

Iterator for array of: The masked interrupt status bit for CH6_ERR_INT.

pub fn ch2_rx_err(&self) -> CH_RX_ERR_R

Bit 6 - The masked interrupt status bit for CH6_ERR_INT.

pub fn ch3_rx_err(&self) -> CH_RX_ERR_R

Bit 7 - The masked interrupt status bit for CH6_ERR_INT.

pub fn ch_tx_thr_event(&self, n: u8) -> CH_TX_THR_EVENT_R

The masked interrupt status bit for CH(0-1)_TX_THR_EVENT_INT.

`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.

pub fn ch_tx_thr_event_iter( &self, ) -> impl Iterator<Item = CH_TX_THR_EVENT_R> + '_

Iterator for array of: The masked interrupt status bit for CH(0-1)_TX_THR_EVENT_INT.

pub fn ch0_tx_thr_event(&self) -> CH_TX_THR_EVENT_R

Bit 8 - The masked interrupt status bit for CH0_TX_THR_EVENT_INT.

pub fn ch1_tx_thr_event(&self) -> CH_TX_THR_EVENT_R

Bit 9 - The masked interrupt status bit for CH1_TX_THR_EVENT_INT.

pub fn ch_rx_thr_event(&self, n: u8) -> CH_RX_THR_EVENT_R

The masked interrupt status bit for CH2_RX_THR_EVENT_INT.

`n` is number of field in register. `n == 0` corresponds to `CH2_RX_THR_EVENT` field.

pub fn ch_rx_thr_event_iter( &self, ) -> impl Iterator<Item = CH_RX_THR_EVENT_R> + '_

Iterator for array of: The masked interrupt status bit for CH2_RX_THR_EVENT_INT.

pub fn ch2_rx_thr_event(&self) -> CH_RX_THR_EVENT_R

Bit 10 - The masked interrupt status bit for CH2_RX_THR_EVENT_INT.

pub fn ch3_rx_thr_event(&self) -> CH_RX_THR_EVENT_R

Bit 11 - The masked interrupt status bit for CH2_RX_THR_EVENT_INT.

pub fn ch_x_loop(&self, n: u8) -> CH_X_LOOP_R

The masked interrupt status bit for CH(0-1)_TX_LOOP_INT.

`n` is number of field in register. `n == 0` corresponds to `CH0_X_LOOP` field.

pub fn ch_x_loop_iter(&self) -> impl Iterator<Item = CH_X_LOOP_R> + '_

Iterator for array of: The masked interrupt status bit for CH(0-1)_TX_LOOP_INT.

pub fn ch0_x_loop(&self) -> CH_X_LOOP_R

Bit 12 - The masked interrupt status bit for CH0_TX_LOOP_INT.

pub fn ch1_x_loop(&self) -> CH_X_LOOP_R

Bit 13 - The masked interrupt status bit for CH1_TX_LOOP_INT.