Module esp32h2::spi0::ddr

SPI0 flash DDR mode control register

Structs

• DDR_SPEC
  SPI0 flash DDR mode control register

Type Aliases

• R
  Register DDR reader
• SPI_FMEM_CLK_DIFF_EN_R
  Field SPI_FMEM_CLK_DIFF_EN reader - Set this bit to enable the differential SPI_CLK#.
• SPI_FMEM_CLK_DIFF_INV_R
  Field SPI_FMEM_CLK_DIFF_INV reader - Set this bit to invert SPI_DIFF when accesses to flash. .
• SPI_FMEM_DDR_CMD_DIS_R
  Field SPI_FMEM_DDR_CMD_DIS reader - the bit is used to disable dual edge in command phase when DDR mode.
• SPI_FMEM_DDR_DQS_LOOP_R
  Field SPI_FMEM_DDR_DQS_LOOP reader - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.
• SPI_FMEM_DDR_EN_R
  Field SPI_FMEM_DDR_EN reader - 1: in DDR mode, 0 in SDR mode
• SPI_FMEM_DDR_RDAT_SWP_R
  Field SPI_FMEM_DDR_RDAT_SWP reader - Set the bit to reorder rx data of the word in spi DDR mode.
• SPI_FMEM_DDR_WDAT_SWP_R
  Field SPI_FMEM_DDR_WDAT_SWP reader - Set the bit to reorder tx data of the word in spi DDR mode.
• SPI_FMEM_DQS_CA_IN_R
  Field SPI_FMEM_DQS_CA_IN reader - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
• SPI_FMEM_HYPERBUS_CA_R
  Field SPI_FMEM_HYPERBUS_CA reader - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13’d0, spi_usr_addr_value[3:1]}.
• SPI_FMEM_HYPERBUS_DUMMY_2X_R
  Field SPI_FMEM_HYPERBUS_DUMMY_2X reader - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.
• SPI_FMEM_OCTA_RAM_ADDR_R
  Field SPI_FMEM_OCTA_RAM_ADDR reader - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6’d0, spi_usr_addr_value[3:1], 1’b0}.
• SPI_FMEM_OUTMINBYTELEN_R
  Field SPI_FMEM_OUTMINBYTELEN reader - It is the minimum output data length in the panda device.
• SPI_FMEM_RX_DDR_MSK_EN_R
  Field SPI_FMEM_RX_DDR_MSK_EN reader - Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to flash.
• SPI_FMEM_TX_DDR_MSK_EN_R
  Field SPI_FMEM_TX_DDR_MSK_EN reader - Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to flash.
• SPI_FMEM_USR_DDR_DQS_THD_R
  Field SPI_FMEM_USR_DDR_DQS_THD reader - The delay number of data strobe which from memory based on SPI clock.
• SPI_FMEM_VAR_DUMMY_R
  Field SPI_FMEM_VAR_DUMMY reader - Set the bit to enable variable dummy cycle in spi DDR mode.