Struct esp32h2::spi1::spi_mem_cache_fctrl::R

pub struct R(_);

Register SPI_MEM_CACHE_FCTRL reader

Implementations

impl R

pub fn spi_mem_cache_usr_addr_4byte(&self) -> SPI_MEM_CACHE_USR_ADDR_4BYTE_R

Bit 1 - For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.

pub fn spi_mem_fdin_dual(&self) -> SPI_MEM_FDIN_DUAL_R

Bit 3 - For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

pub fn spi_mem_fdout_dual(&self) -> SPI_MEM_FDOUT_DUAL_R

Bit 4 - For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

pub fn spi_mem_faddr_dual(&self) -> SPI_MEM_FADDR_DUAL_R

Bit 5 - For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.

pub fn spi_mem_fdin_quad(&self) -> SPI_MEM_FDIN_QUAD_R

Bit 6 - For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

pub fn spi_mem_fdout_quad(&self) -> SPI_MEM_FDOUT_QUAD_R

Bit 7 - For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

pub fn spi_mem_faddr_quad(&self) -> SPI_MEM_FADDR_QUAD_R

Bit 8 - For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.

Methods from Deref<Target = R<SPI_MEM_CACHE_FCTRL_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<SPI_MEM_CACHE_FCTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<SPI_MEM_CACHE_FCTRL_SPEC>> for R

fn from(reader: R<SPI_MEM_CACHE_FCTRL_SPEC>) -> Self

Converts to this type from the input type.