Struct esp32h2::spi0::spi_mem_din_num::R
source · pub struct R(_);
Expand description
Register SPI_MEM_DIN_NUM
reader
Implementations§
source§impl R
impl R
sourcepub fn spi_mem_din0_num(&self) -> SPI_MEM_DIN0_NUM_R
pub fn spi_mem_din0_num(&self) -> SPI_MEM_DIN0_NUM_R
Bits 0:1 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_din1_num(&self) -> SPI_MEM_DIN1_NUM_R
pub fn spi_mem_din1_num(&self) -> SPI_MEM_DIN1_NUM_R
Bits 2:3 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_din2_num(&self) -> SPI_MEM_DIN2_NUM_R
pub fn spi_mem_din2_num(&self) -> SPI_MEM_DIN2_NUM_R
Bits 4:5 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_din3_num(&self) -> SPI_MEM_DIN3_NUM_R
pub fn spi_mem_din3_num(&self) -> SPI_MEM_DIN3_NUM_R
Bits 6:7 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_din4_num(&self) -> SPI_MEM_DIN4_NUM_R
pub fn spi_mem_din4_num(&self) -> SPI_MEM_DIN4_NUM_R
Bits 8:9 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_din5_num(&self) -> SPI_MEM_DIN5_NUM_R
pub fn spi_mem_din5_num(&self) -> SPI_MEM_DIN5_NUM_R
Bits 10:11 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_din6_num(&self) -> SPI_MEM_DIN6_NUM_R
pub fn spi_mem_din6_num(&self) -> SPI_MEM_DIN6_NUM_R
Bits 12:13 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_din7_num(&self) -> SPI_MEM_DIN7_NUM_R
pub fn spi_mem_din7_num(&self) -> SPI_MEM_DIN7_NUM_R
Bits 14:15 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…
sourcepub fn spi_mem_dins_num(&self) -> SPI_MEM_DINS_NUM_R
pub fn spi_mem_dins_num(&self) -> SPI_MEM_DINS_NUM_R
Bits 16:17 - the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,…