pub struct TIMG1 { /* private fields */ }
Implementations§
Source§impl TIMG1
impl TIMG1
Sourcepub const PTR: *const <TIMG1 as Deref>::Target = {0x6000a000 as *const <esp32h2::TIMG1 as core::ops::Deref>::Target}
pub const PTR: *const <TIMG1 as Deref>::Target = {0x6000a000 as *const <esp32h2::TIMG1 as core::ops::Deref>::Target}
Pointer to the register block
Methods from Deref<Target = RegisterBlock>§
Sourcepub fn t0config(&self) -> &Reg<T0CONFIG_SPEC>
pub fn t0config(&self) -> &Reg<T0CONFIG_SPEC>
0x00 - Timer %s configuration register
Sourcepub fn t0update(&self) -> &Reg<T0UPDATE_SPEC>
pub fn t0update(&self) -> &Reg<T0UPDATE_SPEC>
0x0c - Write to copy current timer value to TIMGn_T%s_(LO/HI)_REG
Sourcepub fn t0alarmlo(&self) -> &Reg<T0ALARMLO_SPEC>
pub fn t0alarmlo(&self) -> &Reg<T0ALARMLO_SPEC>
0x10 - Timer %s alarm value, low 32 bits
Sourcepub fn t0alarmhi(&self) -> &Reg<T0ALARMHI_SPEC>
pub fn t0alarmhi(&self) -> &Reg<T0ALARMHI_SPEC>
0x14 - Timer %s alarm value, high bits
Sourcepub fn t0loadlo(&self) -> &Reg<T0LOADLO_SPEC>
pub fn t0loadlo(&self) -> &Reg<T0LOADLO_SPEC>
0x18 - Timer %s reload value, low 32 bits
Sourcepub fn t0loadhi(&self) -> &Reg<T0LOADHI_SPEC>
pub fn t0loadhi(&self) -> &Reg<T0LOADHI_SPEC>
0x1c - Timer %s reload value, high 22 bits
Sourcepub fn t0load(&self) -> &Reg<T0LOAD_SPEC>
pub fn t0load(&self) -> &Reg<T0LOAD_SPEC>
0x20 - Write to reload timer from TIMG_T%s_(LOADLOLOADHI)_REG
Sourcepub fn wdtconfig0(&self) -> &Reg<WDTCONFIG0_SPEC>
pub fn wdtconfig0(&self) -> &Reg<WDTCONFIG0_SPEC>
0x48 - Watchdog timer configuration register
Sourcepub fn wdtconfig1(&self) -> &Reg<WDTCONFIG1_SPEC>
pub fn wdtconfig1(&self) -> &Reg<WDTCONFIG1_SPEC>
0x4c - Watchdog timer prescaler register
Sourcepub fn wdtconfig2(&self) -> &Reg<WDTCONFIG2_SPEC>
pub fn wdtconfig2(&self) -> &Reg<WDTCONFIG2_SPEC>
0x50 - Watchdog timer stage 0 timeout value
Sourcepub fn wdtconfig3(&self) -> &Reg<WDTCONFIG3_SPEC>
pub fn wdtconfig3(&self) -> &Reg<WDTCONFIG3_SPEC>
0x54 - Watchdog timer stage 1 timeout value
Sourcepub fn wdtconfig4(&self) -> &Reg<WDTCONFIG4_SPEC>
pub fn wdtconfig4(&self) -> &Reg<WDTCONFIG4_SPEC>
0x58 - Watchdog timer stage 2 timeout value
Sourcepub fn wdtconfig5(&self) -> &Reg<WDTCONFIG5_SPEC>
pub fn wdtconfig5(&self) -> &Reg<WDTCONFIG5_SPEC>
0x5c - Watchdog timer stage 3 timeout value
Sourcepub fn wdtfeed(&self) -> &Reg<WDTFEED_SPEC>
pub fn wdtfeed(&self) -> &Reg<WDTFEED_SPEC>
0x60 - Write to feed the watchdog timer
Sourcepub fn wdtwprotect(&self) -> &Reg<WDTWPROTECT_SPEC>
pub fn wdtwprotect(&self) -> &Reg<WDTWPROTECT_SPEC>
0x64 - Watchdog write protect register
Sourcepub fn rtccalicfg(&self) -> &Reg<RTCCALICFG_SPEC>
pub fn rtccalicfg(&self) -> &Reg<RTCCALICFG_SPEC>
0x68 - RTC calibration configure register
Sourcepub fn rtccalicfg1(&self) -> &Reg<RTCCALICFG1_SPEC>
pub fn rtccalicfg1(&self) -> &Reg<RTCCALICFG1_SPEC>
0x6c - RTC calibration configure1 register
Sourcepub fn int_ena_timers(&self) -> &Reg<INT_ENA_TIMERS_SPEC>
pub fn int_ena_timers(&self) -> &Reg<INT_ENA_TIMERS_SPEC>
0x70 - Interrupt enable bits
Sourcepub fn int_raw_timers(&self) -> &Reg<INT_RAW_TIMERS_SPEC>
pub fn int_raw_timers(&self) -> &Reg<INT_RAW_TIMERS_SPEC>
0x74 - Raw interrupt status
Sourcepub fn int_st_timers(&self) -> &Reg<INT_ST_TIMERS_SPEC>
pub fn int_st_timers(&self) -> &Reg<INT_ST_TIMERS_SPEC>
0x78 - Masked interrupt status
Sourcepub fn int_clr_timers(&self) -> &Reg<INT_CLR_TIMERS_SPEC>
pub fn int_clr_timers(&self) -> &Reg<INT_CLR_TIMERS_SPEC>
0x7c - Interrupt clear bits
Sourcepub fn rtccalicfg2(&self) -> &Reg<RTCCALICFG2_SPEC>
pub fn rtccalicfg2(&self) -> &Reg<RTCCALICFG2_SPEC>
0x80 - Timer group calibration register
Sourcepub fn ntimers_date(&self) -> &Reg<NTIMERS_DATE_SPEC>
pub fn ntimers_date(&self) -> &Reg<NTIMERS_DATE_SPEC>
0xf8 - Timer version control register
Sourcepub fn regclk(&self) -> &Reg<REGCLK_SPEC>
pub fn regclk(&self) -> &Reg<REGCLK_SPEC>
0xfc - Timer group clock gate register