Type Alias W

pub type W = W<INT_ENA_SPEC>;

Register INT_ENA writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn ch_tx_end(&mut self, n: u8) -> CH_TX_END_W<'_, INT_ENA_SPEC>

The interrupt enable bit for CH(0-1)_TX_END_INT.

`n` is number of field in register. `n == 0` corresponds to `CH0_TX_END` field.

pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<'_, INT_ENA_SPEC>

Bit 0 - The interrupt enable bit for CH0_TX_END_INT.

pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<'_, INT_ENA_SPEC>

Bit 1 - The interrupt enable bit for CH1_TX_END_INT.

pub fn ch_rx_end(&mut self, n: u8) -> CH_RX_END_W<'_, INT_ENA_SPEC>

The interrupt enable bit for CH2_RX_END_INT.

`n` is number of field in register. `n == 0` corresponds to `CH2_RX_END` field.

pub fn ch2_rx_end(&mut self) -> CH_RX_END_W<'_, INT_ENA_SPEC>

Bit 2 - The interrupt enable bit for CH2_RX_END_INT.

pub fn ch3_rx_end(&mut self) -> CH_RX_END_W<'_, INT_ENA_SPEC>

Bit 3 - The interrupt enable bit for CH2_RX_END_INT.

pub fn ch_tx_err(&mut self, n: u8) -> CH_TX_ERR_W<'_, INT_ENA_SPEC>

The interrupt enable bit for CH4_ERR_INT.

`n` is number of field in register. `n == 0` corresponds to `CH0_TX_ERR` field.

pub fn ch0_tx_err(&mut self) -> CH_TX_ERR_W<'_, INT_ENA_SPEC>

Bit 4 - The interrupt enable bit for CH4_ERR_INT.

pub fn ch1_tx_err(&mut self) -> CH_TX_ERR_W<'_, INT_ENA_SPEC>

Bit 5 - The interrupt enable bit for CH4_ERR_INT.

pub fn ch_rx_err(&mut self, n: u8) -> CH_RX_ERR_W<'_, INT_ENA_SPEC>

The interrupt enable bit for CH6_ERR_INT.

`n` is number of field in register. `n == 0` corresponds to `CH2_RX_ERR` field.

pub fn ch2_rx_err(&mut self) -> CH_RX_ERR_W<'_, INT_ENA_SPEC>

Bit 6 - The interrupt enable bit for CH6_ERR_INT.

pub fn ch3_rx_err(&mut self) -> CH_RX_ERR_W<'_, INT_ENA_SPEC>

Bit 7 - The interrupt enable bit for CH6_ERR_INT.

pub fn ch_tx_thr_event(&mut self, n: u8) -> CH_TX_THR_EVENT_W<'_, INT_ENA_SPEC>

The interrupt enable bit for CH(0-1)_TX_THR_EVENT_INT.

`n` is number of field in register. `n == 0` corresponds to `CH0_TX_THR_EVENT` field.

pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<'_, INT_ENA_SPEC>

Bit 8 - The interrupt enable bit for CH0_TX_THR_EVENT_INT.

pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<'_, INT_ENA_SPEC>

Bit 9 - The interrupt enable bit for CH1_TX_THR_EVENT_INT.

pub fn ch_rx_thr_event(&mut self, n: u8) -> CH_RX_THR_EVENT_W<'_, INT_ENA_SPEC>

The interrupt enable bit for CH2_RX_THR_EVENT_INT.

`n` is number of field in register. `n == 0` corresponds to `CH2_RX_THR_EVENT` field.

pub fn ch2_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<'_, INT_ENA_SPEC>

Bit 10 - The interrupt enable bit for CH2_RX_THR_EVENT_INT.

pub fn ch3_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<'_, INT_ENA_SPEC>

Bit 11 - The interrupt enable bit for CH2_RX_THR_EVENT_INT.

pub fn ch_x_loop(&mut self, n: u8) -> CH_X_LOOP_W<'_, INT_ENA_SPEC>

The interrupt enable bit for CH(0-1)_TX_LOOP_INT.

`n` is number of field in register. `n == 0` corresponds to `CH0_X_LOOP` field.

pub fn ch0_x_loop(&mut self) -> CH_X_LOOP_W<'_, INT_ENA_SPEC>

Bit 12 - The interrupt enable bit for CH0_TX_LOOP_INT.

pub fn ch1_x_loop(&mut self) -> CH_X_LOOP_W<'_, INT_ENA_SPEC>

Bit 13 - The interrupt enable bit for CH1_TX_LOOP_INT.