pub type R = R<FLASH_WAITI_CTRL_SPEC>;
Expand description
Register FLASH_WAITI_CTRL
reader
Aliased Type§
struct R { /* private fields */ }
Implementations§
Source§impl R
impl R
Sourcepub fn waiti_en(&self) -> WAITI_EN_R
pub fn waiti_en(&self) -> WAITI_EN_R
Bit 0 - 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported.
Sourcepub fn waiti_dummy(&self) -> WAITI_DUMMY_R
pub fn waiti_dummy(&self) -> WAITI_DUMMY_R
Bit 1 - The dummy phase enable when wait flash idle (RDSR)
Sourcepub fn waiti_addr_en(&self) -> WAITI_ADDR_EN_R
pub fn waiti_addr_en(&self) -> WAITI_ADDR_EN_R
Bit 2 - 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer.
Sourcepub fn waiti_addr_cyclelen(&self) -> WAITI_ADDR_CYCLELEN_R
pub fn waiti_addr_cyclelen(&self) -> WAITI_ADDR_CYCLELEN_R
Bits 3:4 - When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN[1:0] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared.
Sourcepub fn waiti_cmd_2b(&self) -> WAITI_CMD_2B_R
pub fn waiti_cmd_2b(&self) -> WAITI_CMD_2B_R
Bit 9 - 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8.
Sourcepub fn waiti_dummy_cyclelen(&self) -> WAITI_DUMMY_CYCLELEN_R
pub fn waiti_dummy_cyclelen(&self) -> WAITI_DUMMY_CYCLELEN_R
Bits 10:15 - The dummy cycle length when wait flash idle(RDSR).
Sourcepub fn waiti_cmd(&self) -> WAITI_CMD_R
pub fn waiti_cmd(&self) -> WAITI_CMD_R
Bits 16:31 - The command value to wait flash idle(RDSR).