List of all items

Structs

• AES
• APB_SARADC
• ASSIST_DEBUG
• ATOMIC
• CLINT
• DMA
• DS
• ECC
• EFUSE
• EXTMEM
• GPIO
• GPIO_SD
• HINF
• HMAC
• HP_APM
• HP_SYS
• I2C0
• I2C_ANA_MST
• I2S0
• IEEE802154
• INTERRUPT_CORE0
• INTPRI
• IO_MUX
• LEDC
• LP_ANA
• LP_AON
• LP_APM
• LP_APM0
• LP_CLKRST
• LP_I2C0
• LP_I2C_ANA_MST
• LP_IO
• LP_PERI
• LP_TEE
• LP_TIMER
• LP_UART
• LP_WDT
• MCPWM0
• MEM_MONITOR
• MODEM_LPCON
• MODEM_SYSCON
• OTP_DEBUG
• PARL_IO
• PAU
• PCNT
• PCR
• PLIC_MX
• PLIC_UX
• PMU
• Peripherals
• RMT
• RNG
• RSA
• SHA
• SLC
• SLCHOST
• SOC_ETM
• SPI0
• SPI1
• SPI2
• SYSTIMER
• TEE
• TIMG0
• TIMG1
• TRACE
• TWAI0
• TWAI1
• UART0
• UART1
• UHCI0
• USB_DEVICE
• aes::RegisterBlock
• aes::aad_block_num::AAD_BLOCK_NUM_SPEC
• aes::block_mode::BLOCK_MODE_SPEC
• aes::block_num::BLOCK_NUM_SPEC
• aes::continue_::CONTINUE_SPEC
• aes::date::DATE_SPEC
• aes::dma_enable::DMA_ENABLE_SPEC
• aes::dma_exit::DMA_EXIT_SPEC
• aes::endian::ENDIAN_SPEC
• aes::h_mem::H_MEM_SPEC
• aes::inc_sel::INC_SEL_SPEC
• aes::int_clr::INT_CLR_SPEC
• aes::int_ena::INT_ENA_SPEC
• aes::iv_mem::IV_MEM_SPEC
• aes::j0_mem::J0_MEM_SPEC
• aes::key::KEY_SPEC
• aes::mode::MODE_SPEC
• aes::remainder_bit_num::REMAINDER_BIT_NUM_SPEC
• aes::state::STATE_SPEC
• aes::t0_mem::T0_MEM_SPEC
• aes::text_in::TEXT_IN_SPEC
• aes::text_out::TEXT_OUT_SPEC
• aes::trigger::TRIGGER_SPEC
• apb_saradc::RegisterBlock
• apb_saradc::arb_ctrl::ARB_CTRL_SPEC
• apb_saradc::cali::CALI_SPEC
• apb_saradc::clkm_conf::CLKM_CONF_SPEC
• apb_saradc::ctrl2::CTRL2_SPEC
• apb_saradc::ctrl::CTRL_SPEC
• apb_saradc::ctrl_date::CTRL_DATE_SPEC
• apb_saradc::dma_conf::DMA_CONF_SPEC
• apb_saradc::filter_ctrl0::FILTER_CTRL0_SPEC
• apb_saradc::filter_ctrl1::FILTER_CTRL1_SPEC
• apb_saradc::fsm_wait::FSM_WAIT_SPEC
• apb_saradc::int_clr::INT_CLR_SPEC
• apb_saradc::int_ena::INT_ENA_SPEC
• apb_saradc::int_raw::INT_RAW_SPEC
• apb_saradc::int_st::INT_ST_SPEC
• apb_saradc::onetime_sample::ONETIME_SAMPLE_SPEC
• apb_saradc::sar1_status::SAR1_STATUS_SPEC
• apb_saradc::sar1data_status::SAR1DATA_STATUS_SPEC
• apb_saradc::sar2_status::SAR2_STATUS_SPEC
• apb_saradc::sar2data_status::SAR2DATA_STATUS_SPEC
• apb_saradc::sar_patt_tab1::SAR_PATT_TAB1_SPEC
• apb_saradc::sar_patt_tab2::SAR_PATT_TAB2_SPEC
• apb_saradc::thres0_ctrl::THRES0_CTRL_SPEC
• apb_saradc::thres1_ctrl::THRES1_CTRL_SPEC
• apb_saradc::thres_ctrl::THRES_CTRL_SPEC
• apb_saradc::tsens_ctrl2::TSENS_CTRL2_SPEC
• apb_saradc::tsens_ctrl::TSENS_CTRL_SPEC
• apb_saradc::tsens_sample::TSENS_SAMPLE_SPEC
• apb_saradc::tsens_wake::TSENS_WAKE_SPEC
• assist_debug::RegisterBlock
• assist_debug::clock_gate::CLOCK_GATE_SPEC
• assist_debug::core_0_area_dram0_0_max::CORE_0_AREA_DRAM0_0_MAX_SPEC
• assist_debug::core_0_area_dram0_0_min::CORE_0_AREA_DRAM0_0_MIN_SPEC
• assist_debug::core_0_area_dram0_1_max::CORE_0_AREA_DRAM0_1_MAX_SPEC
• assist_debug::core_0_area_dram0_1_min::CORE_0_AREA_DRAM0_1_MIN_SPEC
• assist_debug::core_0_area_pc::CORE_0_AREA_PC_SPEC
• assist_debug::core_0_area_pif_0_max::CORE_0_AREA_PIF_0_MAX_SPEC
• assist_debug::core_0_area_pif_0_min::CORE_0_AREA_PIF_0_MIN_SPEC
• assist_debug::core_0_area_pif_1_max::CORE_0_AREA_PIF_1_MAX_SPEC
• assist_debug::core_0_area_pif_1_min::CORE_0_AREA_PIF_1_MIN_SPEC
• assist_debug::core_0_area_sp::CORE_0_AREA_SP_SPEC
• assist_debug::core_0_debug_mode::CORE_0_DEBUG_MODE_SPEC
• assist_debug::core_0_dram0_exception_monitor_0::CORE_0_DRAM0_EXCEPTION_MONITOR_0_SPEC
• assist_debug::core_0_dram0_exception_monitor_1::CORE_0_DRAM0_EXCEPTION_MONITOR_1_SPEC
• assist_debug::core_0_dram0_exception_monitor_2::CORE_0_DRAM0_EXCEPTION_MONITOR_2_SPEC
• assist_debug::core_0_dram0_exception_monitor_3::CORE_0_DRAM0_EXCEPTION_MONITOR_3_SPEC
• assist_debug::core_0_intr_clr::CORE_0_INTR_CLR_SPEC
• assist_debug::core_0_intr_ena::CORE_0_INTR_ENA_SPEC
• assist_debug::core_0_intr_raw::CORE_0_INTR_RAW_SPEC
• assist_debug::core_0_iram0_exception_monitor_0::CORE_0_IRAM0_EXCEPTION_MONITOR_0_SPEC
• assist_debug::core_0_iram0_exception_monitor_1::CORE_0_IRAM0_EXCEPTION_MONITOR_1_SPEC
• assist_debug::core_0_lastpc_before_exception::CORE_0_LASTPC_BEFORE_EXCEPTION_SPEC
• assist_debug::core_0_montr_ena::CORE_0_MONTR_ENA_SPEC
• assist_debug::core_0_rcd_en::CORE_0_RCD_EN_SPEC
• assist_debug::core_0_rcd_pdebugpc::CORE_0_RCD_PDEBUGPC_SPEC
• assist_debug::core_0_rcd_pdebugsp::CORE_0_RCD_PDEBUGSP_SPEC
• assist_debug::core_0_sp_max::CORE_0_SP_MAX_SPEC
• assist_debug::core_0_sp_min::CORE_0_SP_MIN_SPEC
• assist_debug::core_0_sp_pc::CORE_0_SP_PC_SPEC
• assist_debug::core_x_iram0_dram0_exception_monitor_0::CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_SPEC
• assist_debug::core_x_iram0_dram0_exception_monitor_1::CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_SPEC
• assist_debug::date::DATE_SPEC
• atomic::RegisterBlock
• atomic::addr_lock::ADDR_LOCK_SPEC
• atomic::counter::COUNTER_SPEC
• atomic::lock_status::LOCK_STATUS_SPEC
• atomic::lr_addr::LR_ADDR_SPEC
• atomic::lr_value::LR_VALUE_SPEC
• clint::RegisterBlock
• clint::msip::MSIP_SPEC
• clint::mtime::MTIME_SPEC
• clint::mtimecmp::MTIMECMP_SPEC
• clint::mtimectl::MTIMECTL_SPEC
• clint::usip::USIP_SPEC
• clint::utime::UTIME_SPEC
• clint::utimecmp::UTIMECMP_SPEC
• clint::utimectl::UTIMECTL_SPEC
• dma::RegisterBlock
• dma::ahb_test::AHB_TEST_SPEC
• dma::ch::CH
• dma::ch::in_conf0::IN_CONF0_SPEC
• dma::ch::in_conf1::IN_CONF1_SPEC
• dma::ch::in_dscr::IN_DSCR_SPEC
• dma::ch::in_dscr_bf0::IN_DSCR_BF0_SPEC
• dma::ch::in_dscr_bf1::IN_DSCR_BF1_SPEC
• dma::ch::in_err_eof_des_addr::IN_ERR_EOF_DES_ADDR_SPEC
• dma::ch::in_link::IN_LINK_SPEC
• dma::ch::in_peri_sel::IN_PERI_SEL_SPEC
• dma::ch::in_pop::IN_POP_SPEC
• dma::ch::in_pri::IN_PRI_SPEC
• dma::ch::in_state::IN_STATE_SPEC
• dma::ch::in_suc_eof_des_addr::IN_SUC_EOF_DES_ADDR_SPEC
• dma::ch::infifo_status::INFIFO_STATUS_SPEC
• dma::ch::out_conf0::OUT_CONF0_SPEC
• dma::ch::out_conf1::OUT_CONF1_SPEC
• dma::ch::out_dscr::OUT_DSCR_SPEC
• dma::ch::out_dscr_bf0::OUT_DSCR_BF0_SPEC
• dma::ch::out_dscr_bf1::OUT_DSCR_BF1_SPEC
• dma::ch::out_eof_bfr_des_addr::OUT_EOF_BFR_DES_ADDR_SPEC
• dma::ch::out_eof_des_addr::OUT_EOF_DES_ADDR_SPEC
• dma::ch::out_link::OUT_LINK_SPEC
• dma::ch::out_peri_sel::OUT_PERI_SEL_SPEC
• dma::ch::out_pri::OUT_PRI_SPEC
• dma::ch::out_push::OUT_PUSH_SPEC
• dma::ch::out_state::OUT_STATE_SPEC
• dma::ch::outfifo_status::OUTFIFO_STATUS_SPEC
• dma::date::DATE_SPEC
• dma::in_int_ch::IN_INT_CH
• dma::in_int_ch::clr::CLR_SPEC
• dma::in_int_ch::ena::ENA_SPEC
• dma::in_int_ch::raw::RAW_SPEC
• dma::in_int_ch::st::ST_SPEC
• dma::misc_conf::MISC_CONF_SPEC
• dma::out_int_ch::OUT_INT_CH
• dma::out_int_ch::clr::CLR_SPEC
• dma::out_int_ch::ena::ENA_SPEC
• dma::out_int_ch::raw::RAW_SPEC
• dma::out_int_ch::st::ST_SPEC
• ds::RegisterBlock
• ds::box_mem::BOX_MEM_SPEC
• ds::date::DATE_SPEC
• ds::iv_mem::IV_MEM_SPEC
• ds::m_mem::M_MEM_SPEC
• ds::query_busy::QUERY_BUSY_SPEC
• ds::query_check::QUERY_CHECK_SPEC
• ds::query_key_wrong::QUERY_KEY_WRONG_SPEC
• ds::rb_mem::RB_MEM_SPEC
• ds::set_continue::SET_CONTINUE_SPEC
• ds::set_finish::SET_FINISH_SPEC
• ds::set_start::SET_START_SPEC
• ds::x_mem::X_MEM_SPEC
• ds::y_mem::Y_MEM_SPEC
• ds::z_mem::Z_MEM_SPEC
• ecc::RegisterBlock
• ecc::k_mem::K_MEM_SPEC
• ecc::mult_conf::MULT_CONF_SPEC
• ecc::mult_date::MULT_DATE_SPEC
• ecc::mult_int_clr::MULT_INT_CLR_SPEC
• ecc::mult_int_ena::MULT_INT_ENA_SPEC
• ecc::mult_int_raw::MULT_INT_RAW_SPEC
• ecc::mult_int_st::MULT_INT_ST_SPEC
• ecc::px_mem::PX_MEM_SPEC
• ecc::py_mem::PY_MEM_SPEC
• efuse::RegisterBlock
• efuse::clk::CLK_SPEC
• efuse::cmd::CMD_SPEC
• efuse::conf::CONF_SPEC
• efuse::dac_conf::DAC_CONF_SPEC
• efuse::date::DATE_SPEC
• efuse::int_clr::INT_CLR_SPEC
• efuse::int_ena::INT_ENA_SPEC
• efuse::int_raw::INT_RAW_SPEC
• efuse::int_st::INT_ST_SPEC
• efuse::pgm_check_value0::PGM_CHECK_VALUE0_SPEC
• efuse::pgm_check_value1::PGM_CHECK_VALUE1_SPEC
• efuse::pgm_check_value2::PGM_CHECK_VALUE2_SPEC
• efuse::pgm_data0::PGM_DATA0_SPEC
• efuse::pgm_data1::PGM_DATA1_SPEC
• efuse::pgm_data2::PGM_DATA2_SPEC
• efuse::pgm_data3::PGM_DATA3_SPEC
• efuse::pgm_data4::PGM_DATA4_SPEC
• efuse::pgm_data5::PGM_DATA5_SPEC
• efuse::pgm_data6::PGM_DATA6_SPEC
• efuse::pgm_data7::PGM_DATA7_SPEC
• efuse::rd_key0_data0::RD_KEY0_DATA0_SPEC
• efuse::rd_key0_data1::RD_KEY0_DATA1_SPEC
• efuse::rd_key0_data2::RD_KEY0_DATA2_SPEC
• efuse::rd_key0_data3::RD_KEY0_DATA3_SPEC
• efuse::rd_key0_data4::RD_KEY0_DATA4_SPEC
• efuse::rd_key0_data5::RD_KEY0_DATA5_SPEC
• efuse::rd_key0_data6::RD_KEY0_DATA6_SPEC
• efuse::rd_key0_data7::RD_KEY0_DATA7_SPEC
• efuse::rd_key1_data0::RD_KEY1_DATA0_SPEC
• efuse::rd_key1_data1::RD_KEY1_DATA1_SPEC
• efuse::rd_key1_data2::RD_KEY1_DATA2_SPEC
• efuse::rd_key1_data3::RD_KEY1_DATA3_SPEC
• efuse::rd_key1_data4::RD_KEY1_DATA4_SPEC
• efuse::rd_key1_data5::RD_KEY1_DATA5_SPEC
• efuse::rd_key1_data6::RD_KEY1_DATA6_SPEC
• efuse::rd_key1_data7::RD_KEY1_DATA7_SPEC
• efuse::rd_key2_data0::RD_KEY2_DATA0_SPEC
• efuse::rd_key2_data1::RD_KEY2_DATA1_SPEC
• efuse::rd_key2_data2::RD_KEY2_DATA2_SPEC
• efuse::rd_key2_data3::RD_KEY2_DATA3_SPEC
• efuse::rd_key2_data4::RD_KEY2_DATA4_SPEC
• efuse::rd_key2_data5::RD_KEY2_DATA5_SPEC
• efuse::rd_key2_data6::RD_KEY2_DATA6_SPEC
• efuse::rd_key2_data7::RD_KEY2_DATA7_SPEC
• efuse::rd_key3_data0::RD_KEY3_DATA0_SPEC
• efuse::rd_key3_data1::RD_KEY3_DATA1_SPEC
• efuse::rd_key3_data2::RD_KEY3_DATA2_SPEC
• efuse::rd_key3_data3::RD_KEY3_DATA3_SPEC
• efuse::rd_key3_data4::RD_KEY3_DATA4_SPEC
• efuse::rd_key3_data5::RD_KEY3_DATA5_SPEC
• efuse::rd_key3_data6::RD_KEY3_DATA6_SPEC
• efuse::rd_key3_data7::RD_KEY3_DATA7_SPEC
• efuse::rd_key4_data0::RD_KEY4_DATA0_SPEC
• efuse::rd_key4_data1::RD_KEY4_DATA1_SPEC
• efuse::rd_key4_data2::RD_KEY4_DATA2_SPEC
• efuse::rd_key4_data3::RD_KEY4_DATA3_SPEC
• efuse::rd_key4_data4::RD_KEY4_DATA4_SPEC
• efuse::rd_key4_data5::RD_KEY4_DATA5_SPEC
• efuse::rd_key4_data6::RD_KEY4_DATA6_SPEC
• efuse::rd_key4_data7::RD_KEY4_DATA7_SPEC
• efuse::rd_key5_data0::RD_KEY5_DATA0_SPEC
• efuse::rd_key5_data1::RD_KEY5_DATA1_SPEC
• efuse::rd_key5_data2::RD_KEY5_DATA2_SPEC
• efuse::rd_key5_data3::RD_KEY5_DATA3_SPEC
• efuse::rd_key5_data4::RD_KEY5_DATA4_SPEC
• efuse::rd_key5_data5::RD_KEY5_DATA5_SPEC
• efuse::rd_key5_data6::RD_KEY5_DATA6_SPEC
• efuse::rd_key5_data7::RD_KEY5_DATA7_SPEC
• efuse::rd_mac_spi_sys_0::RD_MAC_SPI_SYS_0_SPEC
• efuse::rd_mac_spi_sys_1::RD_MAC_SPI_SYS_1_SPEC
• efuse::rd_mac_spi_sys_2::RD_MAC_SPI_SYS_2_SPEC
• efuse::rd_mac_spi_sys_3::RD_MAC_SPI_SYS_3_SPEC
• efuse::rd_mac_spi_sys_4::RD_MAC_SPI_SYS_4_SPEC
• efuse::rd_mac_spi_sys_5::RD_MAC_SPI_SYS_5_SPEC
• efuse::rd_repeat_data0::RD_REPEAT_DATA0_SPEC
• efuse::rd_repeat_data1::RD_REPEAT_DATA1_SPEC
• efuse::rd_repeat_data2::RD_REPEAT_DATA2_SPEC
• efuse::rd_repeat_data3::RD_REPEAT_DATA3_SPEC
• efuse::rd_repeat_data4::RD_REPEAT_DATA4_SPEC
• efuse::rd_repeat_err0::RD_REPEAT_ERR0_SPEC
• efuse::rd_repeat_err1::RD_REPEAT_ERR1_SPEC
• efuse::rd_repeat_err2::RD_REPEAT_ERR2_SPEC
• efuse::rd_repeat_err3::RD_REPEAT_ERR3_SPEC
• efuse::rd_repeat_err4::RD_REPEAT_ERR4_SPEC
• efuse::rd_rs_err0::RD_RS_ERR0_SPEC
• efuse::rd_rs_err1::RD_RS_ERR1_SPEC
• efuse::rd_sys_part1_data0::RD_SYS_PART1_DATA0_SPEC
• efuse::rd_sys_part1_data1::RD_SYS_PART1_DATA1_SPEC
• efuse::rd_sys_part1_data2::RD_SYS_PART1_DATA2_SPEC
• efuse::rd_sys_part1_data3::RD_SYS_PART1_DATA3_SPEC
• efuse::rd_sys_part1_data4::RD_SYS_PART1_DATA4_SPEC
• efuse::rd_sys_part1_data5::RD_SYS_PART1_DATA5_SPEC
• efuse::rd_sys_part1_data6::RD_SYS_PART1_DATA6_SPEC
• efuse::rd_sys_part1_data7::RD_SYS_PART1_DATA7_SPEC
• efuse::rd_sys_part2_data0::RD_SYS_PART2_DATA0_SPEC
• efuse::rd_sys_part2_data1::RD_SYS_PART2_DATA1_SPEC
• efuse::rd_sys_part2_data2::RD_SYS_PART2_DATA2_SPEC
• efuse::rd_sys_part2_data3::RD_SYS_PART2_DATA3_SPEC
• efuse::rd_sys_part2_data4::RD_SYS_PART2_DATA4_SPEC
• efuse::rd_sys_part2_data5::RD_SYS_PART2_DATA5_SPEC
• efuse::rd_sys_part2_data6::RD_SYS_PART2_DATA6_SPEC
• efuse::rd_sys_part2_data7::RD_SYS_PART2_DATA7_SPEC
• efuse::rd_tim_conf::RD_TIM_CONF_SPEC
• efuse::rd_usr_data0::RD_USR_DATA0_SPEC
• efuse::rd_usr_data1::RD_USR_DATA1_SPEC
• efuse::rd_usr_data2::RD_USR_DATA2_SPEC
• efuse::rd_usr_data3::RD_USR_DATA3_SPEC
• efuse::rd_usr_data4::RD_USR_DATA4_SPEC
• efuse::rd_usr_data5::RD_USR_DATA5_SPEC
• efuse::rd_usr_data6::RD_USR_DATA6_SPEC
• efuse::rd_usr_data7::RD_USR_DATA7_SPEC
• efuse::rd_wr_dis::RD_WR_DIS_SPEC
• efuse::status::STATUS_SPEC
• efuse::wr_tim_conf0_rs_bypass::WR_TIM_CONF0_RS_BYPASS_SPEC
• efuse::wr_tim_conf1::WR_TIM_CONF1_SPEC
• efuse::wr_tim_conf2::WR_TIM_CONF2_SPEC
• extmem::RegisterBlock
• extmem::cache_lock_addr::CACHE_LOCK_ADDR_SPEC
• extmem::cache_lock_ctrl::CACHE_LOCK_CTRL_SPEC
• extmem::cache_lock_map::CACHE_LOCK_MAP_SPEC
• extmem::cache_lock_size::CACHE_LOCK_SIZE_SPEC
• extmem::cache_sync_addr::CACHE_SYNC_ADDR_SPEC
• extmem::cache_sync_ctrl::CACHE_SYNC_CTRL_SPEC
• extmem::cache_sync_map::CACHE_SYNC_MAP_SPEC
• extmem::cache_sync_size::CACHE_SYNC_SIZE_SPEC
• extmem::clock_gate::CLOCK_GATE_SPEC
• extmem::date::DATE_SPEC
• extmem::l1_bus0_acs_conflict_cnt::L1_BUS0_ACS_CONFLICT_CNT_SPEC
• extmem::l1_bus0_acs_hit_cnt::L1_BUS0_ACS_HIT_CNT_SPEC
• extmem::l1_bus0_acs_miss_cnt::L1_BUS0_ACS_MISS_CNT_SPEC
• extmem::l1_bus0_acs_nxtlvl_cnt::L1_BUS0_ACS_NXTLVL_CNT_SPEC
• extmem::l1_bus1_acs_conflict_cnt::L1_BUS1_ACS_CONFLICT_CNT_SPEC
• extmem::l1_bus1_acs_hit_cnt::L1_BUS1_ACS_HIT_CNT_SPEC
• extmem::l1_bus1_acs_miss_cnt::L1_BUS1_ACS_MISS_CNT_SPEC
• extmem::l1_bus1_acs_nxtlvl_cnt::L1_BUS1_ACS_NXTLVL_CNT_SPEC
• extmem::l1_bypass_cache_conf::L1_BYPASS_CACHE_CONF_SPEC
• extmem::l1_cache_acs_cnt_ctrl::L1_CACHE_ACS_CNT_CTRL_SPEC
• extmem::l1_cache_acs_cnt_int_clr::L1_CACHE_ACS_CNT_INT_CLR_SPEC
• extmem::l1_cache_acs_cnt_int_ena::L1_CACHE_ACS_CNT_INT_ENA_SPEC
• extmem::l1_cache_acs_cnt_int_raw::L1_CACHE_ACS_CNT_INT_RAW_SPEC
• extmem::l1_cache_acs_cnt_int_st::L1_CACHE_ACS_CNT_INT_ST_SPEC
• extmem::l1_cache_acs_fail_id_attr::L1_CACHE_ACS_FAIL_ID_ATTR_SPEC
• extmem::l1_cache_acs_fail_int_clr::L1_CACHE_ACS_FAIL_INT_CLR_SPEC
• extmem::l1_cache_acs_fail_int_ena::L1_CACHE_ACS_FAIL_INT_ENA_SPEC
• extmem::l1_cache_acs_fail_int_raw::L1_CACHE_ACS_FAIL_INT_RAW_SPEC
• extmem::l1_cache_acs_fail_int_st::L1_CACHE_ACS_FAIL_INT_ST_SPEC
• extmem::l1_cache_atomic_conf::L1_CACHE_ATOMIC_CONF_SPEC
• extmem::l1_cache_autoload_buf_clr_ctrl::L1_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC
• extmem::l1_cache_autoload_ctrl::L1_CACHE_AUTOLOAD_CTRL_SPEC
• extmem::l1_cache_autoload_sct0_addr::L1_CACHE_AUTOLOAD_SCT0_ADDR_SPEC
• extmem::l1_cache_autoload_sct0_size::L1_CACHE_AUTOLOAD_SCT0_SIZE_SPEC
• extmem::l1_cache_autoload_sct1_addr::L1_CACHE_AUTOLOAD_SCT1_ADDR_SPEC
• extmem::l1_cache_autoload_sct1_size::L1_CACHE_AUTOLOAD_SCT1_SIZE_SPEC
• extmem::l1_cache_autoload_sct2_addr::L1_CACHE_AUTOLOAD_SCT2_ADDR_SPEC
• extmem::l1_cache_autoload_sct2_size::L1_CACHE_AUTOLOAD_SCT2_SIZE_SPEC
• extmem::l1_cache_autoload_sct3_addr::L1_CACHE_AUTOLOAD_SCT3_ADDR_SPEC
• extmem::l1_cache_autoload_sct3_size::L1_CACHE_AUTOLOAD_SCT3_SIZE_SPEC
• extmem::l1_cache_blocksize_conf::L1_CACHE_BLOCKSIZE_CONF_SPEC
• extmem::l1_cache_cachesize_conf::L1_CACHE_CACHESIZE_CONF_SPEC
• extmem::l1_cache_ctrl::L1_CACHE_CTRL_SPEC
• extmem::l1_cache_data_mem_acs_conf::L1_CACHE_DATA_MEM_ACS_CONF_SPEC
• extmem::l1_cache_data_mem_power_ctrl::L1_CACHE_DATA_MEM_POWER_CTRL_SPEC
• extmem::l1_cache_debug_bus::L1_CACHE_DEBUG_BUS_SPEC
• extmem::l1_cache_freeze_ctrl::L1_CACHE_FREEZE_CTRL_SPEC
• extmem::l1_cache_object_ctrl::L1_CACHE_OBJECT_CTRL_SPEC
• extmem::l1_cache_preload_ctrl::L1_CACHE_PRELOAD_CTRL_SPEC
• extmem::l1_cache_preload_rst_ctrl::L1_CACHE_PRELOAD_RST_CTRL_SPEC
• extmem::l1_cache_prelock_conf::L1_CACHE_PRELOCK_CONF_SPEC
• extmem::l1_cache_prelock_sct0_addr::L1_CACHE_PRELOCK_SCT0_ADDR_SPEC
• extmem::l1_cache_sync_preload_exception::L1_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC
• extmem::l1_cache_sync_preload_int_clr::L1_CACHE_SYNC_PRELOAD_INT_CLR_SPEC
• extmem::l1_cache_sync_preload_int_ena::L1_CACHE_SYNC_PRELOAD_INT_ENA_SPEC
• extmem::l1_cache_sync_preload_int_raw::L1_CACHE_SYNC_PRELOAD_INT_RAW_SPEC
• extmem::l1_cache_sync_preload_int_st::L1_CACHE_SYNC_PRELOAD_INT_ST_SPEC
• extmem::l1_cache_sync_rst_ctrl::L1_CACHE_SYNC_RST_CTRL_SPEC
• extmem::l1_cache_tag_mem_acs_conf::L1_CACHE_TAG_MEM_ACS_CONF_SPEC
• extmem::l1_cache_tag_mem_power_ctrl::L1_CACHE_TAG_MEM_POWER_CTRL_SPEC
• extmem::l1_cache_vaddr::L1_CACHE_VADDR_SPEC
• extmem::l1_cache_way_object::L1_CACHE_WAY_OBJECT_SPEC
• extmem::l1_cache_wrap_around_ctrl::L1_CACHE_WRAP_AROUND_CTRL_SPEC
• extmem::l1_dbus2_acs_conflict_cnt::L1_DBUS2_ACS_CONFLICT_CNT_SPEC
• extmem::l1_dbus2_acs_hit_cnt::L1_DBUS2_ACS_HIT_CNT_SPEC
• extmem::l1_dbus2_acs_miss_cnt::L1_DBUS2_ACS_MISS_CNT_SPEC
• extmem::l1_dbus2_acs_nxtlvl_cnt::L1_DBUS2_ACS_NXTLVL_CNT_SPEC
• extmem::l1_dbus3_acs_conflict_cnt::L1_DBUS3_ACS_CONFLICT_CNT_SPEC
• extmem::l1_dbus3_acs_hit_cnt::L1_DBUS3_ACS_HIT_CNT_SPEC
• extmem::l1_dbus3_acs_miss_cnt::L1_DBUS3_ACS_MISS_CNT_SPEC
• extmem::l1_dbus3_acs_nxtlvl_cnt::L1_DBUS3_ACS_NXTLVL_CNT_SPEC
• extmem::l1_dcache_acs_fail_addr::L1_DCACHE_ACS_FAIL_ADDR_SPEC
• extmem::l1_dcache_preload_addr::L1_DCACHE_PRELOAD_ADDR_SPEC
• extmem::l1_dcache_preload_size::L1_DCACHE_PRELOAD_SIZE_SPEC
• extmem::l1_dcache_prelock_sct1_addr::L1_DCACHE_PRELOCK_SCT1_ADDR_SPEC
• extmem::l1_dcache_prelock_sct_size::L1_DCACHE_PRELOCK_SCT_SIZE_SPEC
• extmem::l1_ibus0_acs_conflict_cnt::L1_IBUS0_ACS_CONFLICT_CNT_SPEC
• extmem::l1_ibus0_acs_hit_cnt::L1_IBUS0_ACS_HIT_CNT_SPEC
• extmem::l1_ibus0_acs_miss_cnt::L1_IBUS0_ACS_MISS_CNT_SPEC
• extmem::l1_ibus0_acs_nxtlvl_cnt::L1_IBUS0_ACS_NXTLVL_CNT_SPEC
• extmem::l1_ibus1_acs_conflict_cnt::L1_IBUS1_ACS_CONFLICT_CNT_SPEC
• extmem::l1_ibus1_acs_hit_cnt::L1_IBUS1_ACS_HIT_CNT_SPEC
• extmem::l1_ibus1_acs_miss_cnt::L1_IBUS1_ACS_MISS_CNT_SPEC
• extmem::l1_ibus1_acs_nxtlvl_cnt::L1_IBUS1_ACS_NXTLVL_CNT_SPEC
• extmem::l1_ibus2_acs_conflict_cnt::L1_IBUS2_ACS_CONFLICT_CNT_SPEC
• extmem::l1_ibus2_acs_hit_cnt::L1_IBUS2_ACS_HIT_CNT_SPEC
• extmem::l1_ibus2_acs_miss_cnt::L1_IBUS2_ACS_MISS_CNT_SPEC
• extmem::l1_ibus2_acs_nxtlvl_cnt::L1_IBUS2_ACS_NXTLVL_CNT_SPEC
• extmem::l1_ibus3_acs_conflict_cnt::L1_IBUS3_ACS_CONFLICT_CNT_SPEC
• extmem::l1_ibus3_acs_hit_cnt::L1_IBUS3_ACS_HIT_CNT_SPEC
• extmem::l1_ibus3_acs_miss_cnt::L1_IBUS3_ACS_MISS_CNT_SPEC
• extmem::l1_ibus3_acs_nxtlvl_cnt::L1_IBUS3_ACS_NXTLVL_CNT_SPEC
• extmem::l1_icache0_acs_fail_addr::L1_ICACHE0_ACS_FAIL_ADDR_SPEC
• extmem::l1_icache0_acs_fail_id_attr::L1_ICACHE0_ACS_FAIL_ID_ATTR_SPEC
• extmem::l1_icache0_autoload_ctrl::L1_ICACHE0_AUTOLOAD_CTRL_SPEC
• extmem::l1_icache0_autoload_sct0_addr::L1_ICACHE0_AUTOLOAD_SCT0_ADDR_SPEC
• extmem::l1_icache0_autoload_sct0_size::L1_ICACHE0_AUTOLOAD_SCT0_SIZE_SPEC
• extmem::l1_icache0_autoload_sct1_addr::L1_ICACHE0_AUTOLOAD_SCT1_ADDR_SPEC
• extmem::l1_icache0_autoload_sct1_size::L1_ICACHE0_AUTOLOAD_SCT1_SIZE_SPEC
• extmem::l1_icache0_preload_addr::L1_ICACHE0_PRELOAD_ADDR_SPEC
• extmem::l1_icache0_preload_ctrl::L1_ICACHE0_PRELOAD_CTRL_SPEC
• extmem::l1_icache0_preload_size::L1_ICACHE0_PRELOAD_SIZE_SPEC
• extmem::l1_icache0_prelock_conf::L1_ICACHE0_PRELOCK_CONF_SPEC
• extmem::l1_icache0_prelock_sct0_addr::L1_ICACHE0_PRELOCK_SCT0_ADDR_SPEC
• extmem::l1_icache0_prelock_sct1_addr::L1_ICACHE0_PRELOCK_SCT1_ADDR_SPEC
• extmem::l1_icache0_prelock_sct_size::L1_ICACHE0_PRELOCK_SCT_SIZE_SPEC
• extmem::l1_icache1_acs_fail_addr::L1_ICACHE1_ACS_FAIL_ADDR_SPEC
• extmem::l1_icache1_acs_fail_id_attr::L1_ICACHE1_ACS_FAIL_ID_ATTR_SPEC
• extmem::l1_icache1_autoload_ctrl::L1_ICACHE1_AUTOLOAD_CTRL_SPEC
• extmem::l1_icache1_autoload_sct0_addr::L1_ICACHE1_AUTOLOAD_SCT0_ADDR_SPEC
• extmem::l1_icache1_autoload_sct0_size::L1_ICACHE1_AUTOLOAD_SCT0_SIZE_SPEC
• extmem::l1_icache1_autoload_sct1_addr::L1_ICACHE1_AUTOLOAD_SCT1_ADDR_SPEC
• extmem::l1_icache1_autoload_sct1_size::L1_ICACHE1_AUTOLOAD_SCT1_SIZE_SPEC
• extmem::l1_icache1_preload_addr::L1_ICACHE1_PRELOAD_ADDR_SPEC
• extmem::l1_icache1_preload_ctrl::L1_ICACHE1_PRELOAD_CTRL_SPEC
• extmem::l1_icache1_preload_size::L1_ICACHE1_PRELOAD_SIZE_SPEC
• extmem::l1_icache1_prelock_conf::L1_ICACHE1_PRELOCK_CONF_SPEC
• extmem::l1_icache1_prelock_sct0_addr::L1_ICACHE1_PRELOCK_SCT0_ADDR_SPEC
• extmem::l1_icache1_prelock_sct1_addr::L1_ICACHE1_PRELOCK_SCT1_ADDR_SPEC
• extmem::l1_icache1_prelock_sct_size::L1_ICACHE1_PRELOCK_SCT_SIZE_SPEC
• extmem::l1_icache2_acs_fail_addr::L1_ICACHE2_ACS_FAIL_ADDR_SPEC
• extmem::l1_icache2_acs_fail_id_attr::L1_ICACHE2_ACS_FAIL_ID_ATTR_SPEC
• extmem::l1_icache2_autoload_ctrl::L1_ICACHE2_AUTOLOAD_CTRL_SPEC
• extmem::l1_icache2_autoload_sct0_addr::L1_ICACHE2_AUTOLOAD_SCT0_ADDR_SPEC
• extmem::l1_icache2_autoload_sct0_size::L1_ICACHE2_AUTOLOAD_SCT0_SIZE_SPEC
• extmem::l1_icache2_autoload_sct1_addr::L1_ICACHE2_AUTOLOAD_SCT1_ADDR_SPEC
• extmem::l1_icache2_autoload_sct1_size::L1_ICACHE2_AUTOLOAD_SCT1_SIZE_SPEC
• extmem::l1_icache2_preload_addr::L1_ICACHE2_PRELOAD_ADDR_SPEC
• extmem::l1_icache2_preload_ctrl::L1_ICACHE2_PRELOAD_CTRL_SPEC
• extmem::l1_icache2_preload_size::L1_ICACHE2_PRELOAD_SIZE_SPEC
• extmem::l1_icache2_prelock_conf::L1_ICACHE2_PRELOCK_CONF_SPEC
• extmem::l1_icache2_prelock_sct0_addr::L1_ICACHE2_PRELOCK_SCT0_ADDR_SPEC
• extmem::l1_icache2_prelock_sct1_addr::L1_ICACHE2_PRELOCK_SCT1_ADDR_SPEC
• extmem::l1_icache2_prelock_sct_size::L1_ICACHE2_PRELOCK_SCT_SIZE_SPEC
• extmem::l1_icache3_acs_fail_addr::L1_ICACHE3_ACS_FAIL_ADDR_SPEC
• extmem::l1_icache3_acs_fail_id_attr::L1_ICACHE3_ACS_FAIL_ID_ATTR_SPEC
• extmem::l1_icache3_autoload_ctrl::L1_ICACHE3_AUTOLOAD_CTRL_SPEC
• extmem::l1_icache3_autoload_sct0_addr::L1_ICACHE3_AUTOLOAD_SCT0_ADDR_SPEC
• extmem::l1_icache3_autoload_sct0_size::L1_ICACHE3_AUTOLOAD_SCT0_SIZE_SPEC
• extmem::l1_icache3_autoload_sct1_addr::L1_ICACHE3_AUTOLOAD_SCT1_ADDR_SPEC
• extmem::l1_icache3_autoload_sct1_size::L1_ICACHE3_AUTOLOAD_SCT1_SIZE_SPEC
• extmem::l1_icache3_preload_addr::L1_ICACHE3_PRELOAD_ADDR_SPEC
• extmem::l1_icache3_preload_ctrl::L1_ICACHE3_PRELOAD_CTRL_SPEC
• extmem::l1_icache3_preload_size::L1_ICACHE3_PRELOAD_SIZE_SPEC
• extmem::l1_icache3_prelock_conf::L1_ICACHE3_PRELOCK_CONF_SPEC
• extmem::l1_icache3_prelock_sct0_addr::L1_ICACHE3_PRELOCK_SCT0_ADDR_SPEC
• extmem::l1_icache3_prelock_sct1_addr::L1_ICACHE3_PRELOCK_SCT1_ADDR_SPEC
• extmem::l1_icache3_prelock_sct_size::L1_ICACHE3_PRELOCK_SCT_SIZE_SPEC
• extmem::l1_icache_blocksize_conf::L1_ICACHE_BLOCKSIZE_CONF_SPEC
• extmem::l1_icache_cachesize_conf::L1_ICACHE_CACHESIZE_CONF_SPEC
• extmem::l1_icache_ctrl::L1_ICACHE_CTRL_SPEC
• extmem::l1_unallocate_buffer_clear::L1_UNALLOCATE_BUFFER_CLEAR_SPEC
• extmem::l2_bypass_cache_conf::L2_BYPASS_CACHE_CONF_SPEC
• extmem::l2_cache_access_attr_ctrl::L2_CACHE_ACCESS_ATTR_CTRL_SPEC
• extmem::l2_cache_acs_cnt_ctrl::L2_CACHE_ACS_CNT_CTRL_SPEC
• extmem::l2_cache_acs_cnt_int_clr::L2_CACHE_ACS_CNT_INT_CLR_SPEC
• extmem::l2_cache_acs_cnt_int_ena::L2_CACHE_ACS_CNT_INT_ENA_SPEC
• extmem::l2_cache_acs_cnt_int_raw::L2_CACHE_ACS_CNT_INT_RAW_SPEC
• extmem::l2_cache_acs_cnt_int_st::L2_CACHE_ACS_CNT_INT_ST_SPEC
• extmem::l2_cache_acs_fail_addr::L2_CACHE_ACS_FAIL_ADDR_SPEC
• extmem::l2_cache_acs_fail_id_attr::L2_CACHE_ACS_FAIL_ID_ATTR_SPEC
• extmem::l2_cache_acs_fail_int_clr::L2_CACHE_ACS_FAIL_INT_CLR_SPEC
• extmem::l2_cache_acs_fail_int_ena::L2_CACHE_ACS_FAIL_INT_ENA_SPEC
• extmem::l2_cache_acs_fail_int_raw::L2_CACHE_ACS_FAIL_INT_RAW_SPEC
• extmem::l2_cache_acs_fail_int_st::L2_CACHE_ACS_FAIL_INT_ST_SPEC
• extmem::l2_cache_autoload_buf_clr_ctrl::L2_CACHE_AUTOLOAD_BUF_CLR_CTRL_SPEC
• extmem::l2_cache_autoload_ctrl::L2_CACHE_AUTOLOAD_CTRL_SPEC
• extmem::l2_cache_autoload_sct0_addr::L2_CACHE_AUTOLOAD_SCT0_ADDR_SPEC
• extmem::l2_cache_autoload_sct0_size::L2_CACHE_AUTOLOAD_SCT0_SIZE_SPEC
• extmem::l2_cache_autoload_sct1_addr::L2_CACHE_AUTOLOAD_SCT1_ADDR_SPEC
• extmem::l2_cache_autoload_sct1_size::L2_CACHE_AUTOLOAD_SCT1_SIZE_SPEC
• extmem::l2_cache_autoload_sct2_addr::L2_CACHE_AUTOLOAD_SCT2_ADDR_SPEC
• extmem::l2_cache_autoload_sct2_size::L2_CACHE_AUTOLOAD_SCT2_SIZE_SPEC
• extmem::l2_cache_autoload_sct3_addr::L2_CACHE_AUTOLOAD_SCT3_ADDR_SPEC
• extmem::l2_cache_autoload_sct3_size::L2_CACHE_AUTOLOAD_SCT3_SIZE_SPEC
• extmem::l2_cache_blocksize_conf::L2_CACHE_BLOCKSIZE_CONF_SPEC
• extmem::l2_cache_cachesize_conf::L2_CACHE_CACHESIZE_CONF_SPEC
• extmem::l2_cache_ctrl::L2_CACHE_CTRL_SPEC
• extmem::l2_cache_data_mem_acs_conf::L2_CACHE_DATA_MEM_ACS_CONF_SPEC
• extmem::l2_cache_data_mem_power_ctrl::L2_CACHE_DATA_MEM_POWER_CTRL_SPEC
• extmem::l2_cache_debug_bus::L2_CACHE_DEBUG_BUS_SPEC
• extmem::l2_cache_freeze_ctrl::L2_CACHE_FREEZE_CTRL_SPEC
• extmem::l2_cache_object_ctrl::L2_CACHE_OBJECT_CTRL_SPEC
• extmem::l2_cache_preload_addr::L2_CACHE_PRELOAD_ADDR_SPEC
• extmem::l2_cache_preload_ctrl::L2_CACHE_PRELOAD_CTRL_SPEC
• extmem::l2_cache_preload_rst_ctrl::L2_CACHE_PRELOAD_RST_CTRL_SPEC
• extmem::l2_cache_preload_size::L2_CACHE_PRELOAD_SIZE_SPEC
• extmem::l2_cache_prelock_conf::L2_CACHE_PRELOCK_CONF_SPEC
• extmem::l2_cache_prelock_sct0_addr::L2_CACHE_PRELOCK_SCT0_ADDR_SPEC
• extmem::l2_cache_prelock_sct1_addr::L2_CACHE_PRELOCK_SCT1_ADDR_SPEC
• extmem::l2_cache_prelock_sct_size::L2_CACHE_PRELOCK_SCT_SIZE_SPEC
• extmem::l2_cache_sync_preload_exception::L2_CACHE_SYNC_PRELOAD_EXCEPTION_SPEC
• extmem::l2_cache_sync_preload_int_clr::L2_CACHE_SYNC_PRELOAD_INT_CLR_SPEC
• extmem::l2_cache_sync_preload_int_ena::L2_CACHE_SYNC_PRELOAD_INT_ENA_SPEC
• extmem::l2_cache_sync_preload_int_raw::L2_CACHE_SYNC_PRELOAD_INT_RAW_SPEC
• extmem::l2_cache_sync_preload_int_st::L2_CACHE_SYNC_PRELOAD_INT_ST_SPEC
• extmem::l2_cache_sync_rst_ctrl::L2_CACHE_SYNC_RST_CTRL_SPEC
• extmem::l2_cache_tag_mem_acs_conf::L2_CACHE_TAG_MEM_ACS_CONF_SPEC
• extmem::l2_cache_tag_mem_power_ctrl::L2_CACHE_TAG_MEM_POWER_CTRL_SPEC
• extmem::l2_cache_vaddr::L2_CACHE_VADDR_SPEC
• extmem::l2_cache_way_object::L2_CACHE_WAY_OBJECT_SPEC
• extmem::l2_cache_wrap_around_ctrl::L2_CACHE_WRAP_AROUND_CTRL_SPEC
• extmem::l2_dbus0_acs_conflict_cnt::L2_DBUS0_ACS_CONFLICT_CNT_SPEC
• extmem::l2_dbus0_acs_hit_cnt::L2_DBUS0_ACS_HIT_CNT_SPEC
• extmem::l2_dbus0_acs_miss_cnt::L2_DBUS0_ACS_MISS_CNT_SPEC
• extmem::l2_dbus0_acs_nxtlvl_cnt::L2_DBUS0_ACS_NXTLVL_CNT_SPEC
• extmem::l2_dbus1_acs_conflict_cnt::L2_DBUS1_ACS_CONFLICT_CNT_SPEC
• extmem::l2_dbus1_acs_hit_cnt::L2_DBUS1_ACS_HIT_CNT_SPEC
• extmem::l2_dbus1_acs_miss_cnt::L2_DBUS1_ACS_MISS_CNT_SPEC
• extmem::l2_dbus1_acs_nxtlvl_cnt::L2_DBUS1_ACS_NXTLVL_CNT_SPEC
• extmem::l2_dbus2_acs_conflict_cnt::L2_DBUS2_ACS_CONFLICT_CNT_SPEC
• extmem::l2_dbus2_acs_hit_cnt::L2_DBUS2_ACS_HIT_CNT_SPEC
• extmem::l2_dbus2_acs_miss_cnt::L2_DBUS2_ACS_MISS_CNT_SPEC
• extmem::l2_dbus2_acs_nxtlvl_cnt::L2_DBUS2_ACS_NXTLVL_CNT_SPEC
• extmem::l2_dbus3_acs_conflict_cnt::L2_DBUS3_ACS_CONFLICT_CNT_SPEC
• extmem::l2_dbus3_acs_hit_cnt::L2_DBUS3_ACS_HIT_CNT_SPEC
• extmem::l2_dbus3_acs_miss_cnt::L2_DBUS3_ACS_MISS_CNT_SPEC
• extmem::l2_dbus3_acs_nxtlvl_cnt::L2_DBUS3_ACS_NXTLVL_CNT_SPEC
• extmem::l2_ibus0_acs_conflict_cnt::L2_IBUS0_ACS_CONFLICT_CNT_SPEC
• extmem::l2_ibus0_acs_hit_cnt::L2_IBUS0_ACS_HIT_CNT_SPEC
• extmem::l2_ibus0_acs_miss_cnt::L2_IBUS0_ACS_MISS_CNT_SPEC
• extmem::l2_ibus0_acs_nxtlvl_cnt::L2_IBUS0_ACS_NXTLVL_CNT_SPEC
• extmem::l2_ibus1_acs_conflict_cnt::L2_IBUS1_ACS_CONFLICT_CNT_SPEC
• extmem::l2_ibus1_acs_hit_cnt::L2_IBUS1_ACS_HIT_CNT_SPEC
• extmem::l2_ibus1_acs_miss_cnt::L2_IBUS1_ACS_MISS_CNT_SPEC
• extmem::l2_ibus1_acs_nxtlvl_cnt::L2_IBUS1_ACS_NXTLVL_CNT_SPEC
• extmem::l2_ibus2_acs_conflict_cnt::L2_IBUS2_ACS_CONFLICT_CNT_SPEC
• extmem::l2_ibus2_acs_hit_cnt::L2_IBUS2_ACS_HIT_CNT_SPEC
• extmem::l2_ibus2_acs_miss_cnt::L2_IBUS2_ACS_MISS_CNT_SPEC
• extmem::l2_ibus2_acs_nxtlvl_cnt::L2_IBUS2_ACS_NXTLVL_CNT_SPEC
• extmem::l2_ibus3_acs_conflict_cnt::L2_IBUS3_ACS_CONFLICT_CNT_SPEC
• extmem::l2_ibus3_acs_hit_cnt::L2_IBUS3_ACS_HIT_CNT_SPEC
• extmem::l2_ibus3_acs_miss_cnt::L2_IBUS3_ACS_MISS_CNT_SPEC
• extmem::l2_ibus3_acs_nxtlvl_cnt::L2_IBUS3_ACS_NXTLVL_CNT_SPEC
• extmem::l2_unallocate_buffer_clear::L2_UNALLOCATE_BUFFER_CLEAR_SPEC
• extmem::level_split0::LEVEL_SPLIT0_SPEC
• extmem::level_split1::LEVEL_SPLIT1_SPEC
• extmem::redundancy_sig0::REDUNDANCY_SIG0_SPEC
• extmem::redundancy_sig1::REDUNDANCY_SIG1_SPEC
• extmem::redundancy_sig2::REDUNDANCY_SIG2_SPEC
• extmem::redundancy_sig3::REDUNDANCY_SIG3_SPEC
• extmem::redundancy_sig4::REDUNDANCY_SIG4_SPEC
• generic::Range
• generic::RangeFrom
• generic::RangeTo
• generic::Reg
• generic::Safe
• generic::Unsafe
• gpio::RegisterBlock
• gpio::bt_select::BT_SELECT_SPEC
• gpio::clock_gate::CLOCK_GATE_SPEC
• gpio::cpusdio_int1::CPUSDIO_INT1_SPEC
• gpio::cpusdio_int::CPUSDIO_INT_SPEC
• gpio::date::DATE_SPEC
• gpio::enable1::ENABLE1_SPEC
• gpio::enable1_w1tc::ENABLE1_W1TC_SPEC
• gpio::enable1_w1ts::ENABLE1_W1TS_SPEC
• gpio::enable::ENABLE_SPEC
• gpio::enable_w1tc::ENABLE_W1TC_SPEC
• gpio::enable_w1ts::ENABLE_W1TS_SPEC
• gpio::func_in_sel_cfg::FUNC_IN_SEL_CFG_SPEC
• gpio::func_out_sel_cfg::FUNC_OUT_SEL_CFG_SPEC
• gpio::in1::IN1_SPEC
• gpio::in_::IN_SPEC
• gpio::out1::OUT1_SPEC
• gpio::out1_w1tc::OUT1_W1TC_SPEC
• gpio::out1_w1ts::OUT1_W1TS_SPEC
• gpio::out::OUT_SPEC
• gpio::out_w1tc::OUT_W1TC_SPEC
• gpio::out_w1ts::OUT_W1TS_SPEC
• gpio::pcpu_int1::PCPU_INT1_SPEC
• gpio::pcpu_int::PCPU_INT_SPEC
• gpio::pcpu_nmi_int1::PCPU_NMI_INT1_SPEC
• gpio::pcpu_nmi_int::PCPU_NMI_INT_SPEC
• gpio::pin::PIN_SPEC
• gpio::sdio_select::SDIO_SELECT_SPEC
• gpio::status1::STATUS1_SPEC
• gpio::status1_w1tc::STATUS1_W1TC_SPEC
• gpio::status1_w1ts::STATUS1_W1TS_SPEC
• gpio::status::STATUS_SPEC
• gpio::status_next1::STATUS_NEXT1_SPEC
• gpio::status_next::STATUS_NEXT_SPEC
• gpio::status_w1tc::STATUS_W1TC_SPEC
• gpio::status_w1ts::STATUS_W1TS_SPEC
• gpio::strap::STRAP_SPEC
• gpio_sd::RegisterBlock
• gpio_sd::clock_gate::CLOCK_GATE_SPEC
• gpio_sd::etm_event_ch_cfg::ETM_EVENT_CH_CFG_SPEC
• gpio_sd::etm_task_p0_cfg::ETM_TASK_P0_CFG_SPEC
• gpio_sd::etm_task_p1_cfg::ETM_TASK_P1_CFG_SPEC
• gpio_sd::etm_task_p2_cfg::ETM_TASK_P2_CFG_SPEC
• gpio_sd::etm_task_p3_cfg::ETM_TASK_P3_CFG_SPEC
• gpio_sd::etm_task_p4_cfg::ETM_TASK_P4_CFG_SPEC
• gpio_sd::etm_task_p5_cfg::ETM_TASK_P5_CFG_SPEC
• gpio_sd::etm_task_p6_cfg::ETM_TASK_P6_CFG_SPEC
• gpio_sd::etm_task_p7_cfg::ETM_TASK_P7_CFG_SPEC
• gpio_sd::glitch_filter_ch::GLITCH_FILTER_CH_SPEC
• gpio_sd::sigmadelta::SIGMADELTA_SPEC
• gpio_sd::sigmadelta_misc::SIGMADELTA_MISC_SPEC
• gpio_sd::version::VERSION_SPEC
• hinf::RegisterBlock
• hinf::cfg_data0::CFG_DATA0_SPEC
• hinf::cfg_data16::CFG_DATA16_SPEC
• hinf::cfg_data1::CFG_DATA1_SPEC
• hinf::cfg_data7::CFG_DATA7_SPEC
• hinf::cfg_timing::CFG_TIMING_SPEC
• hinf::cfg_uhs1_int_mode::CFG_UHS1_INT_MODE_SPEC
• hinf::cfg_update::CFG_UPDATE_SPEC
• hinf::cis_conf_w0::CIS_CONF_W0_SPEC
• hinf::cis_conf_w1::CIS_CONF_W1_SPEC
• hinf::cis_conf_w2::CIS_CONF_W2_SPEC
• hinf::cis_conf_w3::CIS_CONF_W3_SPEC
• hinf::cis_conf_w4::CIS_CONF_W4_SPEC
• hinf::cis_conf_w5::CIS_CONF_W5_SPEC
• hinf::cis_conf_w6::CIS_CONF_W6_SPEC
• hinf::cis_conf_w7::CIS_CONF_W7_SPEC
• hinf::conf_status::CONF_STATUS_SPEC
• hinf::sdio_date::SDIO_DATE_SPEC
• hinf::sdio_slave_eco_conf::SDIO_SLAVE_ECO_CONF_SPEC
• hinf::sdio_slave_eco_high::SDIO_SLAVE_ECO_HIGH_SPEC
• hinf::sdio_slave_eco_low::SDIO_SLAVE_ECO_LOW_SPEC
• hinf::sdio_slave_ldo_conf::SDIO_SLAVE_LDO_CONF_SPEC
• hmac::RegisterBlock
• hmac::date::DATE_SPEC
• hmac::one_block::ONE_BLOCK_SPEC
• hmac::query_busy::QUERY_BUSY_SPEC
• hmac::query_error::QUERY_ERROR_SPEC
• hmac::rd_result_mem::RD_RESULT_MEM_SPEC
• hmac::set_invalidate_ds::SET_INVALIDATE_DS_SPEC
• hmac::set_invalidate_jtag::SET_INVALIDATE_JTAG_SPEC
• hmac::set_message_end::SET_MESSAGE_END_SPEC
• hmac::set_message_ing::SET_MESSAGE_ING_SPEC
• hmac::set_message_one::SET_MESSAGE_ONE_SPEC
• hmac::set_message_pad::SET_MESSAGE_PAD_SPEC
• hmac::set_para_finish::SET_PARA_FINISH_SPEC
• hmac::set_para_key::SET_PARA_KEY_SPEC
• hmac::set_para_purpose::SET_PARA_PURPOSE_SPEC
• hmac::set_result_finish::SET_RESULT_FINISH_SPEC
• hmac::set_start::SET_START_SPEC
• hmac::soft_jtag_ctrl::SOFT_JTAG_CTRL_SPEC
• hmac::wr_jtag::WR_JTAG_SPEC
• hmac::wr_message_mem::WR_MESSAGE_MEM_SPEC
• hp_apm::RegisterBlock
• hp_apm::clock_gate::CLOCK_GATE_SPEC
• hp_apm::date::DATE_SPEC
• hp_apm::func_ctrl::FUNC_CTRL_SPEC
• hp_apm::int_en::INT_EN_SPEC
• hp_apm::m::M
• hp_apm::m::exception_info0::EXCEPTION_INFO0_SPEC
• hp_apm::m::exception_info1::EXCEPTION_INFO1_SPEC
• hp_apm::m::status::STATUS_SPEC
• hp_apm::m::status_clr::STATUS_CLR_SPEC
• hp_apm::region::REGION
• hp_apm::region::addr_end::ADDR_END_SPEC
• hp_apm::region::addr_start::ADDR_START_SPEC
• hp_apm::region::pms_attr::PMS_ATTR_SPEC
• hp_apm::region_filter_en::REGION_FILTER_EN_SPEC
• hp_sys::RegisterBlock
• hp_sys::clock_gate::CLOCK_GATE_SPEC
• hp_sys::core_debug_runstall_conf::CORE_DEBUG_RUNSTALL_CONF_SPEC
• hp_sys::cpu_peri_timeout_addr::CPU_PERI_TIMEOUT_ADDR_SPEC
• hp_sys::cpu_peri_timeout_conf::CPU_PERI_TIMEOUT_CONF_SPEC
• hp_sys::cpu_peri_timeout_uid::CPU_PERI_TIMEOUT_UID_SPEC
• hp_sys::date::DATE_SPEC
• hp_sys::external_device_encrypt_decrypt_control::EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_SPEC
• hp_sys::hp_peri_timeout_addr::HP_PERI_TIMEOUT_ADDR_SPEC
• hp_sys::hp_peri_timeout_conf::HP_PERI_TIMEOUT_CONF_SPEC
• hp_sys::hp_peri_timeout_uid::HP_PERI_TIMEOUT_UID_SPEC
• hp_sys::mem_test_conf::MEM_TEST_CONF_SPEC
• hp_sys::modem_peri_timeout_addr::MODEM_PERI_TIMEOUT_ADDR_SPEC
• hp_sys::modem_peri_timeout_conf::MODEM_PERI_TIMEOUT_CONF_SPEC
• hp_sys::modem_peri_timeout_uid::MODEM_PERI_TIMEOUT_UID_SPEC
• hp_sys::retention_conf::RETENTION_CONF_SPEC
• hp_sys::rnd_eco::RND_ECO_SPEC
• hp_sys::rnd_eco_high::RND_ECO_HIGH_SPEC
• hp_sys::rnd_eco_low::RND_ECO_LOW_SPEC
• hp_sys::rom_table::ROM_TABLE_SPEC
• hp_sys::rom_table_lock::ROM_TABLE_LOCK_SPEC
• hp_sys::sdio_ctrl::SDIO_CTRL_SPEC
• hp_sys::sec_dpa_conf::SEC_DPA_CONF_SPEC
• hp_sys::sram_usage_conf::SRAM_USAGE_CONF_SPEC
• i2c0::RegisterBlock
• i2c0::clk_conf::CLK_CONF_SPEC
• i2c0::comd::COMD_SPEC
• i2c0::ctr::CTR_SPEC
• i2c0::data::DATA_SPEC
• i2c0::date::DATE_SPEC
• i2c0::fifo_conf::FIFO_CONF_SPEC
• i2c0::fifo_st::FIFO_ST_SPEC
• i2c0::filter_cfg::FILTER_CFG_SPEC
• i2c0::int_clr::INT_CLR_SPEC
• i2c0::int_ena::INT_ENA_SPEC
• i2c0::int_raw::INT_RAW_SPEC
• i2c0::int_st::INT_ST_SPEC
• i2c0::rxfifo_start_addr::RXFIFO_START_ADDR_SPEC
• i2c0::scl_high_period::SCL_HIGH_PERIOD_SPEC
• i2c0::scl_low_period::SCL_LOW_PERIOD_SPEC
• i2c0::scl_main_st_time_out::SCL_MAIN_ST_TIME_OUT_SPEC
• i2c0::scl_rstart_setup::SCL_RSTART_SETUP_SPEC
• i2c0::scl_sp_conf::SCL_SP_CONF_SPEC
• i2c0::scl_st_time_out::SCL_ST_TIME_OUT_SPEC
• i2c0::scl_start_hold::SCL_START_HOLD_SPEC
• i2c0::scl_stop_hold::SCL_STOP_HOLD_SPEC
• i2c0::scl_stop_setup::SCL_STOP_SETUP_SPEC
• i2c0::scl_stretch_conf::SCL_STRETCH_CONF_SPEC
• i2c0::sda_hold::SDA_HOLD_SPEC
• i2c0::sda_sample::SDA_SAMPLE_SPEC
• i2c0::slave_addr::SLAVE_ADDR_SPEC
• i2c0::sr::SR_SPEC
• i2c0::to::TO_SPEC
• i2c0::txfifo_start_addr::TXFIFO_START_ADDR_SPEC
• i2c_ana_mst::RegisterBlock
• i2c_ana_mst::ana_conf0::ANA_CONF0_SPEC
• i2c_ana_mst::ana_conf1::ANA_CONF1_SPEC
• i2c_ana_mst::ana_conf2::ANA_CONF2_SPEC
• i2c_ana_mst::burst_conf::BURST_CONF_SPEC
• i2c_ana_mst::burst_status::BURST_STATUS_SPEC
• i2c_ana_mst::date::DATE_SPEC
• i2c_ana_mst::i2c0_conf::I2C0_CONF_SPEC
• i2c_ana_mst::i2c1_conf::I2C1_CONF_SPEC
• i2c_ana_mst::i2c_ctrl1::I2C_CTRL1_SPEC
• i2c_ana_mst::i2c_ctrl::I2C_CTRL_SPEC
• i2s0::RegisterBlock
• i2s0::conf_sigle_data::CONF_SIGLE_DATA_SPEC
• i2s0::date::DATE_SPEC
• i2s0::etm_conf::ETM_CONF_SPEC
• i2s0::int_clr::INT_CLR_SPEC
• i2s0::int_ena::INT_ENA_SPEC
• i2s0::int_raw::INT_RAW_SPEC
• i2s0::int_st::INT_ST_SPEC
• i2s0::lc_hung_conf::LC_HUNG_CONF_SPEC
• i2s0::rx_clkm_conf::RX_CLKM_CONF_SPEC
• i2s0::rx_clkm_div_conf::RX_CLKM_DIV_CONF_SPEC
• i2s0::rx_conf1::RX_CONF1_SPEC
• i2s0::rx_conf::RX_CONF_SPEC
• i2s0::rx_tdm_ctrl::RX_TDM_CTRL_SPEC
• i2s0::rx_timing::RX_TIMING_SPEC
• i2s0::rxeof_num::RXEOF_NUM_SPEC
• i2s0::state::STATE_SPEC
• i2s0::tx_clkm_conf::TX_CLKM_CONF_SPEC
• i2s0::tx_clkm_div_conf::TX_CLKM_DIV_CONF_SPEC
• i2s0::tx_conf1::TX_CONF1_SPEC
• i2s0::tx_conf::TX_CONF_SPEC
• i2s0::tx_pcm2pdm_conf1::TX_PCM2PDM_CONF1_SPEC
• i2s0::tx_pcm2pdm_conf::TX_PCM2PDM_CONF_SPEC
• i2s0::tx_tdm_ctrl::TX_TDM_CTRL_SPEC
• i2s0::tx_timing::TX_TIMING_SPEC
• ieee802154::RegisterBlock
• ieee802154::ack_frame_pending_en::ACK_FRAME_PENDING_EN_SPEC
• ieee802154::ack_timeout::ACK_TIMEOUT_SPEC
• ieee802154::bb_clk::BB_CLK_SPEC
• ieee802154::cca_busy_cnt::CCA_BUSY_CNT_SPEC
• ieee802154::cca_fail_cnt::CCA_FAIL_CNT_SPEC
• ieee802154::channel::CHANNEL_SPEC
• ieee802154::clk_counter::CLK_COUNTER_SPEC
• ieee802154::clk_counter_match_val::CLK_COUNTER_MATCH_VAL_SPEC
• ieee802154::coex_pti::COEX_PTI_SPEC
• ieee802154::command::COMMAND_SPEC
• ieee802154::cont_rx_delay::CONT_RX_DELAY_SPEC
• ieee802154::core_dummy_data::CORE_DUMMY_DATA_SPEC
• ieee802154::core_gck_cfg::CORE_GCK_CFG_SPEC
• ieee802154::crc_error_cnt::CRC_ERROR_CNT_SPEC
• ieee802154::ctrl_cfg::CTRL_CFG_SPEC
• ieee802154::dcdc_ctrl::DCDC_CTRL_SPEC
• ieee802154::debug_ctrl::DEBUG_CTRL_SPEC
• ieee802154::dma_dummy::DMA_DUMMY_SPEC
• ieee802154::dma_gck_cfg::DMA_GCK_CFG_SPEC
• ieee802154::dtm_config::DTM_CONFIG_SPEC
• ieee802154::dtm_pkt_counter::DTM_PKT_COUNTER_SPEC
• ieee802154::dtm_tx_pkt_config::DTM_TX_PKT_CONFIG_SPEC
• ieee802154::ed_abort_cnt::ED_ABORT_CNT_SPEC
• ieee802154::ed_scan_cfg::ED_SCAN_CFG_SPEC
• ieee802154::ed_scan_coex_cnt::ED_SCAN_COEX_CNT_SPEC
• ieee802154::ed_scan_duration::ED_SCAN_DURATION_SPEC
• ieee802154::enhance_ack_cfg::ENHANCE_ACK_CFG_SPEC
• ieee802154::error_cnt_clear::ERROR_CNT_CLEAR_SPEC
• ieee802154::event_en::EVENT_EN_SPEC
• ieee802154::event_status::EVENT_STATUS_SPEC
• ieee802154::ifs::IFS_SPEC
• ieee802154::ifs_counter::IFS_COUNTER_SPEC
• ieee802154::inf0_extend_addr0::INF0_EXTEND_ADDR0_SPEC
• ieee802154::inf0_extend_addr1::INF0_EXTEND_ADDR1_SPEC
• ieee802154::inf0_pan_id::INF0_PAN_ID_SPEC
• ieee802154::inf0_short_addr::INF0_SHORT_ADDR_SPEC
• ieee802154::inf1_extend_addr0::INF1_EXTEND_ADDR0_SPEC
• ieee802154::inf1_extend_addr1::INF1_EXTEND_ADDR1_SPEC
• ieee802154::inf1_pan_id::INF1_PAN_ID_SPEC
• ieee802154::inf1_short_addr::INF1_SHORT_ADDR_SPEC
• ieee802154::inf2_extend_addr0::INF2_EXTEND_ADDR0_SPEC
• ieee802154::inf2_extend_addr1::INF2_EXTEND_ADDR1_SPEC
• ieee802154::inf2_pan_id::INF2_PAN_ID_SPEC
• ieee802154::inf2_short_addr::INF2_SHORT_ADDR_SPEC
• ieee802154::inf3_extend_addr0::INF3_EXTEND_ADDR0_SPEC
• ieee802154::inf3_extend_addr1::INF3_EXTEND_ADDR1_SPEC
• ieee802154::inf3_pan_id::INF3_PAN_ID_SPEC
• ieee802154::inf3_short_addr::INF3_SHORT_ADDR_SPEC
• ieee802154::mac_date::MAC_DATE_SPEC
• ieee802154::no_rss_detect_cnt::NO_RSS_DETECT_CNT_SPEC
• ieee802154::paon_delay::PAON_DELAY_SPEC
• ieee802154::rx_abort_coex_cnt::RX_ABORT_COEX_CNT_SPEC
• ieee802154::rx_abort_intr_ctrl::RX_ABORT_INTR_CTRL_SPEC
• ieee802154::rx_ack_abort_coex_cnt::RX_ACK_ABORT_COEX_CNT_SPEC
• ieee802154::rx_ack_timeout_cnt::RX_ACK_TIMEOUT_CNT_SPEC
• ieee802154::rx_filter_fail_cnt::RX_FILTER_FAIL_CNT_SPEC
• ieee802154::rx_length::RX_LENGTH_SPEC
• ieee802154::rx_restart_cnt::RX_RESTART_CNT_SPEC
• ieee802154::rx_status::RX_STATUS_SPEC
• ieee802154::rxdma_addr::RXDMA_ADDR_SPEC
• ieee802154::rxdma_ctrl_state::RXDMA_CTRL_STATE_SPEC
• ieee802154::rxdma_err::RXDMA_ERR_SPEC
• ieee802154::rxon_delay::RXON_DELAY_SPEC
• ieee802154::sec_ctrl::SEC_CTRL_SPEC
• ieee802154::sec_extend_address0::SEC_EXTEND_ADDRESS0_SPEC
• ieee802154::sec_extend_address1::SEC_EXTEND_ADDRESS1_SPEC
• ieee802154::sec_key0::SEC_KEY0_SPEC
• ieee802154::sec_key1::SEC_KEY1_SPEC
• ieee802154::sec_key2::SEC_KEY2_SPEC
• ieee802154::sec_key3::SEC_KEY3_SPEC
• ieee802154::sfd_timeout_cnt::SFD_TIMEOUT_CNT_SPEC
• ieee802154::sfd_wait_symbol::SFD_WAIT_SYMBOL_SPEC
• ieee802154::test_control::TEST_CONTROL_SPEC
• ieee802154::time0_threshold::TIME0_THRESHOLD_SPEC
• ieee802154::time0_value::TIME0_VALUE_SPEC
• ieee802154::time1_threshold::TIME1_THRESHOLD_SPEC
• ieee802154::time1_value::TIME1_VALUE_SPEC
• ieee802154::tx_abort_interrupt_control::TX_ABORT_INTERRUPT_CONTROL_SPEC
• ieee802154::tx_ack_abort_coex_cnt::TX_ACK_ABORT_COEX_CNT_SPEC
• ieee802154::tx_break_coex_cnt::TX_BREAK_COEX_CNT_SPEC
• ieee802154::tx_ccm_schedule_status::TX_CCM_SCHEDULE_STATUS_SPEC
• ieee802154::tx_power::TX_POWER_SPEC
• ieee802154::tx_security_error_cnt::TX_SECURITY_ERROR_CNT_SPEC
• ieee802154::tx_status::TX_STATUS_SPEC
• ieee802154::txdma_addr::TXDMA_ADDR_SPEC
• ieee802154::txdma_ctrl_state::TXDMA_CTRL_STATE_SPEC
• ieee802154::txdma_err::TXDMA_ERR_SPEC
• ieee802154::txen_stop_delay::TXEN_STOP_DELAY_SPEC
• ieee802154::txoff_delay::TXOFF_DELAY_SPEC
• ieee802154::txon_delay::TXON_DELAY_SPEC
• ieee802154::txrx_path_delay::TXRX_PATH_DELAY_SPEC
• ieee802154::txrx_status::TXRX_STATUS_SPEC
• ieee802154::txrx_switch_delay::TXRX_SWITCH_DELAY_SPEC
• interrupt_core0::RegisterBlock
• interrupt_core0::aes_intr_map::AES_INTR_MAP_SPEC
• interrupt_core0::apb_adc_intr_map::APB_ADC_INTR_MAP_SPEC
• interrupt_core0::assist_debug_intr_map::ASSIST_DEBUG_INTR_MAP_SPEC
• interrupt_core0::ble_sec_intr_map::BLE_SEC_INTR_MAP_SPEC
• interrupt_core0::ble_timer_intr_map::BLE_TIMER_INTR_MAP_SPEC
• interrupt_core0::bt_bb_intr_map::BT_BB_INTR_MAP_SPEC
• interrupt_core0::bt_bb_nmi_map::BT_BB_NMI_MAP_SPEC
• interrupt_core0::bt_mac_intr_map::BT_MAC_INTR_MAP_SPEC
• interrupt_core0::cache_intr_map::CACHE_INTR_MAP_SPEC
• interrupt_core0::can0_intr_map::CAN0_INTR_MAP_SPEC
• interrupt_core0::can1_intr_map::CAN1_INTR_MAP_SPEC
• interrupt_core0::clock_gate::CLOCK_GATE_SPEC
• interrupt_core0::coex_intr_map::COEX_INTR_MAP_SPEC
• interrupt_core0::cpu_intr_from_cpu_0_map::CPU_INTR_FROM_CPU_0_MAP_SPEC
• interrupt_core0::cpu_intr_from_cpu_1_map::CPU_INTR_FROM_CPU_1_MAP_SPEC
• interrupt_core0::cpu_intr_from_cpu_2_map::CPU_INTR_FROM_CPU_2_MAP_SPEC
• interrupt_core0::cpu_intr_from_cpu_3_map::CPU_INTR_FROM_CPU_3_MAP_SPEC
• interrupt_core0::cpu_peri_timeout_intr_map::CPU_PERI_TIMEOUT_INTR_MAP_SPEC
• interrupt_core0::dma_in_ch0_intr_map::DMA_IN_CH0_INTR_MAP_SPEC
• interrupt_core0::dma_in_ch1_intr_map::DMA_IN_CH1_INTR_MAP_SPEC
• interrupt_core0::dma_in_ch2_intr_map::DMA_IN_CH2_INTR_MAP_SPEC
• interrupt_core0::dma_out_ch0_intr_map::DMA_OUT_CH0_INTR_MAP_SPEC
• interrupt_core0::dma_out_ch1_intr_map::DMA_OUT_CH1_INTR_MAP_SPEC
• interrupt_core0::dma_out_ch2_intr_map::DMA_OUT_CH2_INTR_MAP_SPEC
• interrupt_core0::ecc_intr_map::ECC_INTR_MAP_SPEC
• interrupt_core0::efuse_intr_map::EFUSE_INTR_MAP_SPEC
• interrupt_core0::gpio_interrupt_pro_map::GPIO_INTERRUPT_PRO_MAP_SPEC
• interrupt_core0::gpio_interrupt_pro_nmi_map::GPIO_INTERRUPT_PRO_NMI_MAP_SPEC
• interrupt_core0::gpspi2_intr_map::GPSPI2_INTR_MAP_SPEC
• interrupt_core0::hp_apm_m0_intr_map::HP_APM_M0_INTR_MAP_SPEC
• interrupt_core0::hp_apm_m1_intr_map::HP_APM_M1_INTR_MAP_SPEC
• interrupt_core0::hp_apm_m2_intr_map::HP_APM_M2_INTR_MAP_SPEC
• interrupt_core0::hp_apm_m3_intr_map::HP_APM_M3_INTR_MAP_SPEC
• interrupt_core0::hp_peri_timeout_intr_map::HP_PERI_TIMEOUT_INTR_MAP_SPEC
• interrupt_core0::i2c_ext0_intr_map::I2C_EXT0_INTR_MAP_SPEC
• interrupt_core0::i2c_mst_intr_map::I2C_MST_INTR_MAP_SPEC
• interrupt_core0::i2s1_intr_map::I2S1_INTR_MAP_SPEC
• interrupt_core0::int_status_reg_2::INT_STATUS_REG_2_SPEC
• interrupt_core0::interrupt_reg_date::INTERRUPT_REG_DATE_SPEC
• interrupt_core0::intr_status_reg_0::INTR_STATUS_REG_0_SPEC
• interrupt_core0::intr_status_reg_1::INTR_STATUS_REG_1_SPEC
• interrupt_core0::ledc_intr_map::LEDC_INTR_MAP_SPEC
• interrupt_core0::lp_apm0_intr_map::LP_APM0_INTR_MAP_SPEC
• interrupt_core0::lp_apm_m0_intr_map::LP_APM_M0_INTR_MAP_SPEC
• interrupt_core0::lp_apm_m1_intr_map::LP_APM_M1_INTR_MAP_SPEC
• interrupt_core0::lp_i2c_intr_map::LP_I2C_INTR_MAP_SPEC
• interrupt_core0::lp_peri_timeout_intr_map::LP_PERI_TIMEOUT_INTR_MAP_SPEC
• interrupt_core0::lp_rtc_timer_intr_map::LP_RTC_TIMER_INTR_MAP_SPEC
• interrupt_core0::lp_timer_intr_map::LP_TIMER_INTR_MAP_SPEC
• interrupt_core0::lp_uart_intr_map::LP_UART_INTR_MAP_SPEC
• interrupt_core0::lp_wdt_intr_map::LP_WDT_INTR_MAP_SPEC
• interrupt_core0::modem_peri_timeout_intr_map::MODEM_PERI_TIMEOUT_INTR_MAP_SPEC
• interrupt_core0::mspi_intr_map::MSPI_INTR_MAP_SPEC
• interrupt_core0::parl_io_intr_map::PARL_IO_INTR_MAP_SPEC
• interrupt_core0::pau_intr_map::PAU_INTR_MAP_SPEC
• interrupt_core0::pcnt_intr_map::PCNT_INTR_MAP_SPEC
• interrupt_core0::pmu_intr_map::PMU_INTR_MAP_SPEC
• interrupt_core0::pwm_intr_map::PWM_INTR_MAP_SPEC
• interrupt_core0::rmt_intr_map::RMT_INTR_MAP_SPEC
• interrupt_core0::rsa_intr_map::RSA_INTR_MAP_SPEC
• interrupt_core0::sha_intr_map::SHA_INTR_MAP_SPEC
• interrupt_core0::slc0_intr_map::SLC0_INTR_MAP_SPEC
• interrupt_core0::slc1_intr_map::SLC1_INTR_MAP_SPEC
• interrupt_core0::systimer_target0_intr_map::SYSTIMER_TARGET0_INTR_MAP_SPEC
• interrupt_core0::systimer_target1_intr_map::SYSTIMER_TARGET1_INTR_MAP_SPEC
• interrupt_core0::systimer_target2_intr_map::SYSTIMER_TARGET2_INTR_MAP_SPEC
• interrupt_core0::tg0_t0_intr_map::TG0_T0_INTR_MAP_SPEC
• interrupt_core0::tg0_t1_intr_map::TG0_T1_INTR_MAP_SPEC
• interrupt_core0::tg0_wdt_intr_map::TG0_WDT_INTR_MAP_SPEC
• interrupt_core0::tg1_t0_intr_map::TG1_T0_INTR_MAP_SPEC
• interrupt_core0::tg1_t1_intr_map::TG1_T1_INTR_MAP_SPEC
• interrupt_core0::tg1_wdt_intr_map::TG1_WDT_INTR_MAP_SPEC
• interrupt_core0::trace_intr_map::TRACE_INTR_MAP_SPEC
• interrupt_core0::uart0_intr_map::UART0_INTR_MAP_SPEC
• interrupt_core0::uart1_intr_map::UART1_INTR_MAP_SPEC
• interrupt_core0::uhci0_intr_map::UHCI0_INTR_MAP_SPEC
• interrupt_core0::usb_intr_map::USB_INTR_MAP_SPEC
• interrupt_core0::wifi_bb_intr_map::WIFI_BB_INTR_MAP_SPEC
• interrupt_core0::wifi_mac_intr_map::WIFI_MAC_INTR_MAP_SPEC
• interrupt_core0::wifi_mac_nmi_map::WIFI_MAC_NMI_MAP_SPEC
• interrupt_core0::wifi_pwr_intr_map::WIFI_PWR_INTR_MAP_SPEC
• interrupt_core0::zb_mac_intr_map::ZB_MAC_INTR_MAP_SPEC
• intpri::RegisterBlock
• intpri::clock_gate::CLOCK_GATE_SPEC
• intpri::cpu_int_clear::CPU_INT_CLEAR_SPEC
• intpri::cpu_int_eip_status::CPU_INT_EIP_STATUS_SPEC
• intpri::cpu_int_enable::CPU_INT_ENABLE_SPEC
• intpri::cpu_int_pri::CPU_INT_PRI_SPEC
• intpri::cpu_int_thresh::CPU_INT_THRESH_SPEC
• intpri::cpu_int_type::CPU_INT_TYPE_SPEC
• intpri::cpu_intr_from_cpu_0::CPU_INTR_FROM_CPU_0_SPEC
• intpri::cpu_intr_from_cpu_1::CPU_INTR_FROM_CPU_1_SPEC
• intpri::cpu_intr_from_cpu_2::CPU_INTR_FROM_CPU_2_SPEC
• intpri::cpu_intr_from_cpu_3::CPU_INTR_FROM_CPU_3_SPEC
• intpri::date::DATE_SPEC
• intpri::rnd_eco::RND_ECO_SPEC
• intpri::rnd_eco_high::RND_ECO_HIGH_SPEC
• intpri::rnd_eco_low::RND_ECO_LOW_SPEC
• io_mux::RegisterBlock
• io_mux::date::DATE_SPEC
• io_mux::gpio::GPIO_SPEC
• io_mux::modem_diag_en::MODEM_DIAG_EN_SPEC
• io_mux::pin_ctrl::PIN_CTRL_SPEC
• ledc::RegisterBlock
• ledc::ch::CH
• ledc::ch::conf0::CONF0_SPEC
• ledc::ch::conf1::CONF1_SPEC
• ledc::ch::duty::DUTY_SPEC
• ledc::ch::duty_r::DUTY_R_SPEC
• ledc::ch::hpoint::HPOINT_SPEC
• ledc::ch_gamma_conf::CH_GAMMA_CONF_SPEC
• ledc::ch_gamma_rd_addr::CH_GAMMA_RD_ADDR_SPEC
• ledc::ch_gamma_rd_data::CH_GAMMA_RD_DATA_SPEC
• ledc::ch_gamma_wr::CH_GAMMA_WR_SPEC
• ledc::ch_gamma_wr_addr::CH_GAMMA_WR_ADDR_SPEC
• ledc::conf::CONF_SPEC
• ledc::date::DATE_SPEC
• ledc::evt_task_en0::EVT_TASK_EN0_SPEC
• ledc::evt_task_en1::EVT_TASK_EN1_SPEC
• ledc::evt_task_en2::EVT_TASK_EN2_SPEC
• ledc::int_clr::INT_CLR_SPEC
• ledc::int_ena::INT_ENA_SPEC
• ledc::int_raw::INT_RAW_SPEC
• ledc::int_st::INT_ST_SPEC
• ledc::timer::TIMER
• ledc::timer::conf::CONF_SPEC
• ledc::timer::value::VALUE_SPEC
• ledc::timer_cmp::TIMER_CMP_SPEC
• ledc::timer_cnt_cap::TIMER_CNT_CAP_SPEC
• lp_ana::RegisterBlock
• lp_ana::bod_mode0_cntl::BOD_MODE0_CNTL_SPEC
• lp_ana::bod_mode1_cntl::BOD_MODE1_CNTL_SPEC
• lp_ana::ck_glitch_cntl::CK_GLITCH_CNTL_SPEC
• lp_ana::date::DATE_SPEC
• lp_ana::fib_enable::FIB_ENABLE_SPEC
• lp_ana::int_clr::INT_CLR_SPEC
• lp_ana::int_ena::INT_ENA_SPEC
• lp_ana::int_raw::INT_RAW_SPEC
• lp_ana::int_st::INT_ST_SPEC
• lp_ana::lp_int_clr::LP_INT_CLR_SPEC
• lp_ana::lp_int_ena::LP_INT_ENA_SPEC
• lp_ana::lp_int_raw::LP_INT_RAW_SPEC
• lp_ana::lp_int_st::LP_INT_ST_SPEC
• lp_aon::RegisterBlock
• lp_aon::cpucore0_cfg::CPUCORE0_CFG_SPEC
• lp_aon::date::DATE_SPEC
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_CNTL_SPEC
• lp_aon::gpio_hold0::GPIO_HOLD0_SPEC
• lp_aon::gpio_hold1::GPIO_HOLD1_SPEC
• lp_aon::gpio_mux::GPIO_MUX_SPEC
• lp_aon::io_mux::IO_MUX_SPEC
• lp_aon::lpbus::LPBUS_SPEC
• lp_aon::lpcore::LPCORE_SPEC
• lp_aon::sar_cct::SAR_CCT_SPEC
• lp_aon::sdio_active::SDIO_ACTIVE_SPEC
• lp_aon::store0::STORE0_SPEC
• lp_aon::store1::STORE1_SPEC
• lp_aon::store2::STORE2_SPEC
• lp_aon::store3::STORE3_SPEC
• lp_aon::store4::STORE4_SPEC
• lp_aon::store5::STORE5_SPEC
• lp_aon::store6::STORE6_SPEC
• lp_aon::store7::STORE7_SPEC
• lp_aon::store8::STORE8_SPEC
• lp_aon::store9::STORE9_SPEC
• lp_aon::sys_cfg::SYS_CFG_SPEC
• lp_aon::usb::USB_SPEC
• lp_apm0::RegisterBlock
• lp_apm0::clock_gate::CLOCK_GATE_SPEC
• lp_apm0::date::DATE_SPEC
• lp_apm0::func_ctrl::FUNC_CTRL_SPEC
• lp_apm0::int_en::INT_EN_SPEC
• lp_apm0::m::M
• lp_apm0::m::exception_info0::EXCEPTION_INFO0_SPEC
• lp_apm0::m::exception_info1::EXCEPTION_INFO1_SPEC
• lp_apm0::m::status::STATUS_SPEC
• lp_apm0::m::status_clr::STATUS_CLR_SPEC
• lp_apm0::region::REGION
• lp_apm0::region::addr_end::ADDR_END_SPEC
• lp_apm0::region::addr_start::ADDR_START_SPEC
• lp_apm0::region::pms_attr::PMS_ATTR_SPEC
• lp_apm0::region_filter_en::REGION_FILTER_EN_SPEC
• lp_apm::RegisterBlock
• lp_apm::clock_gate::CLOCK_GATE_SPEC
• lp_apm::date::DATE_SPEC
• lp_apm::func_ctrl::FUNC_CTRL_SPEC
• lp_apm::int_en::INT_EN_SPEC
• lp_apm::m::M
• lp_apm::m::exception_info0::EXCEPTION_INFO0_SPEC
• lp_apm::m::exception_info1::EXCEPTION_INFO1_SPEC
• lp_apm::m::status::STATUS_SPEC
• lp_apm::m::status_clr::STATUS_CLR_SPEC
• lp_apm::region::REGION
• lp_apm::region::addr_end::ADDR_END_SPEC
• lp_apm::region::addr_start::ADDR_START_SPEC
• lp_apm::region::pms_attr::PMS_ATTR_SPEC
• lp_apm::region_filter_en::REGION_FILTER_EN_SPEC
• lp_clkrst::RegisterBlock
• lp_clkrst::clk_to_hp::CLK_TO_HP_SPEC
• lp_clkrst::cpu_reset::CPU_RESET_SPEC
• lp_clkrst::date::DATE_SPEC
• lp_clkrst::fosc_cntl::FOSC_CNTL_SPEC
• lp_clkrst::lp_clk_conf::LP_CLK_CONF_SPEC
• lp_clkrst::lp_clk_en::LP_CLK_EN_SPEC
• lp_clkrst::lp_clk_po_en::LP_CLK_PO_EN_SPEC
• lp_clkrst::lp_rst_en::LP_RST_EN_SPEC
• lp_clkrst::lpmem_force::LPMEM_FORCE_SPEC
• lp_clkrst::lpperi::LPPERI_SPEC
• lp_clkrst::rc32k_cntl::RC32K_CNTL_SPEC
• lp_clkrst::reset_cause::RESET_CAUSE_SPEC
• lp_clkrst::xtal32k::XTAL32K_SPEC
• lp_i2c0::RegisterBlock
• lp_i2c0::clk_conf::CLK_CONF_SPEC
• lp_i2c0::comd::COMD_SPEC
• lp_i2c0::ctr::CTR_SPEC
• lp_i2c0::data::DATA_SPEC
• lp_i2c0::date::DATE_SPEC
• lp_i2c0::fifo_conf::FIFO_CONF_SPEC
• lp_i2c0::fifo_st::FIFO_ST_SPEC
• lp_i2c0::filter_cfg::FILTER_CFG_SPEC
• lp_i2c0::int_clr::INT_CLR_SPEC
• lp_i2c0::int_ena::INT_ENA_SPEC
• lp_i2c0::int_raw::INT_RAW_SPEC
• lp_i2c0::int_st::INT_ST_SPEC
• lp_i2c0::rxfifo_start_addr::RXFIFO_START_ADDR_SPEC
• lp_i2c0::scl_high_period::SCL_HIGH_PERIOD_SPEC
• lp_i2c0::scl_low_period::SCL_LOW_PERIOD_SPEC
• lp_i2c0::scl_main_st_time_out::SCL_MAIN_ST_TIME_OUT_SPEC
• lp_i2c0::scl_rstart_setup::SCL_RSTART_SETUP_SPEC
• lp_i2c0::scl_sp_conf::SCL_SP_CONF_SPEC
• lp_i2c0::scl_st_time_out::SCL_ST_TIME_OUT_SPEC
• lp_i2c0::scl_start_hold::SCL_START_HOLD_SPEC
• lp_i2c0::scl_stop_hold::SCL_STOP_HOLD_SPEC
• lp_i2c0::scl_stop_setup::SCL_STOP_SETUP_SPEC
• lp_i2c0::sda_hold::SDA_HOLD_SPEC
• lp_i2c0::sda_sample::SDA_SAMPLE_SPEC
• lp_i2c0::sr::SR_SPEC
• lp_i2c0::to::TO_SPEC
• lp_i2c0::txfifo_start_addr::TXFIFO_START_ADDR_SPEC
• lp_i2c_ana_mst::RegisterBlock
• lp_i2c_ana_mst::ana_conf1::ANA_CONF1_SPEC
• lp_i2c_ana_mst::date::DATE_SPEC
• lp_i2c_ana_mst::device_en::DEVICE_EN_SPEC
• lp_i2c_ana_mst::i2c0_conf::I2C0_CONF_SPEC
• lp_i2c_ana_mst::i2c0_ctrl::I2C0_CTRL_SPEC
• lp_i2c_ana_mst::i2c0_data::I2C0_DATA_SPEC
• lp_i2c_ana_mst::nouse::NOUSE_SPEC
• lp_io::RegisterBlock
• lp_io::date::DATE_SPEC
• lp_io::debug_sel0::DEBUG_SEL0_SPEC
• lp_io::debug_sel1::DEBUG_SEL1_SPEC
• lp_io::gpio::GPIO_SPEC
• lp_io::in_::IN_SPEC
• lp_io::lpi2c::LPI2C_SPEC
• lp_io::out_data::OUT_DATA_SPEC
• lp_io::out_data_w1tc::OUT_DATA_W1TC_SPEC
• lp_io::out_data_w1ts::OUT_DATA_W1TS_SPEC
• lp_io::out_enable::OUT_ENABLE_SPEC
• lp_io::out_enable_w1tc::OUT_ENABLE_W1TC_SPEC
• lp_io::out_enable_w1ts::OUT_ENABLE_W1TS_SPEC
• lp_io::pin::PIN_SPEC
• lp_io::status::STATUS_SPEC
• lp_io::status_interrupt::STATUS_INTERRUPT_SPEC
• lp_io::status_w1tc::STATUS_W1TC_SPEC
• lp_io::status_w1ts::STATUS_W1TS_SPEC
• lp_peri::RegisterBlock
• lp_peri::bus_timeout::BUS_TIMEOUT_SPEC
• lp_peri::bus_timeout_addr::BUS_TIMEOUT_ADDR_SPEC
• lp_peri::bus_timeout_uid::BUS_TIMEOUT_UID_SPEC
• lp_peri::clk_en::CLK_EN_SPEC
• lp_peri::cpu::CPU_SPEC
• lp_peri::date::DATE_SPEC
• lp_peri::interrupt_source::INTERRUPT_SOURCE_SPEC
• lp_peri::mem_ctrl::MEM_CTRL_SPEC
• lp_peri::reset_en::RESET_EN_SPEC
• lp_peri::rng_data::RNG_DATA_SPEC
• lp_tee::RegisterBlock
• lp_tee::clock_gate::CLOCK_GATE_SPEC
• lp_tee::date::DATE_SPEC
• lp_tee::force_acc_hp::FORCE_ACC_HP_SPEC
• lp_tee::m_mode_ctrl::M_MODE_CTRL_SPEC
• lp_timer::RegisterBlock
• lp_timer::date::DATE_SPEC
• lp_timer::int_clr::INT_CLR_SPEC
• lp_timer::int_ena::INT_ENA_SPEC
• lp_timer::int_raw::INT_RAW_SPEC
• lp_timer::int_st::INT_ST_SPEC
• lp_timer::lp_int_clr::LP_INT_CLR_SPEC
• lp_timer::lp_int_ena::LP_INT_ENA_SPEC
• lp_timer::lp_int_raw::LP_INT_RAW_SPEC
• lp_timer::lp_int_st::LP_INT_ST_SPEC
• lp_timer::main_buf0_high::MAIN_BUF0_HIGH_SPEC
• lp_timer::main_buf0_low::MAIN_BUF0_LOW_SPEC
• lp_timer::main_buf1_high::MAIN_BUF1_HIGH_SPEC
• lp_timer::main_buf1_low::MAIN_BUF1_LOW_SPEC
• lp_timer::main_overflow::MAIN_OVERFLOW_SPEC
• lp_timer::tar0_high::TAR0_HIGH_SPEC
• lp_timer::tar0_low::TAR0_LOW_SPEC
• lp_timer::tar1_high::TAR1_HIGH_SPEC
• lp_timer::tar1_low::TAR1_LOW_SPEC
• lp_timer::update::UPDATE_SPEC
• lp_uart::RegisterBlock
• lp_uart::afifo_status::AFIFO_STATUS_SPEC
• lp_uart::at_cmd_char::AT_CMD_CHAR_SPEC
• lp_uart::at_cmd_gaptout::AT_CMD_GAPTOUT_SPEC
• lp_uart::at_cmd_postcnt::AT_CMD_POSTCNT_SPEC
• lp_uart::at_cmd_precnt::AT_CMD_PRECNT_SPEC
• lp_uart::clk_conf::CLK_CONF_SPEC
• lp_uart::clkdiv::CLKDIV_SPEC
• lp_uart::conf0::CONF0_SPEC
• lp_uart::conf1::CONF1_SPEC
• lp_uart::date::DATE_SPEC
• lp_uart::fifo::FIFO_SPEC
• lp_uart::fsm_status::FSM_STATUS_SPEC
• lp_uart::hwfc_conf::HWFC_CONF_SPEC
• lp_uart::id::ID_SPEC
• lp_uart::idle_conf::IDLE_CONF_SPEC
• lp_uart::int_clr::INT_CLR_SPEC
• lp_uart::int_ena::INT_ENA_SPEC
• lp_uart::int_raw::INT_RAW_SPEC
• lp_uart::int_st::INT_ST_SPEC
• lp_uart::mem_conf::MEM_CONF_SPEC
• lp_uart::mem_rx_status::MEM_RX_STATUS_SPEC
• lp_uart::mem_tx_status::MEM_TX_STATUS_SPEC
• lp_uart::reg_update::REG_UPDATE_SPEC
• lp_uart::rs485_conf::RS485_CONF_SPEC
• lp_uart::rx_filt::RX_FILT_SPEC
• lp_uart::sleep_conf0::SLEEP_CONF0_SPEC
• lp_uart::sleep_conf1::SLEEP_CONF1_SPEC
• lp_uart::sleep_conf2::SLEEP_CONF2_SPEC
• lp_uart::status::STATUS_SPEC
• lp_uart::swfc_conf0::SWFC_CONF0_SPEC
• lp_uart::swfc_conf1::SWFC_CONF1_SPEC
• lp_uart::tout_conf::TOUT_CONF_SPEC
• lp_uart::txbrk_conf::TXBRK_CONF_SPEC
• lp_wdt::RegisterBlock
• lp_wdt::config1::CONFIG1_SPEC
• lp_wdt::config2::CONFIG2_SPEC
• lp_wdt::config3::CONFIG3_SPEC
• lp_wdt::config4::CONFIG4_SPEC
• lp_wdt::date::DATE_SPEC
• lp_wdt::int_clr::INT_CLR_SPEC
• lp_wdt::int_ena::INT_ENA_SPEC
• lp_wdt::int_raw::INT_RAW_SPEC
• lp_wdt::int_st::INT_ST_SPEC
• lp_wdt::swd_conf::SWD_CONF_SPEC
• lp_wdt::swd_wprotect::SWD_WPROTECT_SPEC
• lp_wdt::wdtconfig0::WDTCONFIG0_SPEC
• lp_wdt::wdtfeed::WDTFEED_SPEC
• lp_wdt::wdtwprotect::WDTWPROTECT_SPEC
• mcpwm0::RegisterBlock
• mcpwm0::cap_ch::CAP_CH_SPEC
• mcpwm0::cap_ch_cfg::CAP_CH_CFG_SPEC
• mcpwm0::cap_status::CAP_STATUS_SPEC
• mcpwm0::cap_timer_cfg::CAP_TIMER_CFG_SPEC
• mcpwm0::cap_timer_phase::CAP_TIMER_PHASE_SPEC
• mcpwm0::ch::CH
• mcpwm0::ch::carrier_cfg::CARRIER_CFG_SPEC
• mcpwm0::ch::dt_cfg::DT_CFG_SPEC
• mcpwm0::ch::dt_fed_cfg::DT_FED_CFG_SPEC
• mcpwm0::ch::dt_red_cfg::DT_RED_CFG_SPEC
• mcpwm0::ch::fh_cfg0::FH_CFG0_SPEC
• mcpwm0::ch::fh_cfg1::FH_CFG1_SPEC
• mcpwm0::ch::fh_status::FH_STATUS_SPEC
• mcpwm0::ch::gen::GEN_SPEC
• mcpwm0::ch::gen_cfg0::GEN_CFG0_SPEC
• mcpwm0::ch::gen_force::GEN_FORCE_SPEC
• mcpwm0::ch::gen_stmp_cfg::GEN_STMP_CFG_SPEC
• mcpwm0::ch::gen_tstmp_a::GEN_TSTMP_A_SPEC
• mcpwm0::ch::gen_tstmp_b::GEN_TSTMP_B_SPEC
• mcpwm0::clk::CLK_SPEC
• mcpwm0::clk_cfg::CLK_CFG_SPEC
• mcpwm0::evt_en::EVT_EN_SPEC
• mcpwm0::fault_detect::FAULT_DETECT_SPEC
• mcpwm0::int_clr::INT_CLR_SPEC
• mcpwm0::int_ena::INT_ENA_SPEC
• mcpwm0::int_raw::INT_RAW_SPEC
• mcpwm0::int_st::INT_ST_SPEC
• mcpwm0::operator_timersel::OPERATOR_TIMERSEL_SPEC
• mcpwm0::task_en::TASK_EN_SPEC
• mcpwm0::timer::TIMER
• mcpwm0::timer::cfg0::CFG0_SPEC
• mcpwm0::timer::cfg1::CFG1_SPEC
• mcpwm0::timer::status::STATUS_SPEC
• mcpwm0::timer::sync::SYNC_SPEC
• mcpwm0::timer_synci_cfg::TIMER_SYNCI_CFG_SPEC
• mcpwm0::update_cfg::UPDATE_CFG_SPEC
• mcpwm0::version::VERSION_SPEC
• mem_monitor::RegisterBlock
• mem_monitor::clock_gate::CLOCK_GATE_SPEC
• mem_monitor::date::DATE_SPEC
• mem_monitor::log_check_data::LOG_CHECK_DATA_SPEC
• mem_monitor::log_data_mask::LOG_DATA_MASK_SPEC
• mem_monitor::log_max::LOG_MAX_SPEC
• mem_monitor::log_mem_addr_update::LOG_MEM_ADDR_UPDATE_SPEC
• mem_monitor::log_mem_current_addr::LOG_MEM_CURRENT_ADDR_SPEC
• mem_monitor::log_mem_end::LOG_MEM_END_SPEC
• mem_monitor::log_mem_full_flag::LOG_MEM_FULL_FLAG_SPEC
• mem_monitor::log_mem_start::LOG_MEM_START_SPEC
• mem_monitor::log_min::LOG_MIN_SPEC
• mem_monitor::log_setting::LOG_SETTING_SPEC
• modem_lpcon::RegisterBlock
• modem_lpcon::clk_conf::CLK_CONF_SPEC
• modem_lpcon::clk_conf_force_on::CLK_CONF_FORCE_ON_SPEC
• modem_lpcon::clk_conf_power_st::CLK_CONF_POWER_ST_SPEC
• modem_lpcon::coex_lp_clk_conf::COEX_LP_CLK_CONF_SPEC
• modem_lpcon::date::DATE_SPEC
• modem_lpcon::i2c_mst_clk_conf::I2C_MST_CLK_CONF_SPEC
• modem_lpcon::lp_timer_conf::LP_TIMER_CONF_SPEC
• modem_lpcon::mem_conf::MEM_CONF_SPEC
• modem_lpcon::modem_32k_clk_conf::MODEM_32K_CLK_CONF_SPEC
• modem_lpcon::rst_conf::RST_CONF_SPEC
• modem_lpcon::test_conf::TEST_CONF_SPEC
• modem_lpcon::wifi_lp_clk_conf::WIFI_LP_CLK_CONF_SPEC
• modem_syscon::RegisterBlock
• modem_syscon::clk_conf1::CLK_CONF1_SPEC
• modem_syscon::clk_conf1_force_on::CLK_CONF1_FORCE_ON_SPEC
• modem_syscon::clk_conf::CLK_CONF_SPEC
• modem_syscon::clk_conf_force_on::CLK_CONF_FORCE_ON_SPEC
• modem_syscon::clk_conf_power_st::CLK_CONF_POWER_ST_SPEC
• modem_syscon::date::DATE_SPEC
• modem_syscon::mem_conf::MEM_CONF_SPEC
• modem_syscon::modem_rst_conf::MODEM_RST_CONF_SPEC
• modem_syscon::test_conf::TEST_CONF_SPEC
• modem_syscon::wifi_bb_cfg::WIFI_BB_CFG_SPEC
• otp_debug::RegisterBlock
• otp_debug::apb2otp_en::APB2OTP_EN_SPEC
• otp_debug::blk0_backup1_w1::BLK0_BACKUP1_W1_SPEC
• otp_debug::blk0_backup1_w2::BLK0_BACKUP1_W2_SPEC
• otp_debug::blk0_backup1_w3::BLK0_BACKUP1_W3_SPEC
• otp_debug::blk0_backup1_w4::BLK0_BACKUP1_W4_SPEC
• otp_debug::blk0_backup1_w5::BLK0_BACKUP1_W5_SPEC
• otp_debug::blk0_backup2_w1::BLK0_BACKUP2_W1_SPEC
• otp_debug::blk0_backup2_w2::BLK0_BACKUP2_W2_SPEC
• otp_debug::blk0_backup2_w3::BLK0_BACKUP2_W3_SPEC
• otp_debug::blk0_backup2_w4::BLK0_BACKUP2_W4_SPEC
• otp_debug::blk0_backup2_w5::BLK0_BACKUP2_W5_SPEC
• otp_debug::blk0_backup3_w1::BLK0_BACKUP3_W1_SPEC
• otp_debug::blk0_backup3_w2::BLK0_BACKUP3_W2_SPEC
• otp_debug::blk0_backup3_w3::BLK0_BACKUP3_W3_SPEC
• otp_debug::blk0_backup3_w4::BLK0_BACKUP3_W4_SPEC
• otp_debug::blk0_backup3_w5::BLK0_BACKUP3_W5_SPEC
• otp_debug::blk0_backup4_w1::BLK0_BACKUP4_W1_SPEC
• otp_debug::blk0_backup4_w2::BLK0_BACKUP4_W2_SPEC
• otp_debug::blk0_backup4_w3::BLK0_BACKUP4_W3_SPEC
• otp_debug::blk0_backup4_w4::BLK0_BACKUP4_W4_SPEC
• otp_debug::blk0_backup4_w5::BLK0_BACKUP4_W5_SPEC
• otp_debug::blk10_w10::BLK10_W10_SPEC
• otp_debug::blk10_w11::BLK10_W11_SPEC
• otp_debug::blk10_w1::BLK10_W1_SPEC
• otp_debug::blk10_w2::BLK10_W2_SPEC
• otp_debug::blk10_w3::BLK10_W3_SPEC
• otp_debug::blk10_w4::BLK10_W4_SPEC
• otp_debug::blk10_w5::BLK10_W5_SPEC
• otp_debug::blk10_w6::BLK10_W6_SPEC
• otp_debug::blk10_w7::BLK10_W7_SPEC
• otp_debug::blk10_w8::BLK10_W8_SPEC
• otp_debug::blk10_w9::BLK10_W9_SPEC
• otp_debug::blk1_w1::BLK1_W1_SPEC
• otp_debug::blk1_w2::BLK1_W2_SPEC
• otp_debug::blk1_w3::BLK1_W3_SPEC
• otp_debug::blk1_w4::BLK1_W4_SPEC
• otp_debug::blk1_w5::BLK1_W5_SPEC
• otp_debug::blk1_w6::BLK1_W6_SPEC
• otp_debug::blk1_w7::BLK1_W7_SPEC
• otp_debug::blk1_w8::BLK1_W8_SPEC
• otp_debug::blk1_w9::BLK1_W9_SPEC
• otp_debug::blk2_w10::BLK2_W10_SPEC
• otp_debug::blk2_w11::BLK2_W11_SPEC
• otp_debug::blk2_w1::BLK2_W1_SPEC
• otp_debug::blk2_w2::BLK2_W2_SPEC
• otp_debug::blk2_w3::BLK2_W3_SPEC
• otp_debug::blk2_w4::BLK2_W4_SPEC
• otp_debug::blk2_w5::BLK2_W5_SPEC
• otp_debug::blk2_w6::BLK2_W6_SPEC
• otp_debug::blk2_w7::BLK2_W7_SPEC
• otp_debug::blk2_w8::BLK2_W8_SPEC
• otp_debug::blk2_w9::BLK2_W9_SPEC
• otp_debug::blk3_w10::BLK3_W10_SPEC
• otp_debug::blk3_w11::BLK3_W11_SPEC
• otp_debug::blk3_w1::BLK3_W1_SPEC
• otp_debug::blk3_w2::BLK3_W2_SPEC
• otp_debug::blk3_w3::BLK3_W3_SPEC
• otp_debug::blk3_w4::BLK3_W4_SPEC
• otp_debug::blk3_w5::BLK3_W5_SPEC
• otp_debug::blk3_w6::BLK3_W6_SPEC
• otp_debug::blk3_w7::BLK3_W7_SPEC
• otp_debug::blk3_w8::BLK3_W8_SPEC
• otp_debug::blk3_w9::BLK3_W9_SPEC
• otp_debug::blk4_w10::BLK4_W10_SPEC
• otp_debug::blk4_w11::BLK4_W11_SPEC
• otp_debug::blk4_w1::BLK4_W1_SPEC
• otp_debug::blk4_w2::BLK4_W2_SPEC
• otp_debug::blk4_w3::BLK4_W3_SPEC
• otp_debug::blk4_w4::BLK4_W4_SPEC
• otp_debug::blk4_w5::BLK4_W5_SPEC
• otp_debug::blk4_w6::BLK4_W6_SPEC
• otp_debug::blk4_w7::BLK4_W7_SPEC
• otp_debug::blk4_w8::BLK4_W8_SPEC
• otp_debug::blk4_w9::BLK4_W9_SPEC
• otp_debug::blk5_w10::BLK5_W10_SPEC
• otp_debug::blk5_w11::BLK5_W11_SPEC
• otp_debug::blk5_w1::BLK5_W1_SPEC
• otp_debug::blk5_w2::BLK5_W2_SPEC
• otp_debug::blk5_w3::BLK5_W3_SPEC
• otp_debug::blk5_w4::BLK5_W4_SPEC
• otp_debug::blk5_w5::BLK5_W5_SPEC
• otp_debug::blk5_w6::BLK5_W6_SPEC
• otp_debug::blk5_w7::BLK5_W7_SPEC
• otp_debug::blk5_w8::BLK5_W8_SPEC
• otp_debug::blk5_w9::BLK5_W9_SPEC
• otp_debug::blk6_w10::BLK6_W10_SPEC
• otp_debug::blk6_w11::BLK6_W11_SPEC
• otp_debug::blk6_w1::BLK6_W1_SPEC
• otp_debug::blk6_w2::BLK6_W2_SPEC
• otp_debug::blk6_w3::BLK6_W3_SPEC
• otp_debug::blk6_w4::BLK6_W4_SPEC
• otp_debug::blk6_w5::BLK6_W5_SPEC
• otp_debug::blk6_w6::BLK6_W6_SPEC
• otp_debug::blk6_w7::BLK6_W7_SPEC
• otp_debug::blk6_w8::BLK6_W8_SPEC
• otp_debug::blk6_w9::BLK6_W9_SPEC
• otp_debug::blk7_w10::BLK7_W10_SPEC
• otp_debug::blk7_w11::BLK7_W11_SPEC
• otp_debug::blk7_w1::BLK7_W1_SPEC
• otp_debug::blk7_w2::BLK7_W2_SPEC
• otp_debug::blk7_w3::BLK7_W3_SPEC
• otp_debug::blk7_w4::BLK7_W4_SPEC
• otp_debug::blk7_w5::BLK7_W5_SPEC
• otp_debug::blk7_w6::BLK7_W6_SPEC
• otp_debug::blk7_w7::BLK7_W7_SPEC
• otp_debug::blk7_w8::BLK7_W8_SPEC
• otp_debug::blk7_w9::BLK7_W9_SPEC
• otp_debug::blk8_w10::BLK8_W10_SPEC
• otp_debug::blk8_w11::BLK8_W11_SPEC
• otp_debug::blk8_w1::BLK8_W1_SPEC
• otp_debug::blk8_w2::BLK8_W2_SPEC
• otp_debug::blk8_w3::BLK8_W3_SPEC
• otp_debug::blk8_w4::BLK8_W4_SPEC
• otp_debug::blk8_w5::BLK8_W5_SPEC
• otp_debug::blk8_w6::BLK8_W6_SPEC
• otp_debug::blk8_w7::BLK8_W7_SPEC
• otp_debug::blk8_w8::BLK8_W8_SPEC
• otp_debug::blk8_w9::BLK8_W9_SPEC
• otp_debug::blk9_w10::BLK9_W10_SPEC
• otp_debug::blk9_w11::BLK9_W11_SPEC
• otp_debug::blk9_w1::BLK9_W1_SPEC
• otp_debug::blk9_w2::BLK9_W2_SPEC
• otp_debug::blk9_w3::BLK9_W3_SPEC
• otp_debug::blk9_w4::BLK9_W4_SPEC
• otp_debug::blk9_w5::BLK9_W5_SPEC
• otp_debug::blk9_w6::BLK9_W6_SPEC
• otp_debug::blk9_w7::BLK9_W7_SPEC
• otp_debug::blk9_w8::BLK9_W8_SPEC
• otp_debug::blk9_w9::BLK9_W9_SPEC
• otp_debug::clk::CLK_SPEC
• otp_debug::date::DATE_SPEC
• otp_debug::wr_dis::WR_DIS_SPEC
• parl_io::RegisterBlock
• parl_io::clk::CLK_SPEC
• parl_io::int_clr::INT_CLR_SPEC
• parl_io::int_ena::INT_ENA_SPEC
• parl_io::int_raw::INT_RAW_SPEC
• parl_io::int_st::INT_ST_SPEC
• parl_io::rx_cfg0::RX_CFG0_SPEC
• parl_io::rx_cfg1::RX_CFG1_SPEC
• parl_io::st::ST_SPEC
• parl_io::tx_cfg0::TX_CFG0_SPEC
• parl_io::tx_cfg1::TX_CFG1_SPEC
• parl_io::version::VERSION_SPEC
• pau::RegisterBlock
• pau::date::DATE_SPEC
• pau::int_clr::INT_CLR_SPEC
• pau::int_ena::INT_ENA_SPEC
• pau::int_raw::INT_RAW_SPEC
• pau::int_st::INT_ST_SPEC
• pau::regdma_backup_addr::REGDMA_BACKUP_ADDR_SPEC
• pau::regdma_bkp_conf::REGDMA_BKP_CONF_SPEC
• pau::regdma_clk_conf::REGDMA_CLK_CONF_SPEC
• pau::regdma_conf::REGDMA_CONF_SPEC
• pau::regdma_current_link_addr::REGDMA_CURRENT_LINK_ADDR_SPEC
• pau::regdma_etm_ctrl::REGDMA_ETM_CTRL_SPEC
• pau::regdma_link_0_addr::REGDMA_LINK_0_ADDR_SPEC
• pau::regdma_link_1_addr::REGDMA_LINK_1_ADDR_SPEC
• pau::regdma_link_2_addr::REGDMA_LINK_2_ADDR_SPEC
• pau::regdma_link_3_addr::REGDMA_LINK_3_ADDR_SPEC
• pau::regdma_link_mac_addr::REGDMA_LINK_MAC_ADDR_SPEC
• pau::regdma_mem_addr::REGDMA_MEM_ADDR_SPEC
• pau::retention_cfg::RETENTION_CFG_SPEC
• pau::retention_link_base::RETENTION_LINK_BASE_SPEC
• pcnt::RegisterBlock
• pcnt::ctrl::CTRL_SPEC
• pcnt::date::DATE_SPEC
• pcnt::int_clr::INT_CLR_SPEC
• pcnt::int_ena::INT_ENA_SPEC
• pcnt::int_raw::INT_RAW_SPEC
• pcnt::int_st::INT_ST_SPEC
• pcnt::u_cnt::U_CNT_SPEC
• pcnt::u_status::U_STATUS_SPEC
• pcnt::unit::UNIT
• pcnt::unit::conf0::CONF0_SPEC
• pcnt::unit::conf1::CONF1_SPEC
• pcnt::unit::conf2::CONF2_SPEC
• pcr::RegisterBlock
• pcr::aes_conf::AES_CONF_SPEC
• pcr::ahb_freq_conf::AHB_FREQ_CONF_SPEC
• pcr::apb_freq_conf::APB_FREQ_CONF_SPEC
• pcr::assist_conf::ASSIST_CONF_SPEC
• pcr::cache_conf::CACHE_CONF_SPEC
• pcr::clock_gate::CLOCK_GATE_SPEC
• pcr::cpu_freq_conf::CPU_FREQ_CONF_SPEC
• pcr::cpu_waiti_conf::CPU_WAITI_CONF_SPEC
• pcr::ctrl_32k_conf::CTRL_32K_CONF_SPEC
• pcr::ctrl_clk_out_en::CTRL_CLK_OUT_EN_SPEC
• pcr::ctrl_tick_conf::CTRL_TICK_CONF_SPEC
• pcr::date::DATE_SPEC
• pcr::ds_conf::DS_CONF_SPEC
• pcr::ecc_conf::ECC_CONF_SPEC
• pcr::ecc_pd_ctrl::ECC_PD_CTRL_SPEC
• pcr::etm_conf::ETM_CONF_SPEC
• pcr::fpga_debug::FPGA_DEBUG_SPEC
• pcr::gdma_conf::GDMA_CONF_SPEC
• pcr::hmac_conf::HMAC_CONF_SPEC
• pcr::i2c0_conf::I2C0_CONF_SPEC
• pcr::i2c_sclk_conf::I2C_SCLK_CONF_SPEC
• pcr::i2s_conf::I2S_CONF_SPEC
• pcr::i2s_rx_clkm_conf::I2S_RX_CLKM_CONF_SPEC
• pcr::i2s_rx_clkm_div_conf::I2S_RX_CLKM_DIV_CONF_SPEC
• pcr::i2s_tx_clkm_conf::I2S_TX_CLKM_CONF_SPEC
• pcr::i2s_tx_clkm_div_conf::I2S_TX_CLKM_DIV_CONF_SPEC
• pcr::intmtx_conf::INTMTX_CONF_SPEC
• pcr::iomux_clk_conf::IOMUX_CLK_CONF_SPEC
• pcr::iomux_conf::IOMUX_CONF_SPEC
• pcr::ledc_conf::LEDC_CONF_SPEC
• pcr::ledc_sclk_conf::LEDC_SCLK_CONF_SPEC
• pcr::mem_monitor_conf::MEM_MONITOR_CONF_SPEC
• pcr::modem_apb_conf::MODEM_APB_CONF_SPEC
• pcr::mspi_clk_conf::MSPI_CLK_CONF_SPEC
• pcr::mspi_conf::MSPI_CONF_SPEC
• pcr::parl_clk_rx_conf::PARL_CLK_RX_CONF_SPEC
• pcr::parl_clk_tx_conf::PARL_CLK_TX_CONF_SPEC
• pcr::parl_io_conf::PARL_IO_CONF_SPEC
• pcr::pcnt_conf::PCNT_CONF_SPEC
• pcr::pll_div_clk_en::PLL_DIV_CLK_EN_SPEC
• pcr::pvt_monitor_conf::PVT_MONITOR_CONF_SPEC
• pcr::pvt_monitor_func_clk_conf::PVT_MONITOR_FUNC_CLK_CONF_SPEC
• pcr::pwm_clk_conf::PWM_CLK_CONF_SPEC
• pcr::pwm_conf::PWM_CONF_SPEC
• pcr::regdma_conf::REGDMA_CONF_SPEC
• pcr::reset_event_bypass::RESET_EVENT_BYPASS_SPEC
• pcr::retention_conf::RETENTION_CONF_SPEC
• pcr::rmt_conf::RMT_CONF_SPEC
• pcr::rmt_sclk_conf::RMT_SCLK_CONF_SPEC
• pcr::rsa_conf::RSA_CONF_SPEC
• pcr::rsa_pd_ctrl::RSA_PD_CTRL_SPEC
• pcr::saradc_clkm_conf::SARADC_CLKM_CONF_SPEC
• pcr::saradc_conf::SARADC_CONF_SPEC
• pcr::sdio_slave_conf::SDIO_SLAVE_CONF_SPEC
• pcr::sha_conf::SHA_CONF_SPEC
• pcr::spi2_clkm_conf::SPI2_CLKM_CONF_SPEC
• pcr::spi2_conf::SPI2_CONF_SPEC
• pcr::sram_power_conf::SRAM_POWER_CONF_SPEC
• pcr::sysclk_conf::SYSCLK_CONF_SPEC
• pcr::sysclk_freq_query_0::SYSCLK_FREQ_QUERY_0_SPEC
• pcr::systimer_conf::SYSTIMER_CONF_SPEC
• pcr::systimer_func_clk_conf::SYSTIMER_FUNC_CLK_CONF_SPEC
• pcr::timeout_conf::TIMEOUT_CONF_SPEC
• pcr::timergroup0_conf::TIMERGROUP0_CONF_SPEC
• pcr::timergroup0_timer_clk_conf::TIMERGROUP0_TIMER_CLK_CONF_SPEC
• pcr::timergroup0_wdt_clk_conf::TIMERGROUP0_WDT_CLK_CONF_SPEC
• pcr::timergroup1_conf::TIMERGROUP1_CONF_SPEC
• pcr::timergroup1_timer_clk_conf::TIMERGROUP1_TIMER_CLK_CONF_SPEC
• pcr::timergroup1_wdt_clk_conf::TIMERGROUP1_WDT_CLK_CONF_SPEC
• pcr::trace_conf::TRACE_CONF_SPEC
• pcr::tsens_clk_conf::TSENS_CLK_CONF_SPEC
• pcr::twai0_conf::TWAI0_CONF_SPEC
• pcr::twai0_func_clk_conf::TWAI0_FUNC_CLK_CONF_SPEC
• pcr::twai1_conf::TWAI1_CONF_SPEC
• pcr::twai1_func_clk_conf::TWAI1_FUNC_CLK_CONF_SPEC
• pcr::uart::UART
• pcr::uart::clk_conf::CLK_CONF_SPEC
• pcr::uart::conf::CONF_SPEC
• pcr::uart::pd_ctrl::PD_CTRL_SPEC
• pcr::uhci_conf::UHCI_CONF_SPEC
• pcr::usb_device_conf::USB_DEVICE_CONF_SPEC
• plic_mx::RegisterBlock
• plic_mx::emip_status::EMIP_STATUS_SPEC
• plic_mx::mxint_claim::MXINT_CLAIM_SPEC
• plic_mx::mxint_clear::MXINT_CLEAR_SPEC
• plic_mx::mxint_enable::MXINT_ENABLE_SPEC
• plic_mx::mxint_pri::MXINT_PRI_SPEC
• plic_mx::mxint_thresh::MXINT_THRESH_SPEC
• plic_mx::mxint_type::MXINT_TYPE_SPEC
• plic_ux::RegisterBlock
• plic_ux::euip_status::EUIP_STATUS_SPEC
• plic_ux::uxint_claim::UXINT_CLAIM_SPEC
• plic_ux::uxint_clear::UXINT_CLEAR_SPEC
• plic_ux::uxint_enable::UXINT_ENABLE_SPEC
• plic_ux::uxint_pri::UXINT_PRI_SPEC
• plic_ux::uxint_thresh::UXINT_THRESH_SPEC
• plic_ux::uxint_type::UXINT_TYPE_SPEC
• pmu::RegisterBlock
• pmu::backup_cfg::BACKUP_CFG_SPEC
• pmu::clk_state0::CLK_STATE0_SPEC
• pmu::clk_state1::CLK_STATE1_SPEC
• pmu::clk_state2::CLK_STATE2_SPEC
• pmu::date::DATE_SPEC
• pmu::hp_active_backup::HP_ACTIVE_BACKUP_SPEC
• pmu::hp_active_backup_clk::HP_ACTIVE_BACKUP_CLK_SPEC
• pmu::hp_active_bias::HP_ACTIVE_BIAS_SPEC
• pmu::hp_active_dig_power::HP_ACTIVE_DIG_POWER_SPEC
• pmu::hp_active_hp_ck_power::HP_ACTIVE_HP_CK_POWER_SPEC
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR0_SPEC
• pmu::hp_active_hp_regulator1::HP_ACTIVE_HP_REGULATOR1_SPEC
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_HP_SYS_CNTL_SPEC
• pmu::hp_active_icg_hp_apb::HP_ACTIVE_ICG_HP_APB_SPEC
• pmu::hp_active_icg_hp_func::HP_ACTIVE_ICG_HP_FUNC_SPEC
• pmu::hp_active_icg_modem::HP_ACTIVE_ICG_MODEM_SPEC
• pmu::hp_active_sysclk::HP_ACTIVE_SYSCLK_SPEC
• pmu::hp_active_xtal::HP_ACTIVE_XTAL_SPEC
• pmu::hp_ck_cntl::HP_CK_CNTL_SPEC
• pmu::hp_ck_poweron::HP_CK_POWERON_SPEC
• pmu::hp_lp_cpu_comm::HP_LP_CPU_COMM_SPEC
• pmu::hp_modem_backup::HP_MODEM_BACKUP_SPEC
• pmu::hp_modem_backup_clk::HP_MODEM_BACKUP_CLK_SPEC
• pmu::hp_modem_bias::HP_MODEM_BIAS_SPEC
• pmu::hp_modem_dig_power::HP_MODEM_DIG_POWER_SPEC
• pmu::hp_modem_hp_ck_power::HP_MODEM_HP_CK_POWER_SPEC
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR0_SPEC
• pmu::hp_modem_hp_regulator1::HP_MODEM_HP_REGULATOR1_SPEC
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_HP_SYS_CNTL_SPEC
• pmu::hp_modem_icg_hp_apb::HP_MODEM_ICG_HP_APB_SPEC
• pmu::hp_modem_icg_hp_func::HP_MODEM_ICG_HP_FUNC_SPEC
• pmu::hp_modem_icg_modem::HP_MODEM_ICG_MODEM_SPEC
• pmu::hp_modem_sysclk::HP_MODEM_SYSCLK_SPEC
• pmu::hp_modem_xtal::HP_MODEM_XTAL_SPEC
• pmu::hp_regulator_cfg::HP_REGULATOR_CFG_SPEC
• pmu::hp_sleep_backup::HP_SLEEP_BACKUP_SPEC
• pmu::hp_sleep_backup_clk::HP_SLEEP_BACKUP_CLK_SPEC
• pmu::hp_sleep_bias::HP_SLEEP_BIAS_SPEC
• pmu::hp_sleep_dig_power::HP_SLEEP_DIG_POWER_SPEC
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_HP_CK_POWER_SPEC
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR0_SPEC
• pmu::hp_sleep_hp_regulator1::HP_SLEEP_HP_REGULATOR1_SPEC
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_HP_SYS_CNTL_SPEC
• pmu::hp_sleep_icg_hp_apb::HP_SLEEP_ICG_HP_APB_SPEC
• pmu::hp_sleep_icg_hp_func::HP_SLEEP_ICG_HP_FUNC_SPEC
• pmu::hp_sleep_icg_modem::HP_SLEEP_ICG_MODEM_SPEC
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_LP_CK_POWER_SPEC
• pmu::hp_sleep_lp_dcdc_reserve::HP_SLEEP_LP_DCDC_RESERVE_SPEC
• pmu::hp_sleep_lp_dig_power::HP_SLEEP_LP_DIG_POWER_SPEC
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR0_SPEC
• pmu::hp_sleep_lp_regulator1::HP_SLEEP_LP_REGULATOR1_SPEC
• pmu::hp_sleep_sysclk::HP_SLEEP_SYSCLK_SPEC
• pmu::hp_sleep_xtal::HP_SLEEP_XTAL_SPEC
• pmu::imm_hp_apb_icg::IMM_HP_APB_ICG_SPEC
• pmu::imm_hp_ck_power::IMM_HP_CK_POWER_SPEC
• pmu::imm_hp_func_icg::IMM_HP_FUNC_ICG_SPEC
• pmu::imm_i2c_iso::IMM_I2C_ISO_SPEC
• pmu::imm_lp_icg::IMM_LP_ICG_SPEC
• pmu::imm_modem_icg::IMM_MODEM_ICG_SPEC
• pmu::imm_pad_hold_all::IMM_PAD_HOLD_ALL_SPEC
• pmu::imm_sleep_sysclk::IMM_SLEEP_SYSCLK_SPEC
• pmu::int_clr::INT_CLR_SPEC
• pmu::int_ena::INT_ENA_SPEC
• pmu::int_raw::INT_RAW_SPEC
• pmu::int_st::INT_ST_SPEC
• pmu::lp_cpu_pwr0::LP_CPU_PWR0_SPEC
• pmu::lp_cpu_pwr1::LP_CPU_PWR1_SPEC
• pmu::lp_int_clr::LP_INT_CLR_SPEC
• pmu::lp_int_ena::LP_INT_ENA_SPEC
• pmu::lp_int_raw::LP_INT_RAW_SPEC
• pmu::lp_int_st::LP_INT_ST_SPEC
• pmu::lp_sleep_bias::LP_SLEEP_BIAS_SPEC
• pmu::lp_sleep_lp_bias_reserve::LP_SLEEP_LP_BIAS_RESERVE_SPEC
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_LP_CK_POWER_SPEC
• pmu::lp_sleep_lp_dig_power::LP_SLEEP_LP_DIG_POWER_SPEC
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR0_SPEC
• pmu::lp_sleep_lp_regulator1::LP_SLEEP_LP_REGULATOR1_SPEC
• pmu::lp_sleep_xtal::LP_SLEEP_XTAL_SPEC
• pmu::main_state::MAIN_STATE_SPEC
• pmu::por_status::POR_STATUS_SPEC
• pmu::power_ck_wait_cntl::POWER_CK_WAIT_CNTL_SPEC
• pmu::power_hp_pad::POWER_HP_PAD_SPEC
• pmu::power_pd_hpaon_cntl::POWER_PD_HPAON_CNTL_SPEC
• pmu::power_pd_hpcpu_cntl::POWER_PD_HPCPU_CNTL_SPEC
• pmu::power_pd_hpperi_reserve::POWER_PD_HPPERI_RESERVE_SPEC
• pmu::power_pd_hpwifi_cntl::POWER_PD_HPWIFI_CNTL_SPEC
• pmu::power_pd_lpperi_cntl::POWER_PD_LPPERI_CNTL_SPEC
• pmu::power_pd_mem_cntl::POWER_PD_MEM_CNTL_SPEC
• pmu::power_pd_mem_mask::POWER_PD_MEM_MASK_SPEC
• pmu::power_pd_top_cntl::POWER_PD_TOP_CNTL_SPEC
• pmu::power_vdd_spi_cntl::POWER_VDD_SPI_CNTL_SPEC
• pmu::power_wait_timer0::POWER_WAIT_TIMER0_SPEC
• pmu::power_wait_timer1::POWER_WAIT_TIMER1_SPEC
• pmu::pwr_state::PWR_STATE_SPEC
• pmu::rf_pwc::RF_PWC_SPEC
• pmu::slp_wakeup_cntl0::SLP_WAKEUP_CNTL0_SPEC
• pmu::slp_wakeup_cntl1::SLP_WAKEUP_CNTL1_SPEC
• pmu::slp_wakeup_cntl2::SLP_WAKEUP_CNTL2_SPEC
• pmu::slp_wakeup_cntl3::SLP_WAKEUP_CNTL3_SPEC
• pmu::slp_wakeup_cntl4::SLP_WAKEUP_CNTL4_SPEC
• pmu::slp_wakeup_cntl5::SLP_WAKEUP_CNTL5_SPEC
• pmu::slp_wakeup_cntl6::SLP_WAKEUP_CNTL6_SPEC
• pmu::slp_wakeup_cntl7::SLP_WAKEUP_CNTL7_SPEC
• pmu::slp_wakeup_status0::SLP_WAKEUP_STATUS0_SPEC
• pmu::slp_wakeup_status1::SLP_WAKEUP_STATUS1_SPEC
• pmu::vdd_spi_status::VDD_SPI_STATUS_SPEC
• rmt::RegisterBlock
• rmt::ch_rx_carrier_rm::CH_RX_CARRIER_RM_SPEC
• rmt::ch_rx_conf0::CH_RX_CONF0_SPEC
• rmt::ch_rx_conf1::CH_RX_CONF1_SPEC
• rmt::ch_rx_lim::CH_RX_LIM_SPEC
• rmt::ch_rx_status::CH_RX_STATUS_SPEC
• rmt::ch_tx_conf0::CH_TX_CONF0_SPEC
• rmt::ch_tx_lim::CH_TX_LIM_SPEC
• rmt::ch_tx_status::CH_TX_STATUS_SPEC
• rmt::chcarrier_duty::CHCARRIER_DUTY_SPEC
• rmt::chdata::CHDATA_SPEC
• rmt::date::DATE_SPEC
• rmt::int_clr::INT_CLR_SPEC
• rmt::int_ena::INT_ENA_SPEC
• rmt::int_raw::INT_RAW_SPEC
• rmt::int_st::INT_ST_SPEC
• rmt::ref_cnt_rst::REF_CNT_RST_SPEC
• rmt::sys_conf::SYS_CONF_SPEC
• rmt::tx_sim::TX_SIM_SPEC
• rng::RegisterBlock
• rng::data::DATA_SPEC
• rsa::RegisterBlock
• rsa::constant_time::CONSTANT_TIME_SPEC
• rsa::date::DATE_SPEC
• rsa::int_clr::INT_CLR_SPEC
• rsa::int_ena::INT_ENA_SPEC
• rsa::m_mem::M_MEM_SPEC
• rsa::m_prime::M_PRIME_SPEC
• rsa::mode::MODE_SPEC
• rsa::query_clean::QUERY_CLEAN_SPEC
• rsa::query_idle::QUERY_IDLE_SPEC
• rsa::search_enable::SEARCH_ENABLE_SPEC
• rsa::search_pos::SEARCH_POS_SPEC
• rsa::set_start_modexp::SET_START_MODEXP_SPEC
• rsa::set_start_modmult::SET_START_MODMULT_SPEC
• rsa::set_start_mult::SET_START_MULT_SPEC
• rsa::x_mem::X_MEM_SPEC
• rsa::y_mem::Y_MEM_SPEC
• rsa::z_mem::Z_MEM_SPEC
• sha::RegisterBlock
• sha::busy::BUSY_SPEC
• sha::clear_irq::CLEAR_IRQ_SPEC
• sha::continue_::CONTINUE_SPEC
• sha::date::DATE_SPEC
• sha::dma_block_num::DMA_BLOCK_NUM_SPEC
• sha::dma_continue::DMA_CONTINUE_SPEC
• sha::dma_start::DMA_START_SPEC
• sha::h_mem::H_MEM_SPEC
• sha::irq_ena::IRQ_ENA_SPEC
• sha::m_mem::M_MEM_SPEC
• sha::mode::MODE_SPEC
• sha::start::START_SPEC
• sha::t_length::T_LENGTH_SPEC
• sha::t_string::T_STRING_SPEC
• slc::RegisterBlock
• slc::slc0_len_conf::SLC0_LEN_CONF_SPEC
• slc::slc0_length::SLC0_LENGTH_SPEC
• slc::slc0_rx_sharemem_end::SLC0_RX_SHAREMEM_END_SPEC
• slc::slc0_rx_sharemem_start::SLC0_RX_SHAREMEM_START_SPEC
• slc::slc0_tx_sharemem_end::SLC0_TX_SHAREMEM_END_SPEC
• slc::slc0_tx_sharemem_start::SLC0_TX_SHAREMEM_START_SPEC
• slc::slc0int_clr::SLC0INT_CLR_SPEC
• slc::slc0int_ena::SLC0INT_ENA_SPEC
• slc::slc0int_raw::SLC0INT_RAW_SPEC
• slc::slc0int_st::SLC0INT_ST_SPEC
• slc::slc0rx_link::SLC0RX_LINK_SPEC
• slc::slc0rx_link_addr::SLC0RX_LINK_ADDR_SPEC
• slc::slc0token1::SLC0TOKEN1_SPEC
• slc::slc0tx_link::SLC0TX_LINK_SPEC
• slc::slc0tx_link_addr::SLC0TX_LINK_ADDR_SPEC
• slc::slc1_rx_sharemem_end::SLC1_RX_SHAREMEM_END_SPEC
• slc::slc1_rx_sharemem_start::SLC1_RX_SHAREMEM_START_SPEC
• slc::slc1_tx_sharemem_end::SLC1_TX_SHAREMEM_END_SPEC
• slc::slc1_tx_sharemem_start::SLC1_TX_SHAREMEM_START_SPEC
• slc::slc1int_clr::SLC1INT_CLR_SPEC
• slc::slc1int_ena1::SLC1INT_ENA1_SPEC
• slc::slc1int_raw::SLC1INT_RAW_SPEC
• slc::slc1int_st1::SLC1INT_ST1_SPEC
• slc::slc1rx_link::SLC1RX_LINK_SPEC
• slc::slc1rx_link_addr::SLC1RX_LINK_ADDR_SPEC
• slc::slc1token1::SLC1TOKEN1_SPEC
• slc::slc1tx_link::SLC1TX_LINK_SPEC
• slc::slc1tx_link_addr::SLC1TX_LINK_ADDR_SPEC
• slc::slc_burst_len::SLC_BURST_LEN_SPEC
• slc::slc_rx_dscr_conf::SLC_RX_DSCR_CONF_SPEC
• slc::slcconf0::SLCCONF0_SPEC
• slc::slcconf1::SLCCONF1_SPEC
• slc::slcintvec_tohost::SLCINTVEC_TOHOST_SPEC
• slchost::RegisterBlock
• slchost::check_sum0::CHECK_SUM0_SPEC
• slchost::check_sum1::CHECK_SUM1_SPEC
• slchost::conf::CONF_SPEC
• slchost::conf_w0::CONF_W0_SPEC
• slchost::conf_w10::CONF_W10_SPEC
• slchost::conf_w11::CONF_W11_SPEC
• slchost::conf_w12::CONF_W12_SPEC
• slchost::conf_w13::CONF_W13_SPEC
• slchost::conf_w14::CONF_W14_SPEC
• slchost::conf_w15::CONF_W15_SPEC
• slchost::conf_w1::CONF_W1_SPEC
• slchost::conf_w2::CONF_W2_SPEC
• slchost::conf_w3::CONF_W3_SPEC
• slchost::conf_w4::CONF_W4_SPEC
• slchost::conf_w5::CONF_W5_SPEC
• slchost::conf_w6::CONF_W6_SPEC
• slchost::conf_w7::CONF_W7_SPEC
• slchost::conf_w8::CONF_W8_SPEC
• slchost::conf_w9::CONF_W9_SPEC
• slchost::func2_0::FUNC2_0_SPEC
• slchost::func2_1::FUNC2_1_SPEC
• slchost::func2_2::FUNC2_2_SPEC
• slchost::gpio_in0::GPIO_IN0_SPEC
• slchost::gpio_in1::GPIO_IN1_SPEC
• slchost::gpio_status0::GPIO_STATUS0_SPEC
• slchost::gpio_status1::GPIO_STATUS1_SPEC
• slchost::inf_st::INF_ST_SPEC
• slchost::pkt_len0::PKT_LEN0_SPEC
• slchost::pkt_len1::PKT_LEN1_SPEC
• slchost::pkt_len2::PKT_LEN2_SPEC
• slchost::pkt_len::PKT_LEN_SPEC
• slchost::rdclr0::RDCLR0_SPEC
• slchost::rdclr1::RDCLR1_SPEC
• slchost::slc0_host_pf::SLC0_HOST_PF_SPEC
• slchost::slc0host_func1_int_ena::SLC0HOST_FUNC1_INT_ENA_SPEC
• slchost::slc0host_func2_int_ena::SLC0HOST_FUNC2_INT_ENA_SPEC
• slchost::slc0host_int_clr::SLC0HOST_INT_CLR_SPEC
• slchost::slc0host_int_ena1::SLC0HOST_INT_ENA1_SPEC
• slchost::slc0host_int_ena::SLC0HOST_INT_ENA_SPEC
• slchost::slc0host_int_raw::SLC0HOST_INT_RAW_SPEC
• slchost::slc0host_int_st::SLC0HOST_INT_ST_SPEC
• slchost::slc0host_len_wd::SLC0HOST_LEN_WD_SPEC
• slchost::slc0host_rx_infor::SLC0HOST_RX_INFOR_SPEC
• slchost::slc0host_token_rdata::SLC0HOST_TOKEN_RDATA_SPEC
• slchost::slc0host_token_wdata::SLC0HOST_TOKEN_WDATA_SPEC
• slchost::slc1_host_pf::SLC1_HOST_PF_SPEC
• slchost::slc1host_func1_int_ena::SLC1HOST_FUNC1_INT_ENA_SPEC
• slchost::slc1host_func2_int_ena::SLC1HOST_FUNC2_INT_ENA_SPEC
• slchost::slc1host_int_clr::SLC1HOST_INT_CLR_SPEC
• slchost::slc1host_int_ena1::SLC1HOST_INT_ENA1_SPEC
• slchost::slc1host_int_ena::SLC1HOST_INT_ENA_SPEC
• slchost::slc1host_int_raw::SLC1HOST_INT_RAW_SPEC
• slchost::slc1host_int_st::SLC1HOST_INT_ST_SPEC
• slchost::slc1host_rx_infor::SLC1HOST_RX_INFOR_SPEC
• slchost::slc1host_token_rdata::SLC1HOST_TOKEN_RDATA_SPEC
• slchost::slc1host_token_wdata::SLC1HOST_TOKEN_WDATA_SPEC
• slchost::slc_apbwin_conf::SLC_APBWIN_CONF_SPEC
• slchost::slc_apbwin_rdata::SLC_APBWIN_RDATA_SPEC
• slchost::slc_apbwin_wdata::SLC_APBWIN_WDATA_SPEC
• slchost::slchostdate::SLCHOSTDATE_SPEC
• slchost::slchostid::SLCHOSTID_SPEC
• slchost::state_w0::STATE_W0_SPEC
• slchost::state_w1::STATE_W1_SPEC
• slchost::token_con::TOKEN_CON_SPEC
• slchost::win_cmd::WIN_CMD_SPEC
• soc_etm::RegisterBlock
• soc_etm::ch::CH
• soc_etm::ch::evt_id::EVT_ID_SPEC
• soc_etm::ch::task_id::TASK_ID_SPEC
• soc_etm::ch_ena_ad0::CH_ENA_AD0_SPEC
• soc_etm::ch_ena_ad0_clr::CH_ENA_AD0_CLR_SPEC
• soc_etm::ch_ena_ad0_set::CH_ENA_AD0_SET_SPEC
• soc_etm::ch_ena_ad1::CH_ENA_AD1_SPEC
• soc_etm::ch_ena_ad1_clr::CH_ENA_AD1_CLR_SPEC
• soc_etm::ch_ena_ad1_set::CH_ENA_AD1_SET_SPEC
• soc_etm::clk_en::CLK_EN_SPEC
• soc_etm::date::DATE_SPEC
• spi0::RegisterBlock
• spi0::axi_err_addr::AXI_ERR_ADDR_SPEC
• spi0::cache_fctrl::CACHE_FCTRL_SPEC
• spi0::cache_sctrl::CACHE_SCTRL_SPEC
• spi0::clock::CLOCK_SPEC
• spi0::clock_gate::CLOCK_GATE_SPEC
• spi0::cmd::CMD_SPEC
• spi0::ctrl1::CTRL1_SPEC
• spi0::ctrl2::CTRL2_SPEC
• spi0::ctrl::CTRL_SPEC
• spi0::date::DATE_SPEC
• spi0::ddr::DDR_SPEC
• spi0::din_mode::DIN_MODE_SPEC
• spi0::din_num::DIN_NUM_SPEC
• spi0::dout_mode::DOUT_MODE_SPEC
• spi0::dpa_ctrl::DPA_CTRL_SPEC
• spi0::ecc_ctrl::ECC_CTRL_SPEC
• spi0::ecc_err_addr::ECC_ERR_ADDR_SPEC
• spi0::fsm::FSM_SPEC
• spi0::int_clr::INT_CLR_SPEC
• spi0::int_ena::INT_ENA_SPEC
• spi0::int_raw::INT_RAW_SPEC
• spi0::int_st::INT_ST_SPEC
• spi0::misc::MISC_SPEC
• spi0::mmu_item_content::MMU_ITEM_CONTENT_SPEC
• spi0::mmu_item_index::MMU_ITEM_INDEX_SPEC
• spi0::mmu_power_ctrl::MMU_POWER_CTRL_SPEC
• spi0::pms_reject::PMS_REJECT_SPEC
• spi0::rd_status::RD_STATUS_SPEC
• spi0::registerrnd_eco_high::REGISTERRND_ECO_HIGH_SPEC
• spi0::registerrnd_eco_low::REGISTERRND_ECO_LOW_SPEC
• spi0::spi_fmem_pms_addr::SPI_FMEM_PMS_ADDR_SPEC
• spi0::spi_fmem_pms_attr::SPI_FMEM_PMS_ATTR_SPEC
• spi0::spi_fmem_pms_size::SPI_FMEM_PMS_SIZE_SPEC
• spi0::spi_smem_ac::SPI_SMEM_AC_SPEC
• spi0::spi_smem_ddr::SPI_SMEM_DDR_SPEC
• spi0::spi_smem_din_mode::SPI_SMEM_DIN_MODE_SPEC
• spi0::spi_smem_din_num::SPI_SMEM_DIN_NUM_SPEC
• spi0::spi_smem_dout_mode::SPI_SMEM_DOUT_MODE_SPEC
• spi0::spi_smem_ecc_ctrl::SPI_SMEM_ECC_CTRL_SPEC
• spi0::spi_smem_pms_addr::SPI_SMEM_PMS_ADDR_SPEC
• spi0::spi_smem_pms_attr::SPI_SMEM_PMS_ATTR_SPEC
• spi0::spi_smem_pms_size::SPI_SMEM_PMS_SIZE_SPEC
• spi0::spi_smem_timing_cali::SPI_SMEM_TIMING_CALI_SPEC
• spi0::sram_clk::SRAM_CLK_SPEC
• spi0::sram_cmd::SRAM_CMD_SPEC
• spi0::sram_drd_cmd::SRAM_DRD_CMD_SPEC
• spi0::sram_dwr_cmd::SRAM_DWR_CMD_SPEC
• spi0::timing_cali::TIMING_CALI_SPEC
• spi0::user1::USER1_SPEC
• spi0::user2::USER2_SPEC
• spi0::user::USER_SPEC
• spi0::xts_date::XTS_DATE_SPEC
• spi0::xts_destination::XTS_DESTINATION_SPEC
• spi0::xts_destroy::XTS_DESTROY_SPEC
• spi0::xts_linesize::XTS_LINESIZE_SPEC
• spi0::xts_physical_address::XTS_PHYSICAL_ADDRESS_SPEC
• spi0::xts_plain_base::XTS_PLAIN_BASE_SPEC
• spi0::xts_release::XTS_RELEASE_SPEC
• spi0::xts_state::XTS_STATE_SPEC
• spi0::xts_trigger::XTS_TRIGGER_SPEC
• spi1::RegisterBlock
• spi1::addr::ADDR_SPEC
• spi1::cache_fctrl::CACHE_FCTRL_SPEC
• spi1::clock::CLOCK_SPEC
• spi1::clock_gate::CLOCK_GATE_SPEC
• spi1::cmd::CMD_SPEC
• spi1::ctrl1::CTRL1_SPEC
• spi1::ctrl2::CTRL2_SPEC
• spi1::ctrl::CTRL_SPEC
• spi1::date::DATE_SPEC
• spi1::ddr::DDR_SPEC
• spi1::flash_sus_cmd::FLASH_SUS_CMD_SPEC
• spi1::flash_sus_ctrl::FLASH_SUS_CTRL_SPEC
• spi1::flash_waiti_ctrl::FLASH_WAITI_CTRL_SPEC
• spi1::int_clr::INT_CLR_SPEC
• spi1::int_ena::INT_ENA_SPEC
• spi1::int_raw::INT_RAW_SPEC
• spi1::int_st::INT_ST_SPEC
• spi1::misc::MISC_SPEC
• spi1::miso_dlen::MISO_DLEN_SPEC
• spi1::mosi_dlen::MOSI_DLEN_SPEC
• spi1::rd_status::RD_STATUS_SPEC
• spi1::sus_status::SUS_STATUS_SPEC
• spi1::timing_cali::TIMING_CALI_SPEC
• spi1::tx_crc::TX_CRC_SPEC
• spi1::user1::USER1_SPEC
• spi1::user2::USER2_SPEC
• spi1::user::USER_SPEC
• spi1::w::W_SPEC
• spi2::RegisterBlock
• spi2::addr::ADDR_SPEC
• spi2::clk_gate::CLK_GATE_SPEC
• spi2::clock::CLOCK_SPEC
• spi2::cmd::CMD_SPEC
• spi2::ctrl::CTRL_SPEC
• spi2::date::DATE_SPEC
• spi2::din_mode::DIN_MODE_SPEC
• spi2::din_num::DIN_NUM_SPEC
• spi2::dma_conf::DMA_CONF_SPEC
• spi2::dma_int_clr::DMA_INT_CLR_SPEC
• spi2::dma_int_ena::DMA_INT_ENA_SPEC
• spi2::dma_int_raw::DMA_INT_RAW_SPEC
• spi2::dma_int_set::DMA_INT_SET_SPEC
• spi2::dma_int_st::DMA_INT_ST_SPEC
• spi2::dout_mode::DOUT_MODE_SPEC
• spi2::misc::MISC_SPEC
• spi2::ms_dlen::MS_DLEN_SPEC
• spi2::slave1::SLAVE1_SPEC
• spi2::slave::SLAVE_SPEC
• spi2::user1::USER1_SPEC
• spi2::user2::USER2_SPEC
• spi2::user::USER_SPEC
• spi2::w::W_SPEC
• systimer::RegisterBlock
• systimer::comp_load::COMP_LOAD_SPEC
• systimer::conf::CONF_SPEC
• systimer::date::DATE_SPEC
• systimer::int_clr::INT_CLR_SPEC
• systimer::int_ena::INT_ENA_SPEC
• systimer::int_raw::INT_RAW_SPEC
• systimer::int_st::INT_ST_SPEC
• systimer::real_target::REAL_TARGET
• systimer::real_target::hi::HI_SPEC
• systimer::real_target::lo::LO_SPEC
• systimer::target_conf::TARGET_CONF_SPEC
• systimer::trgt::TRGT
• systimer::trgt::hi::HI_SPEC
• systimer::trgt::lo::LO_SPEC
• systimer::unit_load::UNIT_LOAD_SPEC
• systimer::unit_op::UNIT_OP_SPEC
• systimer::unit_value::UNIT_VALUE
• systimer::unit_value::hi::HI_SPEC
• systimer::unit_value::lo::LO_SPEC
• systimer::unitload::UNITLOAD
• systimer::unitload::hi::HI_SPEC
• systimer::unitload::lo::LO_SPEC
• tee::RegisterBlock
• tee::clock_gate::CLOCK_GATE_SPEC
• tee::date::DATE_SPEC
• tee::m_mode_ctrl::M_MODE_CTRL_SPEC
• timg0::RegisterBlock
• timg0::int_clr::INT_CLR_SPEC
• timg0::int_ena::INT_ENA_SPEC
• timg0::int_raw::INT_RAW_SPEC
• timg0::int_st::INT_ST_SPEC
• timg0::ntimers_date::NTIMERS_DATE_SPEC
• timg0::regclk::REGCLK_SPEC
• timg0::rtccalicfg1::RTCCALICFG1_SPEC
• timg0::rtccalicfg2::RTCCALICFG2_SPEC
• timg0::rtccalicfg::RTCCALICFG_SPEC
• timg0::t::T
• timg0::t::alarmhi::ALARMHI_SPEC
• timg0::t::alarmlo::ALARMLO_SPEC
• timg0::t::config::CONFIG_SPEC
• timg0::t::hi::HI_SPEC
• timg0::t::lo::LO_SPEC
• timg0::t::load::LOAD_SPEC
• timg0::t::loadhi::LOADHI_SPEC
• timg0::t::loadlo::LOADLO_SPEC
• timg0::t::update::UPDATE_SPEC
• timg0::wdtconfig0::WDTCONFIG0_SPEC
• timg0::wdtconfig1::WDTCONFIG1_SPEC
• timg0::wdtconfig2::WDTCONFIG2_SPEC
• timg0::wdtconfig3::WDTCONFIG3_SPEC
• timg0::wdtconfig4::WDTCONFIG4_SPEC
• timg0::wdtconfig5::WDTCONFIG5_SPEC
• timg0::wdtfeed::WDTFEED_SPEC
• timg0::wdtwprotect::WDTWPROTECT_SPEC
• trace::RegisterBlock
• trace::clock_gate::CLOCK_GATE_SPEC
• trace::date::DATE_SPEC
• trace::fifo_status::FIFO_STATUS_SPEC
• trace::intr_clr::INTR_CLR_SPEC
• trace::intr_ena::INTR_ENA_SPEC
• trace::intr_raw::INTR_RAW_SPEC
• trace::mem_addr_update::MEM_ADDR_UPDATE_SPEC
• trace::mem_current_addr::MEM_CURRENT_ADDR_SPEC
• trace::mem_end_addr::MEM_END_ADDR_SPEC
• trace::mem_start_addr::MEM_START_ADDR_SPEC
• trace::resync_prolonged::RESYNC_PROLONGED_SPEC
• trace::trigger::TRIGGER_SPEC
• twai0::RegisterBlock
• twai0::arb_lost_cap::ARB_LOST_CAP_SPEC
• twai0::bus_timing_0::BUS_TIMING_0_SPEC
• twai0::bus_timing_1::BUS_TIMING_1_SPEC
• twai0::clock_divider::CLOCK_DIVIDER_SPEC
• twai0::cmd::CMD_SPEC
• twai0::data_0::DATA_0_SPEC
• twai0::data_10::DATA_10_SPEC
• twai0::data_11::DATA_11_SPEC
• twai0::data_12::DATA_12_SPEC
• twai0::data_1::DATA_1_SPEC
• twai0::data_2::DATA_2_SPEC
• twai0::data_3::DATA_3_SPEC
• twai0::data_4::DATA_4_SPEC
• twai0::data_5::DATA_5_SPEC
• twai0::data_6::DATA_6_SPEC
• twai0::data_7::DATA_7_SPEC
• twai0::data_8::DATA_8_SPEC
• twai0::data_9::DATA_9_SPEC
• twai0::eco_cfg::ECO_CFG_SPEC
• twai0::err_code_cap::ERR_CODE_CAP_SPEC
• twai0::err_warning_limit::ERR_WARNING_LIMIT_SPEC
• twai0::hw_cfg::HW_CFG_SPEC
• twai0::hw_standby_cnt::HW_STANDBY_CNT_SPEC
• twai0::idle_intr_cnt::IDLE_INTR_CNT_SPEC
• twai0::interrupt::INTERRUPT_SPEC
• twai0::interrupt_enable::INTERRUPT_ENABLE_SPEC
• twai0::mode::MODE_SPEC
• twai0::rx_err_cnt::RX_ERR_CNT_SPEC
• twai0::rx_message_cnt::RX_MESSAGE_CNT_SPEC
• twai0::status::STATUS_SPEC
• twai0::sw_standby_cfg::SW_STANDBY_CFG_SPEC
• twai0::tx_err_cnt::TX_ERR_CNT_SPEC
• uart0::RegisterBlock
• uart0::afifo_status::AFIFO_STATUS_SPEC
• uart0::at_cmd_char::AT_CMD_CHAR_SPEC
• uart0::at_cmd_gaptout::AT_CMD_GAPTOUT_SPEC
• uart0::at_cmd_postcnt::AT_CMD_POSTCNT_SPEC
• uart0::at_cmd_precnt::AT_CMD_PRECNT_SPEC
• uart0::clk_conf::CLK_CONF_SPEC
• uart0::clkdiv::CLKDIV_SPEC
• uart0::conf0::CONF0_SPEC
• uart0::conf1::CONF1_SPEC
• uart0::date::DATE_SPEC
• uart0::fifo::FIFO_SPEC
• uart0::fsm_status::FSM_STATUS_SPEC
• uart0::highpulse::HIGHPULSE_SPEC
• uart0::hwfc_conf::HWFC_CONF_SPEC
• uart0::id::ID_SPEC
• uart0::idle_conf::IDLE_CONF_SPEC
• uart0::int_clr::INT_CLR_SPEC
• uart0::int_ena::INT_ENA_SPEC
• uart0::int_raw::INT_RAW_SPEC
• uart0::int_st::INT_ST_SPEC
• uart0::lowpulse::LOWPULSE_SPEC
• uart0::mem_conf::MEM_CONF_SPEC
• uart0::mem_rx_status::MEM_RX_STATUS_SPEC
• uart0::mem_tx_status::MEM_TX_STATUS_SPEC
• uart0::negpulse::NEGPULSE_SPEC
• uart0::pospulse::POSPULSE_SPEC
• uart0::reg_update::REG_UPDATE_SPEC
• uart0::rs485_conf::RS485_CONF_SPEC
• uart0::rx_filt::RX_FILT_SPEC
• uart0::rxd_cnt::RXD_CNT_SPEC
• uart0::sleep_conf0::SLEEP_CONF0_SPEC
• uart0::sleep_conf1::SLEEP_CONF1_SPEC
• uart0::sleep_conf2::SLEEP_CONF2_SPEC
• uart0::status::STATUS_SPEC
• uart0::swfc_conf0::SWFC_CONF0_SPEC
• uart0::swfc_conf1::SWFC_CONF1_SPEC
• uart0::tout_conf::TOUT_CONF_SPEC
• uart0::txbrk_conf::TXBRK_CONF_SPEC
• uhci0::RegisterBlock
• uhci0::ack_num::ACK_NUM_SPEC
• uhci0::conf0::CONF0_SPEC
• uhci0::conf1::CONF1_SPEC
• uhci0::date::DATE_SPEC
• uhci0::esc_conf::ESC_CONF_SPEC
• uhci0::escape_conf::ESCAPE_CONF_SPEC
• uhci0::hung_conf::HUNG_CONF_SPEC
• uhci0::int_clr::INT_CLR_SPEC
• uhci0::int_ena::INT_ENA_SPEC
• uhci0::int_raw::INT_RAW_SPEC
• uhci0::int_st::INT_ST_SPEC
• uhci0::pkt_thres::PKT_THRES_SPEC
• uhci0::quick_sent::QUICK_SENT_SPEC
• uhci0::reg_q::REG_Q
• uhci0::reg_q::word0::WORD0_SPEC
• uhci0::reg_q::word1::WORD1_SPEC
• uhci0::rx_head::RX_HEAD_SPEC
• uhci0::state0::STATE0_SPEC
• uhci0::state1::STATE1_SPEC
• usb_device::RegisterBlock
• usb_device::bus_reset_st::BUS_RESET_ST_SPEC
• usb_device::chip_rst::CHIP_RST_SPEC
• usb_device::conf0::CONF0_SPEC
• usb_device::config_update::CONFIG_UPDATE_SPEC
• usb_device::date::DATE_SPEC
• usb_device::ep1::EP1_SPEC
• usb_device::ep1_conf::EP1_CONF_SPEC
• usb_device::fram_num::FRAM_NUM_SPEC
• usb_device::get_line_code_w0::GET_LINE_CODE_W0_SPEC
• usb_device::get_line_code_w1::GET_LINE_CODE_W1_SPEC
• usb_device::in_ep0_st::IN_EP0_ST_SPEC
• usb_device::in_ep1_st::IN_EP1_ST_SPEC
• usb_device::in_ep2_st::IN_EP2_ST_SPEC
• usb_device::in_ep3_st::IN_EP3_ST_SPEC
• usb_device::int_clr::INT_CLR_SPEC
• usb_device::int_ena::INT_ENA_SPEC
• usb_device::int_raw::INT_RAW_SPEC
• usb_device::int_st::INT_ST_SPEC
• usb_device::jfifo_st::JFIFO_ST_SPEC
• usb_device::mem_conf::MEM_CONF_SPEC
• usb_device::misc_conf::MISC_CONF_SPEC
• usb_device::out_ep0_st::OUT_EP0_ST_SPEC
• usb_device::out_ep1_st::OUT_EP1_ST_SPEC
• usb_device::out_ep2_st::OUT_EP2_ST_SPEC
• usb_device::ser_afifo_config::SER_AFIFO_CONFIG_SPEC
• usb_device::set_line_code_w0::SET_LINE_CODE_W0_SPEC
• usb_device::set_line_code_w1::SET_LINE_CODE_W1_SPEC
• usb_device::test::TEST_SPEC

Enums

• Interrupt
• i2c0::comd::OPCODE
• lp_tee::m_mode_ctrl::SECURITY_MODE
• pcnt::unit::conf0::CTRL_MODE
• pcnt::unit::conf0::EDGE_MODE
• tee::m_mode_ctrl::SECURITY_MODE

Traits

• generic::FieldSpec
• generic::IsEnum
• generic::RawReg
• generic::Readable
• generic::RegisterSpec
• generic::Resettable
• generic::Writable

Type Aliases

• aes::AAD_BLOCK_NUM
• aes::BLOCK_MODE
• aes::BLOCK_NUM
• aes::CONTINUE
• aes::DATE
• aes::DMA_ENABLE
• aes::DMA_EXIT
• aes::ENDIAN
• aes::H_MEM
• aes::INC_SEL
• aes::INT_CLR
• aes::INT_ENA
• aes::IV_MEM
• aes::J0_MEM
• aes::KEY
• aes::MODE
• aes::REMAINDER_BIT_NUM
• aes::STATE
• aes::T0_MEM
• aes::TEXT_IN
• aes::TEXT_OUT
• aes::TRIGGER
• aes::aad_block_num::AAD_BLOCK_NUM_R
• aes::aad_block_num::AAD_BLOCK_NUM_W
• aes::aad_block_num::R
• aes::aad_block_num::W
• aes::block_mode::BLOCK_MODE_R
• aes::block_mode::BLOCK_MODE_W
• aes::block_mode::R
• aes::block_mode::W
• aes::block_num::BLOCK_NUM_R
• aes::block_num::BLOCK_NUM_W
• aes::block_num::R
• aes::block_num::W
• aes::continue_::CONTINUE_W
• aes::continue_::W
• aes::date::DATE_R
• aes::date::DATE_W
• aes::date::R
• aes::date::W
• aes::dma_enable::DMA_ENABLE_R
• aes::dma_enable::DMA_ENABLE_W
• aes::dma_enable::R
• aes::dma_enable::W
• aes::dma_exit::DMA_EXIT_W
• aes::dma_exit::W
• aes::endian::ENDIAN_R
• aes::endian::ENDIAN_W
• aes::endian::R
• aes::endian::W
• aes::h_mem::R
• aes::h_mem::W
• aes::inc_sel::INC_SEL_R
• aes::inc_sel::INC_SEL_W
• aes::inc_sel::R
• aes::inc_sel::W
• aes::int_clr::INT_CLR_W
• aes::int_clr::W
• aes::int_ena::INT_ENA_R
• aes::int_ena::INT_ENA_W
• aes::int_ena::R
• aes::int_ena::W
• aes::iv_mem::R
• aes::iv_mem::W
• aes::j0_mem::R
• aes::j0_mem::W
• aes::key::KEY_R
• aes::key::KEY_W
• aes::key::R
• aes::key::W
• aes::mode::MODE_R
• aes::mode::MODE_W
• aes::mode::R
• aes::mode::W
• aes::remainder_bit_num::R
• aes::remainder_bit_num::REMAINDER_BIT_NUM_R
• aes::remainder_bit_num::REMAINDER_BIT_NUM_W
• aes::remainder_bit_num::W
• aes::state::R
• aes::state::STATE_R
• aes::t0_mem::R
• aes::t0_mem::W
• aes::text_in::R
• aes::text_in::TEXT_IN_R
• aes::text_in::TEXT_IN_W
• aes::text_in::W
• aes::text_out::R
• aes::text_out::TEXT_OUT_R
• aes::text_out::TEXT_OUT_W
• aes::text_out::W
• aes::trigger::TRIGGER_W
• aes::trigger::W
• apb_saradc::ARB_CTRL
• apb_saradc::CALI
• apb_saradc::CLKM_CONF
• apb_saradc::CTRL
• apb_saradc::CTRL2
• apb_saradc::CTRL_DATE
• apb_saradc::DMA_CONF
• apb_saradc::FILTER_CTRL0
• apb_saradc::FILTER_CTRL1
• apb_saradc::FSM_WAIT
• apb_saradc::INT_CLR
• apb_saradc::INT_ENA
• apb_saradc::INT_RAW
• apb_saradc::INT_ST
• apb_saradc::ONETIME_SAMPLE
• apb_saradc::SAR1DATA_STATUS
• apb_saradc::SAR1_STATUS
• apb_saradc::SAR2DATA_STATUS
• apb_saradc::SAR2_STATUS
• apb_saradc::SAR_PATT_TAB1
• apb_saradc::SAR_PATT_TAB2
• apb_saradc::THRES0_CTRL
• apb_saradc::THRES1_CTRL
• apb_saradc::THRES_CTRL
• apb_saradc::TSENS_CTRL
• apb_saradc::TSENS_CTRL2
• apb_saradc::TSENS_SAMPLE
• apb_saradc::TSENS_WAKE
• apb_saradc::arb_ctrl::APB_FORCE_R
• apb_saradc::arb_ctrl::APB_FORCE_W
• apb_saradc::arb_ctrl::APB_PRIORITY_R
• apb_saradc::arb_ctrl::APB_PRIORITY_W
• apb_saradc::arb_ctrl::FIX_PRIORITY_R
• apb_saradc::arb_ctrl::FIX_PRIORITY_W
• apb_saradc::arb_ctrl::GRANT_FORCE_R
• apb_saradc::arb_ctrl::GRANT_FORCE_W
• apb_saradc::arb_ctrl::R
• apb_saradc::arb_ctrl::RTC_FORCE_R
• apb_saradc::arb_ctrl::RTC_FORCE_W
• apb_saradc::arb_ctrl::RTC_PRIORITY_R
• apb_saradc::arb_ctrl::RTC_PRIORITY_W
• apb_saradc::arb_ctrl::W
• apb_saradc::arb_ctrl::WIFI_FORCE_R
• apb_saradc::arb_ctrl::WIFI_FORCE_W
• apb_saradc::arb_ctrl::WIFI_PRIORITY_R
• apb_saradc::arb_ctrl::WIFI_PRIORITY_W
• apb_saradc::cali::CFG_R
• apb_saradc::cali::CFG_W
• apb_saradc::cali::R
• apb_saradc::cali::W
• apb_saradc::clkm_conf::CLKM_DIV_A_R
• apb_saradc::clkm_conf::CLKM_DIV_A_W
• apb_saradc::clkm_conf::CLKM_DIV_B_R
• apb_saradc::clkm_conf::CLKM_DIV_B_W
• apb_saradc::clkm_conf::CLKM_DIV_NUM_R
• apb_saradc::clkm_conf::CLKM_DIV_NUM_W
• apb_saradc::clkm_conf::CLK_EN_R
• apb_saradc::clkm_conf::CLK_EN_W
• apb_saradc::clkm_conf::CLK_SEL_R
• apb_saradc::clkm_conf::CLK_SEL_W
• apb_saradc::clkm_conf::R
• apb_saradc::clkm_conf::W
• apb_saradc::ctrl2::MAX_MEAS_NUM_R
• apb_saradc::ctrl2::MAX_MEAS_NUM_W
• apb_saradc::ctrl2::MEAS_NUM_LIMIT_R
• apb_saradc::ctrl2::MEAS_NUM_LIMIT_W
• apb_saradc::ctrl2::R
• apb_saradc::ctrl2::SAR1_INV_R
• apb_saradc::ctrl2::SAR1_INV_W
• apb_saradc::ctrl2::SAR2_INV_R
• apb_saradc::ctrl2::SAR2_INV_W
• apb_saradc::ctrl2::TIMER_EN_R
• apb_saradc::ctrl2::TIMER_EN_W
• apb_saradc::ctrl2::TIMER_TARGET_R
• apb_saradc::ctrl2::TIMER_TARGET_W
• apb_saradc::ctrl2::W
• apb_saradc::ctrl::R
• apb_saradc::ctrl::SARADC2_PWDET_DRV_R
• apb_saradc::ctrl::SARADC2_PWDET_DRV_W
• apb_saradc::ctrl::SAR_CLK_DIV_R
• apb_saradc::ctrl::SAR_CLK_DIV_W
• apb_saradc::ctrl::SAR_CLK_GATED_R
• apb_saradc::ctrl::SAR_CLK_GATED_W
• apb_saradc::ctrl::SAR_PATT_LEN_R
• apb_saradc::ctrl::SAR_PATT_LEN_W
• apb_saradc::ctrl::SAR_PATT_P_CLEAR_R
• apb_saradc::ctrl::SAR_PATT_P_CLEAR_W
• apb_saradc::ctrl::START_FORCE_R
• apb_saradc::ctrl::START_FORCE_W
• apb_saradc::ctrl::START_R
• apb_saradc::ctrl::START_W
• apb_saradc::ctrl::W
• apb_saradc::ctrl::WAIT_ARB_CYCLE_R
• apb_saradc::ctrl::WAIT_ARB_CYCLE_W
• apb_saradc::ctrl::XPD_SAR_FORCE_R
• apb_saradc::ctrl::XPD_SAR_FORCE_W
• apb_saradc::ctrl_date::DATE_R
• apb_saradc::ctrl_date::DATE_W
• apb_saradc::ctrl_date::R
• apb_saradc::ctrl_date::W
• apb_saradc::dma_conf::ADC_EOF_NUM_R
• apb_saradc::dma_conf::ADC_EOF_NUM_W
• apb_saradc::dma_conf::ADC_RESET_FSM_R
• apb_saradc::dma_conf::ADC_RESET_FSM_W
• apb_saradc::dma_conf::ADC_TRANS_R
• apb_saradc::dma_conf::ADC_TRANS_W
• apb_saradc::dma_conf::R
• apb_saradc::dma_conf::W
• apb_saradc::filter_ctrl0::FILTER_CHANNEL0_R
• apb_saradc::filter_ctrl0::FILTER_CHANNEL0_W
• apb_saradc::filter_ctrl0::FILTER_CHANNEL1_R
• apb_saradc::filter_ctrl0::FILTER_CHANNEL1_W
• apb_saradc::filter_ctrl0::FILTER_RESET_R
• apb_saradc::filter_ctrl0::FILTER_RESET_W
• apb_saradc::filter_ctrl0::R
• apb_saradc::filter_ctrl0::W
• apb_saradc::filter_ctrl1::FILTER_FACTOR0_R
• apb_saradc::filter_ctrl1::FILTER_FACTOR0_W
• apb_saradc::filter_ctrl1::FILTER_FACTOR1_R
• apb_saradc::filter_ctrl1::FILTER_FACTOR1_W
• apb_saradc::filter_ctrl1::R
• apb_saradc::filter_ctrl1::W
• apb_saradc::fsm_wait::R
• apb_saradc::fsm_wait::RSTB_WAIT_R
• apb_saradc::fsm_wait::RSTB_WAIT_W
• apb_saradc::fsm_wait::STANDBY_WAIT_R
• apb_saradc::fsm_wait::STANDBY_WAIT_W
• apb_saradc::fsm_wait::W
• apb_saradc::fsm_wait::XPD_WAIT_R
• apb_saradc::fsm_wait::XPD_WAIT_W
• apb_saradc::int_clr::ADC1_DONE_W
• apb_saradc::int_clr::ADC2_DONE_W
• apb_saradc::int_clr::THRES0_HIGH_W
• apb_saradc::int_clr::THRES0_LOW_W
• apb_saradc::int_clr::THRES1_HIGH_W
• apb_saradc::int_clr::THRES1_LOW_W
• apb_saradc::int_clr::TSENS_W
• apb_saradc::int_clr::W
• apb_saradc::int_ena::ADC1_DONE_R
• apb_saradc::int_ena::ADC1_DONE_W
• apb_saradc::int_ena::ADC2_DONE_R
• apb_saradc::int_ena::ADC2_DONE_W
• apb_saradc::int_ena::R
• apb_saradc::int_ena::THRES0_HIGH_R
• apb_saradc::int_ena::THRES0_HIGH_W
• apb_saradc::int_ena::THRES0_LOW_R
• apb_saradc::int_ena::THRES0_LOW_W
• apb_saradc::int_ena::THRES1_HIGH_R
• apb_saradc::int_ena::THRES1_HIGH_W
• apb_saradc::int_ena::THRES1_LOW_R
• apb_saradc::int_ena::THRES1_LOW_W
• apb_saradc::int_ena::TSENS_R
• apb_saradc::int_ena::TSENS_W
• apb_saradc::int_ena::W
• apb_saradc::int_raw::ADC1_DONE_R
• apb_saradc::int_raw::ADC1_DONE_W
• apb_saradc::int_raw::ADC2_DONE_R
• apb_saradc::int_raw::ADC2_DONE_W
• apb_saradc::int_raw::R
• apb_saradc::int_raw::THRES0_HIGH_R
• apb_saradc::int_raw::THRES0_HIGH_W
• apb_saradc::int_raw::THRES0_LOW_R
• apb_saradc::int_raw::THRES0_LOW_W
• apb_saradc::int_raw::THRES1_HIGH_R
• apb_saradc::int_raw::THRES1_HIGH_W
• apb_saradc::int_raw::THRES1_LOW_R
• apb_saradc::int_raw::THRES1_LOW_W
• apb_saradc::int_raw::TSENS_R
• apb_saradc::int_raw::TSENS_W
• apb_saradc::int_raw::W
• apb_saradc::int_st::ADC1_DONE_R
• apb_saradc::int_st::ADC2_DONE_R
• apb_saradc::int_st::R
• apb_saradc::int_st::THRES0_HIGH_R
• apb_saradc::int_st::THRES0_LOW_R
• apb_saradc::int_st::THRES1_HIGH_R
• apb_saradc::int_st::THRES1_LOW_R
• apb_saradc::int_st::TSENS_R
• apb_saradc::onetime_sample::ONETIME_ATTEN_R
• apb_saradc::onetime_sample::ONETIME_ATTEN_W
• apb_saradc::onetime_sample::ONETIME_CHANNEL_R
• apb_saradc::onetime_sample::ONETIME_CHANNEL_W
• apb_saradc::onetime_sample::ONETIME_START_R
• apb_saradc::onetime_sample::ONETIME_START_W
• apb_saradc::onetime_sample::R
• apb_saradc::onetime_sample::SARADC1_ONETIME_SAMPLE_R
• apb_saradc::onetime_sample::SARADC1_ONETIME_SAMPLE_W
• apb_saradc::onetime_sample::SARADC2_ONETIME_SAMPLE_R
• apb_saradc::onetime_sample::SARADC2_ONETIME_SAMPLE_W
• apb_saradc::onetime_sample::W
• apb_saradc::sar1_status::R
• apb_saradc::sar1_status::SAR1_STATUS_R
• apb_saradc::sar1data_status::R
• apb_saradc::sar1data_status::SARADC1_DATA_R
• apb_saradc::sar2_status::R
• apb_saradc::sar2_status::SAR2_STATUS_R
• apb_saradc::sar2data_status::R
• apb_saradc::sar2data_status::SARADC2_DATA_R
• apb_saradc::sar_patt_tab1::R
• apb_saradc::sar_patt_tab1::SAR_PATT_TAB1_R
• apb_saradc::sar_patt_tab1::SAR_PATT_TAB1_W
• apb_saradc::sar_patt_tab1::W
• apb_saradc::sar_patt_tab2::R
• apb_saradc::sar_patt_tab2::SAR_PATT_TAB2_R
• apb_saradc::sar_patt_tab2::SAR_PATT_TAB2_W
• apb_saradc::sar_patt_tab2::W
• apb_saradc::thres0_ctrl::R
• apb_saradc::thres0_ctrl::THRES0_CHANNEL_R
• apb_saradc::thres0_ctrl::THRES0_CHANNEL_W
• apb_saradc::thres0_ctrl::THRES0_HIGH_R
• apb_saradc::thres0_ctrl::THRES0_HIGH_W
• apb_saradc::thres0_ctrl::THRES0_LOW_R
• apb_saradc::thres0_ctrl::THRES0_LOW_W
• apb_saradc::thres0_ctrl::W
• apb_saradc::thres1_ctrl::R
• apb_saradc::thres1_ctrl::THRES1_CHANNEL_R
• apb_saradc::thres1_ctrl::THRES1_CHANNEL_W
• apb_saradc::thres1_ctrl::THRES1_HIGH_R
• apb_saradc::thres1_ctrl::THRES1_HIGH_W
• apb_saradc::thres1_ctrl::THRES1_LOW_R
• apb_saradc::thres1_ctrl::THRES1_LOW_W
• apb_saradc::thres1_ctrl::W
• apb_saradc::thres_ctrl::R
• apb_saradc::thres_ctrl::THRES0_EN_R
• apb_saradc::thres_ctrl::THRES0_EN_W
• apb_saradc::thres_ctrl::THRES1_EN_R
• apb_saradc::thres_ctrl::THRES1_EN_W
• apb_saradc::thres_ctrl::THRES_ALL_EN_R
• apb_saradc::thres_ctrl::THRES_ALL_EN_W
• apb_saradc::thres_ctrl::W
• apb_saradc::tsens_ctrl2::CLK_INV_R
• apb_saradc::tsens_ctrl2::CLK_INV_W
• apb_saradc::tsens_ctrl2::CLK_SEL_R
• apb_saradc::tsens_ctrl2::CLK_SEL_W
• apb_saradc::tsens_ctrl2::R
• apb_saradc::tsens_ctrl2::W
• apb_saradc::tsens_ctrl2::XPD_FORCE_R
• apb_saradc::tsens_ctrl2::XPD_FORCE_W
• apb_saradc::tsens_ctrl2::XPD_WAIT_R
• apb_saradc::tsens_ctrl2::XPD_WAIT_W
• apb_saradc::tsens_ctrl::CLK_DIV_R
• apb_saradc::tsens_ctrl::CLK_DIV_W
• apb_saradc::tsens_ctrl::IN_INV_R
• apb_saradc::tsens_ctrl::IN_INV_W
• apb_saradc::tsens_ctrl::OUT_R
• apb_saradc::tsens_ctrl::PU_R
• apb_saradc::tsens_ctrl::PU_W
• apb_saradc::tsens_ctrl::R
• apb_saradc::tsens_ctrl::W
• apb_saradc::tsens_sample::EN_R
• apb_saradc::tsens_sample::EN_W
• apb_saradc::tsens_sample::R
• apb_saradc::tsens_sample::RATE_R
• apb_saradc::tsens_sample::RATE_W
• apb_saradc::tsens_sample::W
• apb_saradc::tsens_wake::R
• apb_saradc::tsens_wake::W
• apb_saradc::tsens_wake::WAKEUP_EN_R
• apb_saradc::tsens_wake::WAKEUP_EN_W
• apb_saradc::tsens_wake::WAKEUP_MODE_R
• apb_saradc::tsens_wake::WAKEUP_MODE_W
• apb_saradc::tsens_wake::WAKEUP_OVER_UPPER_TH_R
• apb_saradc::tsens_wake::WAKEUP_TH_HIGH_R
• apb_saradc::tsens_wake::WAKEUP_TH_HIGH_W
• apb_saradc::tsens_wake::WAKEUP_TH_LOW_R
• apb_saradc::tsens_wake::WAKEUP_TH_LOW_W
• assist_debug::CLOCK_GATE
• assist_debug::CORE_0_AREA_DRAM0_0_MAX
• assist_debug::CORE_0_AREA_DRAM0_0_MIN
• assist_debug::CORE_0_AREA_DRAM0_1_MAX
• assist_debug::CORE_0_AREA_DRAM0_1_MIN
• assist_debug::CORE_0_AREA_PC
• assist_debug::CORE_0_AREA_PIF_0_MAX
• assist_debug::CORE_0_AREA_PIF_0_MIN
• assist_debug::CORE_0_AREA_PIF_1_MAX
• assist_debug::CORE_0_AREA_PIF_1_MIN
• assist_debug::CORE_0_AREA_SP
• assist_debug::CORE_0_DEBUG_MODE
• assist_debug::CORE_0_DRAM0_EXCEPTION_MONITOR_0
• assist_debug::CORE_0_DRAM0_EXCEPTION_MONITOR_1
• assist_debug::CORE_0_DRAM0_EXCEPTION_MONITOR_2
• assist_debug::CORE_0_DRAM0_EXCEPTION_MONITOR_3
• assist_debug::CORE_0_INTR_CLR
• assist_debug::CORE_0_INTR_ENA
• assist_debug::CORE_0_INTR_RAW
• assist_debug::CORE_0_IRAM0_EXCEPTION_MONITOR_0
• assist_debug::CORE_0_IRAM0_EXCEPTION_MONITOR_1
• assist_debug::CORE_0_LASTPC_BEFORE_EXCEPTION
• assist_debug::CORE_0_MONTR_ENA
• assist_debug::CORE_0_RCD_EN
• assist_debug::CORE_0_RCD_PDEBUGPC
• assist_debug::CORE_0_RCD_PDEBUGSP
• assist_debug::CORE_0_SP_MAX
• assist_debug::CORE_0_SP_MIN
• assist_debug::CORE_0_SP_PC
• assist_debug::CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0
• assist_debug::CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1
• assist_debug::DATE
• assist_debug::clock_gate::CLK_EN_R
• assist_debug::clock_gate::CLK_EN_W
• assist_debug::clock_gate::R
• assist_debug::clock_gate::W
• assist_debug::core_0_area_dram0_0_max::CORE_0_AREA_DRAM0_0_MAX_R
• assist_debug::core_0_area_dram0_0_max::CORE_0_AREA_DRAM0_0_MAX_W
• assist_debug::core_0_area_dram0_0_max::R
• assist_debug::core_0_area_dram0_0_max::W
• assist_debug::core_0_area_dram0_0_min::CORE_0_AREA_DRAM0_0_MIN_R
• assist_debug::core_0_area_dram0_0_min::CORE_0_AREA_DRAM0_0_MIN_W
• assist_debug::core_0_area_dram0_0_min::R
• assist_debug::core_0_area_dram0_0_min::W
• assist_debug::core_0_area_dram0_1_max::CORE_0_AREA_DRAM0_1_MAX_R
• assist_debug::core_0_area_dram0_1_max::CORE_0_AREA_DRAM0_1_MAX_W
• assist_debug::core_0_area_dram0_1_max::R
• assist_debug::core_0_area_dram0_1_max::W
• assist_debug::core_0_area_dram0_1_min::CORE_0_AREA_DRAM0_1_MIN_R
• assist_debug::core_0_area_dram0_1_min::CORE_0_AREA_DRAM0_1_MIN_W
• assist_debug::core_0_area_dram0_1_min::R
• assist_debug::core_0_area_dram0_1_min::W
• assist_debug::core_0_area_pc::CORE_0_AREA_PC_R
• assist_debug::core_0_area_pc::R
• assist_debug::core_0_area_pif_0_max::CORE_0_AREA_PIF_0_MAX_R
• assist_debug::core_0_area_pif_0_max::CORE_0_AREA_PIF_0_MAX_W
• assist_debug::core_0_area_pif_0_max::R
• assist_debug::core_0_area_pif_0_max::W
• assist_debug::core_0_area_pif_0_min::CORE_0_AREA_PIF_0_MIN_R
• assist_debug::core_0_area_pif_0_min::CORE_0_AREA_PIF_0_MIN_W
• assist_debug::core_0_area_pif_0_min::R
• assist_debug::core_0_area_pif_0_min::W
• assist_debug::core_0_area_pif_1_max::CORE_0_AREA_PIF_1_MAX_R
• assist_debug::core_0_area_pif_1_max::CORE_0_AREA_PIF_1_MAX_W
• assist_debug::core_0_area_pif_1_max::R
• assist_debug::core_0_area_pif_1_max::W
• assist_debug::core_0_area_pif_1_min::CORE_0_AREA_PIF_1_MIN_R
• assist_debug::core_0_area_pif_1_min::CORE_0_AREA_PIF_1_MIN_W
• assist_debug::core_0_area_pif_1_min::R
• assist_debug::core_0_area_pif_1_min::W
• assist_debug::core_0_area_sp::CORE_0_AREA_SP_R
• assist_debug::core_0_area_sp::R
• assist_debug::core_0_debug_mode::CORE_0_DEBUG_MODE_R
• assist_debug::core_0_debug_mode::CORE_0_DEBUG_MODULE_ACTIVE_R
• assist_debug::core_0_debug_mode::R
• assist_debug::core_0_dram0_exception_monitor_0::CORE_0_DRAM0_RECORDING_ADDR_0_R
• assist_debug::core_0_dram0_exception_monitor_0::CORE_0_DRAM0_RECORDING_BYTEEN_0_R
• assist_debug::core_0_dram0_exception_monitor_0::CORE_0_DRAM0_RECORDING_WR_0_R
• assist_debug::core_0_dram0_exception_monitor_0::R
• assist_debug::core_0_dram0_exception_monitor_1::CORE_0_DRAM0_RECORDING_PC_0_R
• assist_debug::core_0_dram0_exception_monitor_1::R
• assist_debug::core_0_dram0_exception_monitor_2::CORE_0_DRAM0_RECORDING_ADDR_1_R
• assist_debug::core_0_dram0_exception_monitor_2::CORE_0_DRAM0_RECORDING_BYTEEN_1_R
• assist_debug::core_0_dram0_exception_monitor_2::CORE_0_DRAM0_RECORDING_WR_1_R
• assist_debug::core_0_dram0_exception_monitor_2::R
• assist_debug::core_0_dram0_exception_monitor_3::CORE_0_DRAM0_RECORDING_PC_1_R
• assist_debug::core_0_dram0_exception_monitor_3::R
• assist_debug::core_0_intr_clr::CORE_0_AREA_DRAM0_0_RD_CLR_W
• assist_debug::core_0_intr_clr::CORE_0_AREA_DRAM0_0_WR_CLR_W
• assist_debug::core_0_intr_clr::CORE_0_AREA_DRAM0_1_RD_CLR_W
• assist_debug::core_0_intr_clr::CORE_0_AREA_DRAM0_1_WR_CLR_W
• assist_debug::core_0_intr_clr::CORE_0_AREA_PIF_0_RD_CLR_W
• assist_debug::core_0_intr_clr::CORE_0_AREA_PIF_0_WR_CLR_W
• assist_debug::core_0_intr_clr::CORE_0_AREA_PIF_1_RD_CLR_W
• assist_debug::core_0_intr_clr::CORE_0_AREA_PIF_1_WR_CLR_W
• assist_debug::core_0_intr_clr::CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_W
• assist_debug::core_0_intr_clr::CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_W
• assist_debug::core_0_intr_clr::CORE_0_SP_SPILL_MAX_CLR_W
• assist_debug::core_0_intr_clr::CORE_0_SP_SPILL_MIN_CLR_W
• assist_debug::core_0_intr_clr::W
• assist_debug::core_0_intr_ena::CORE_0_AREA_DRAM0_0_RD_INTR_ENA_R
• assist_debug::core_0_intr_ena::CORE_0_AREA_DRAM0_0_RD_INTR_ENA_W
• assist_debug::core_0_intr_ena::CORE_0_AREA_DRAM0_0_WR_INTR_ENA_R
• assist_debug::core_0_intr_ena::CORE_0_AREA_DRAM0_0_WR_INTR_ENA_W
• assist_debug::core_0_intr_ena::CORE_0_AREA_DRAM0_1_RD_INTR_ENA_R
• assist_debug::core_0_intr_ena::CORE_0_AREA_DRAM0_1_RD_INTR_ENA_W
• assist_debug::core_0_intr_ena::CORE_0_AREA_DRAM0_1_WR_INTR_ENA_R
• assist_debug::core_0_intr_ena::CORE_0_AREA_DRAM0_1_WR_INTR_ENA_W
• assist_debug::core_0_intr_ena::CORE_0_AREA_PIF_0_RD_INTR_ENA_R
• assist_debug::core_0_intr_ena::CORE_0_AREA_PIF_0_RD_INTR_ENA_W
• assist_debug::core_0_intr_ena::CORE_0_AREA_PIF_0_WR_INTR_ENA_R
• assist_debug::core_0_intr_ena::CORE_0_AREA_PIF_0_WR_INTR_ENA_W
• assist_debug::core_0_intr_ena::CORE_0_AREA_PIF_1_RD_INTR_ENA_R
• assist_debug::core_0_intr_ena::CORE_0_AREA_PIF_1_RD_INTR_ENA_W
• assist_debug::core_0_intr_ena::CORE_0_AREA_PIF_1_WR_INTR_ENA_R
• assist_debug::core_0_intr_ena::CORE_0_AREA_PIF_1_WR_INTR_ENA_W
• assist_debug::core_0_intr_ena::CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_R
• assist_debug::core_0_intr_ena::CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_W
• assist_debug::core_0_intr_ena::CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_R
• assist_debug::core_0_intr_ena::CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_W
• assist_debug::core_0_intr_ena::CORE_0_SP_SPILL_MAX_INTR_ENA_R
• assist_debug::core_0_intr_ena::CORE_0_SP_SPILL_MAX_INTR_ENA_W
• assist_debug::core_0_intr_ena::CORE_0_SP_SPILL_MIN_INTR_ENA_R
• assist_debug::core_0_intr_ena::CORE_0_SP_SPILL_MIN_INTR_ENA_W
• assist_debug::core_0_intr_ena::R
• assist_debug::core_0_intr_ena::W
• assist_debug::core_0_intr_raw::CORE_0_AREA_DRAM0_0_RD_RAW_R
• assist_debug::core_0_intr_raw::CORE_0_AREA_DRAM0_0_WR_RAW_R
• assist_debug::core_0_intr_raw::CORE_0_AREA_DRAM0_1_RD_RAW_R
• assist_debug::core_0_intr_raw::CORE_0_AREA_DRAM0_1_WR_RAW_R
• assist_debug::core_0_intr_raw::CORE_0_AREA_PIF_0_RD_RAW_R
• assist_debug::core_0_intr_raw::CORE_0_AREA_PIF_0_WR_RAW_R
• assist_debug::core_0_intr_raw::CORE_0_AREA_PIF_1_RD_RAW_R
• assist_debug::core_0_intr_raw::CORE_0_AREA_PIF_1_WR_RAW_R
• assist_debug::core_0_intr_raw::CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_R
• assist_debug::core_0_intr_raw::CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_R
• assist_debug::core_0_intr_raw::CORE_0_SP_SPILL_MAX_RAW_R
• assist_debug::core_0_intr_raw::CORE_0_SP_SPILL_MIN_RAW_R
• assist_debug::core_0_intr_raw::R
• assist_debug::core_0_iram0_exception_monitor_0::CORE_0_IRAM0_RECORDING_ADDR_0_R
• assist_debug::core_0_iram0_exception_monitor_0::CORE_0_IRAM0_RECORDING_LOADSTORE_0_R
• assist_debug::core_0_iram0_exception_monitor_0::CORE_0_IRAM0_RECORDING_WR_0_R
• assist_debug::core_0_iram0_exception_monitor_0::R
• assist_debug::core_0_iram0_exception_monitor_1::CORE_0_IRAM0_RECORDING_ADDR_1_R
• assist_debug::core_0_iram0_exception_monitor_1::CORE_0_IRAM0_RECORDING_LOADSTORE_1_R
• assist_debug::core_0_iram0_exception_monitor_1::CORE_0_IRAM0_RECORDING_WR_1_R
• assist_debug::core_0_iram0_exception_monitor_1::R
• assist_debug::core_0_lastpc_before_exception::CORE_0_LASTPC_BEFORE_EXC_R
• assist_debug::core_0_lastpc_before_exception::R
• assist_debug::core_0_montr_ena::CORE_0_AREA_DRAM0_0_RD_ENA_R
• assist_debug::core_0_montr_ena::CORE_0_AREA_DRAM0_0_RD_ENA_W
• assist_debug::core_0_montr_ena::CORE_0_AREA_DRAM0_0_WR_ENA_R
• assist_debug::core_0_montr_ena::CORE_0_AREA_DRAM0_0_WR_ENA_W
• assist_debug::core_0_montr_ena::CORE_0_AREA_DRAM0_1_RD_ENA_R
• assist_debug::core_0_montr_ena::CORE_0_AREA_DRAM0_1_RD_ENA_W
• assist_debug::core_0_montr_ena::CORE_0_AREA_DRAM0_1_WR_ENA_R
• assist_debug::core_0_montr_ena::CORE_0_AREA_DRAM0_1_WR_ENA_W
• assist_debug::core_0_montr_ena::CORE_0_AREA_PIF_0_RD_ENA_R
• assist_debug::core_0_montr_ena::CORE_0_AREA_PIF_0_RD_ENA_W
• assist_debug::core_0_montr_ena::CORE_0_AREA_PIF_0_WR_ENA_R
• assist_debug::core_0_montr_ena::CORE_0_AREA_PIF_0_WR_ENA_W
• assist_debug::core_0_montr_ena::CORE_0_AREA_PIF_1_RD_ENA_R
• assist_debug::core_0_montr_ena::CORE_0_AREA_PIF_1_RD_ENA_W
• assist_debug::core_0_montr_ena::CORE_0_AREA_PIF_1_WR_ENA_R
• assist_debug::core_0_montr_ena::CORE_0_AREA_PIF_1_WR_ENA_W
• assist_debug::core_0_montr_ena::CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_R
• assist_debug::core_0_montr_ena::CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_W
• assist_debug::core_0_montr_ena::CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_R
• assist_debug::core_0_montr_ena::CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_W
• assist_debug::core_0_montr_ena::CORE_0_SP_SPILL_MAX_ENA_R
• assist_debug::core_0_montr_ena::CORE_0_SP_SPILL_MAX_ENA_W
• assist_debug::core_0_montr_ena::CORE_0_SP_SPILL_MIN_ENA_R
• assist_debug::core_0_montr_ena::CORE_0_SP_SPILL_MIN_ENA_W
• assist_debug::core_0_montr_ena::R
• assist_debug::core_0_montr_ena::W
• assist_debug::core_0_rcd_en::CORE_0_RCD_PDEBUGEN_R
• assist_debug::core_0_rcd_en::CORE_0_RCD_PDEBUGEN_W
• assist_debug::core_0_rcd_en::CORE_0_RCD_RECORDEN_R
• assist_debug::core_0_rcd_en::CORE_0_RCD_RECORDEN_W
• assist_debug::core_0_rcd_en::R
• assist_debug::core_0_rcd_en::W
• assist_debug::core_0_rcd_pdebugpc::CORE_0_RCD_PDEBUGPC_R
• assist_debug::core_0_rcd_pdebugpc::R
• assist_debug::core_0_rcd_pdebugsp::CORE_0_RCD_PDEBUGSP_R
• assist_debug::core_0_rcd_pdebugsp::R
• assist_debug::core_0_sp_max::CORE_0_SP_MAX_R
• assist_debug::core_0_sp_max::CORE_0_SP_MAX_W
• assist_debug::core_0_sp_max::R
• assist_debug::core_0_sp_max::W
• assist_debug::core_0_sp_min::CORE_0_SP_MIN_R
• assist_debug::core_0_sp_min::CORE_0_SP_MIN_W
• assist_debug::core_0_sp_min::R
• assist_debug::core_0_sp_min::W
• assist_debug::core_0_sp_pc::CORE_0_SP_PC_R
• assist_debug::core_0_sp_pc::R
• assist_debug::core_x_iram0_dram0_exception_monitor_0::CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_R
• assist_debug::core_x_iram0_dram0_exception_monitor_0::CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_W
• assist_debug::core_x_iram0_dram0_exception_monitor_0::R
• assist_debug::core_x_iram0_dram0_exception_monitor_0::W
• assist_debug::core_x_iram0_dram0_exception_monitor_1::CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_R
• assist_debug::core_x_iram0_dram0_exception_monitor_1::CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_W
• assist_debug::core_x_iram0_dram0_exception_monitor_1::R
• assist_debug::core_x_iram0_dram0_exception_monitor_1::W
• assist_debug::date::ASSIST_DEBUG_DATE_R
• assist_debug::date::ASSIST_DEBUG_DATE_W
• assist_debug::date::R
• assist_debug::date::W
• atomic::ADDR_LOCK
• atomic::COUNTER
• atomic::LOCK_STATUS
• atomic::LR_ADDR
• atomic::LR_VALUE
• atomic::addr_lock::LOCK_R
• atomic::addr_lock::LOCK_W
• atomic::addr_lock::R
• atomic::addr_lock::W
• atomic::counter::R
• atomic::counter::W
• atomic::counter::WAIT_COUNTER_R
• atomic::counter::WAIT_COUNTER_W
• atomic::lock_status::LOCK_STATUS_R
• atomic::lock_status::R
• atomic::lr_addr::GLOABLE_LR_ADDR_R
• atomic::lr_addr::GLOABLE_LR_ADDR_W
• atomic::lr_addr::R
• atomic::lr_addr::W
• atomic::lr_value::GLOABLE_LR_VALUE_R
• atomic::lr_value::GLOABLE_LR_VALUE_W
• atomic::lr_value::R
• atomic::lr_value::W
• clint::MSIP
• clint::MTIME
• clint::MTIMECMP
• clint::MTIMECTL
• clint::USIP
• clint::UTIME
• clint::UTIMECMP
• clint::UTIMECTL
• clint::msip::MSIP_R
• clint::msip::MSIP_W
• clint::msip::R
• clint::msip::W
• clint::mtime::MTIME_R
• clint::mtime::MTIME_W
• clint::mtime::R
• clint::mtime::W
• clint::mtimecmp::MTIMECMP_R
• clint::mtimecmp::MTIMECMP_W
• clint::mtimecmp::R
• clint::mtimecmp::W
• clint::mtimectl::MTCE_R
• clint::mtimectl::MTCE_W
• clint::mtimectl::MTIE_R
• clint::mtimectl::MTIE_W
• clint::mtimectl::MTIP_R
• clint::mtimectl::MTOF_R
• clint::mtimectl::MTOF_W
• clint::mtimectl::R
• clint::mtimectl::W
• clint::usip::R
• clint::usip::USIP_R
• clint::usip::USIP_W
• clint::usip::W
• clint::utime::R
• clint::utime::UTIME_R
• clint::utimecmp::R
• clint::utimecmp::UTIMECMP_R
• clint::utimecmp::UTIMECMP_W
• clint::utimecmp::W
• clint::utimectl::R
• clint::utimectl::UTIE_R
• clint::utimectl::UTIE_W
• clint::utimectl::UTIP_R
• clint::utimectl::UTOF_R
• clint::utimectl::UTOF_W
• clint::utimectl::W
• dma::AHB_TEST
• dma::DATE
• dma::MISC_CONF
• dma::ahb_test::AHB_TESTADDR_R
• dma::ahb_test::AHB_TESTADDR_W
• dma::ahb_test::AHB_TESTMODE_R
• dma::ahb_test::AHB_TESTMODE_W
• dma::ahb_test::R
• dma::ahb_test::W
• dma::ch::INFIFO_STATUS
• dma::ch::IN_CONF0
• dma::ch::IN_CONF1
• dma::ch::IN_DSCR
• dma::ch::IN_DSCR_BF0
• dma::ch::IN_DSCR_BF1
• dma::ch::IN_ERR_EOF_DES_ADDR
• dma::ch::IN_LINK
• dma::ch::IN_PERI_SEL
• dma::ch::IN_POP
• dma::ch::IN_PRI
• dma::ch::IN_STATE
• dma::ch::IN_SUC_EOF_DES_ADDR
• dma::ch::OUTFIFO_STATUS
• dma::ch::OUT_CONF0
• dma::ch::OUT_CONF1
• dma::ch::OUT_DSCR
• dma::ch::OUT_DSCR_BF0
• dma::ch::OUT_DSCR_BF1
• dma::ch::OUT_EOF_BFR_DES_ADDR
• dma::ch::OUT_EOF_DES_ADDR
• dma::ch::OUT_LINK
• dma::ch::OUT_PERI_SEL
• dma::ch::OUT_PRI
• dma::ch::OUT_PUSH
• dma::ch::OUT_STATE
• dma::ch::in_conf0::INDSCR_BURST_EN_R
• dma::ch::in_conf0::INDSCR_BURST_EN_W
• dma::ch::in_conf0::IN_DATA_BURST_EN_R
• dma::ch::in_conf0::IN_DATA_BURST_EN_W
• dma::ch::in_conf0::IN_ETM_EN_R
• dma::ch::in_conf0::IN_ETM_EN_W
• dma::ch::in_conf0::IN_LOOP_TEST_R
• dma::ch::in_conf0::IN_LOOP_TEST_W
• dma::ch::in_conf0::IN_RST_R
• dma::ch::in_conf0::IN_RST_W
• dma::ch::in_conf0::MEM_TRANS_EN_R
• dma::ch::in_conf0::MEM_TRANS_EN_W
• dma::ch::in_conf0::R
• dma::ch::in_conf0::W
• dma::ch::in_conf1::IN_CHECK_OWNER_R
• dma::ch::in_conf1::IN_CHECK_OWNER_W
• dma::ch::in_conf1::R
• dma::ch::in_conf1::W
• dma::ch::in_dscr::INLINK_DSCR_R
• dma::ch::in_dscr::R
• dma::ch::in_dscr_bf0::INLINK_DSCR_BF0_R
• dma::ch::in_dscr_bf0::R
• dma::ch::in_dscr_bf1::INLINK_DSCR_BF1_R
• dma::ch::in_dscr_bf1::R
• dma::ch::in_err_eof_des_addr::IN_ERR_EOF_DES_ADDR_R
• dma::ch::in_err_eof_des_addr::R
• dma::ch::in_link::INLINK_ADDR_R
• dma::ch::in_link::INLINK_ADDR_W
• dma::ch::in_link::INLINK_AUTO_RET_R
• dma::ch::in_link::INLINK_AUTO_RET_W
• dma::ch::in_link::INLINK_PARK_R
• dma::ch::in_link::INLINK_RESTART_W
• dma::ch::in_link::INLINK_START_W
• dma::ch::in_link::INLINK_STOP_W
• dma::ch::in_link::R
• dma::ch::in_link::W
• dma::ch::in_peri_sel::PERI_IN_SEL_R
• dma::ch::in_peri_sel::PERI_IN_SEL_W
• dma::ch::in_peri_sel::R
• dma::ch::in_peri_sel::W
• dma::ch::in_pop::INFIFO_POP_W
• dma::ch::in_pop::INFIFO_RDATA_R
• dma::ch::in_pop::R
• dma::ch::in_pop::W
• dma::ch::in_pri::R
• dma::ch::in_pri::RX_PRI_R
• dma::ch::in_pri::RX_PRI_W
• dma::ch::in_pri::W
• dma::ch::in_state::INLINK_DSCR_ADDR_R
• dma::ch::in_state::IN_DSCR_STATE_R
• dma::ch::in_state::IN_STATE_R
• dma::ch::in_state::R
• dma::ch::in_suc_eof_des_addr::IN_SUC_EOF_DES_ADDR_R
• dma::ch::in_suc_eof_des_addr::R
• dma::ch::infifo_status::INFIFO_CNT_R
• dma::ch::infifo_status::INFIFO_EMPTY_R
• dma::ch::infifo_status::INFIFO_FULL_R
• dma::ch::infifo_status::IN_BUF_HUNGRY_R
• dma::ch::infifo_status::IN_REMAIN_UNDER_1B_R
• dma::ch::infifo_status::IN_REMAIN_UNDER_2B_R
• dma::ch::infifo_status::IN_REMAIN_UNDER_3B_R
• dma::ch::infifo_status::IN_REMAIN_UNDER_4B_R
• dma::ch::infifo_status::R
• dma::ch::out_conf0::OUTDSCR_BURST_EN_R
• dma::ch::out_conf0::OUTDSCR_BURST_EN_W
• dma::ch::out_conf0::OUT_AUTO_WRBACK_R
• dma::ch::out_conf0::OUT_AUTO_WRBACK_W
• dma::ch::out_conf0::OUT_DATA_BURST_EN_R
• dma::ch::out_conf0::OUT_DATA_BURST_EN_W
• dma::ch::out_conf0::OUT_EOF_MODE_R
• dma::ch::out_conf0::OUT_EOF_MODE_W
• dma::ch::out_conf0::OUT_ETM_EN_R
• dma::ch::out_conf0::OUT_ETM_EN_W
• dma::ch::out_conf0::OUT_LOOP_TEST_R
• dma::ch::out_conf0::OUT_LOOP_TEST_W
• dma::ch::out_conf0::OUT_RST_R
• dma::ch::out_conf0::OUT_RST_W
• dma::ch::out_conf0::R
• dma::ch::out_conf0::W
• dma::ch::out_conf1::OUT_CHECK_OWNER_R
• dma::ch::out_conf1::OUT_CHECK_OWNER_W
• dma::ch::out_conf1::R
• dma::ch::out_conf1::W
• dma::ch::out_dscr::OUTLINK_DSCR_R
• dma::ch::out_dscr::R
• dma::ch::out_dscr_bf0::OUTLINK_DSCR_BF0_R
• dma::ch::out_dscr_bf0::R
• dma::ch::out_dscr_bf1::OUTLINK_DSCR_BF1_R
• dma::ch::out_dscr_bf1::R
• dma::ch::out_eof_bfr_des_addr::OUT_EOF_BFR_DES_ADDR_R
• dma::ch::out_eof_bfr_des_addr::R
• dma::ch::out_eof_des_addr::OUT_EOF_DES_ADDR_R
• dma::ch::out_eof_des_addr::R
• dma::ch::out_link::OUTLINK_ADDR_R
• dma::ch::out_link::OUTLINK_ADDR_W
• dma::ch::out_link::OUTLINK_PARK_R
• dma::ch::out_link::OUTLINK_RESTART_W
• dma::ch::out_link::OUTLINK_START_W
• dma::ch::out_link::OUTLINK_STOP_W
• dma::ch::out_link::R
• dma::ch::out_link::W
• dma::ch::out_peri_sel::PERI_OUT_SEL_R
• dma::ch::out_peri_sel::PERI_OUT_SEL_W
• dma::ch::out_peri_sel::R
• dma::ch::out_peri_sel::W
• dma::ch::out_pri::R
• dma::ch::out_pri::TX_PRI_R
• dma::ch::out_pri::TX_PRI_W
• dma::ch::out_pri::W
• dma::ch::out_push::OUTFIFO_PUSH_W
• dma::ch::out_push::OUTFIFO_WDATA_R
• dma::ch::out_push::OUTFIFO_WDATA_W
• dma::ch::out_push::R
• dma::ch::out_push::W
• dma::ch::out_state::OUTLINK_DSCR_ADDR_R
• dma::ch::out_state::OUT_DSCR_STATE_R
• dma::ch::out_state::OUT_STATE_R
• dma::ch::out_state::R
• dma::ch::outfifo_status::OUTFIFO_CNT_R
• dma::ch::outfifo_status::OUTFIFO_EMPTY_R
• dma::ch::outfifo_status::OUTFIFO_FULL_R
• dma::ch::outfifo_status::OUT_REMAIN_UNDER_1B_R
• dma::ch::outfifo_status::OUT_REMAIN_UNDER_2B_R
• dma::ch::outfifo_status::OUT_REMAIN_UNDER_3B_R
• dma::ch::outfifo_status::OUT_REMAIN_UNDER_4B_R
• dma::ch::outfifo_status::R
• dma::date::DATE_R
• dma::date::DATE_W
• dma::date::R
• dma::date::W
• dma::in_int_ch::CLR
• dma::in_int_ch::ENA
• dma::in_int_ch::RAW
• dma::in_int_ch::ST
• dma::in_int_ch::clr::INFIFO_OVF_W
• dma::in_int_ch::clr::INFIFO_UDF_W
• dma::in_int_ch::clr::IN_DONE_W
• dma::in_int_ch::clr::IN_DSCR_EMPTY_W
• dma::in_int_ch::clr::IN_DSCR_ERR_W
• dma::in_int_ch::clr::IN_ERR_EOF_W
• dma::in_int_ch::clr::IN_SUC_EOF_W
• dma::in_int_ch::clr::W
• dma::in_int_ch::ena::INFIFO_OVF_R
• dma::in_int_ch::ena::INFIFO_OVF_W
• dma::in_int_ch::ena::INFIFO_UDF_R
• dma::in_int_ch::ena::INFIFO_UDF_W
• dma::in_int_ch::ena::IN_DONE_R
• dma::in_int_ch::ena::IN_DONE_W
• dma::in_int_ch::ena::IN_DSCR_EMPTY_R
• dma::in_int_ch::ena::IN_DSCR_EMPTY_W
• dma::in_int_ch::ena::IN_DSCR_ERR_R
• dma::in_int_ch::ena::IN_DSCR_ERR_W
• dma::in_int_ch::ena::IN_ERR_EOF_R
• dma::in_int_ch::ena::IN_ERR_EOF_W
• dma::in_int_ch::ena::IN_SUC_EOF_R
• dma::in_int_ch::ena::IN_SUC_EOF_W
• dma::in_int_ch::ena::R
• dma::in_int_ch::ena::W
• dma::in_int_ch::raw::INFIFO_OVF_R
• dma::in_int_ch::raw::INFIFO_OVF_W
• dma::in_int_ch::raw::INFIFO_UDF_R
• dma::in_int_ch::raw::INFIFO_UDF_W
• dma::in_int_ch::raw::IN_DONE_R
• dma::in_int_ch::raw::IN_DONE_W
• dma::in_int_ch::raw::IN_DSCR_EMPTY_R
• dma::in_int_ch::raw::IN_DSCR_EMPTY_W
• dma::in_int_ch::raw::IN_DSCR_ERR_R
• dma::in_int_ch::raw::IN_DSCR_ERR_W
• dma::in_int_ch::raw::IN_ERR_EOF_R
• dma::in_int_ch::raw::IN_ERR_EOF_W
• dma::in_int_ch::raw::IN_SUC_EOF_R
• dma::in_int_ch::raw::IN_SUC_EOF_W
• dma::in_int_ch::raw::R
• dma::in_int_ch::raw::W
• dma::in_int_ch::st::INFIFO_OVF_R
• dma::in_int_ch::st::INFIFO_UDF_R
• dma::in_int_ch::st::IN_DONE_R
• dma::in_int_ch::st::IN_DSCR_EMPTY_R
• dma::in_int_ch::st::IN_DSCR_ERR_R
• dma::in_int_ch::st::IN_ERR_EOF_R
• dma::in_int_ch::st::IN_SUC_EOF_R
• dma::in_int_ch::st::R
• dma::misc_conf::AHBM_RST_INTER_R
• dma::misc_conf::AHBM_RST_INTER_W
• dma::misc_conf::ARB_PRI_DIS_R
• dma::misc_conf::ARB_PRI_DIS_W
• dma::misc_conf::CLK_EN_R
• dma::misc_conf::CLK_EN_W
• dma::misc_conf::R
• dma::misc_conf::W
• dma::out_int_ch::CLR
• dma::out_int_ch::ENA
• dma::out_int_ch::RAW
• dma::out_int_ch::ST
• dma::out_int_ch::clr::OUTFIFO_OVF_W
• dma::out_int_ch::clr::OUTFIFO_UDF_W
• dma::out_int_ch::clr::OUT_DONE_W
• dma::out_int_ch::clr::OUT_DSCR_ERR_W
• dma::out_int_ch::clr::OUT_EOF_W
• dma::out_int_ch::clr::OUT_TOTAL_EOF_W
• dma::out_int_ch::clr::W
• dma::out_int_ch::ena::OUTFIFO_OVF_R
• dma::out_int_ch::ena::OUTFIFO_OVF_W
• dma::out_int_ch::ena::OUTFIFO_UDF_R
• dma::out_int_ch::ena::OUTFIFO_UDF_W
• dma::out_int_ch::ena::OUT_DONE_R
• dma::out_int_ch::ena::OUT_DONE_W
• dma::out_int_ch::ena::OUT_DSCR_ERR_R
• dma::out_int_ch::ena::OUT_DSCR_ERR_W
• dma::out_int_ch::ena::OUT_EOF_R
• dma::out_int_ch::ena::OUT_EOF_W
• dma::out_int_ch::ena::OUT_TOTAL_EOF_R
• dma::out_int_ch::ena::OUT_TOTAL_EOF_W
• dma::out_int_ch::ena::R
• dma::out_int_ch::ena::W
• dma::out_int_ch::raw::OUTFIFO_OVF_R
• dma::out_int_ch::raw::OUTFIFO_OVF_W
• dma::out_int_ch::raw::OUTFIFO_UDF_R
• dma::out_int_ch::raw::OUTFIFO_UDF_W
• dma::out_int_ch::raw::OUT_DONE_R
• dma::out_int_ch::raw::OUT_DONE_W
• dma::out_int_ch::raw::OUT_DSCR_ERR_R
• dma::out_int_ch::raw::OUT_DSCR_ERR_W
• dma::out_int_ch::raw::OUT_EOF_R
• dma::out_int_ch::raw::OUT_EOF_W
• dma::out_int_ch::raw::OUT_TOTAL_EOF_R
• dma::out_int_ch::raw::OUT_TOTAL_EOF_W
• dma::out_int_ch::raw::R
• dma::out_int_ch::raw::W
• dma::out_int_ch::st::OUTFIFO_OVF_R
• dma::out_int_ch::st::OUTFIFO_UDF_R
• dma::out_int_ch::st::OUT_DONE_R
• dma::out_int_ch::st::OUT_DSCR_ERR_R
• dma::out_int_ch::st::OUT_EOF_R
• dma::out_int_ch::st::OUT_TOTAL_EOF_R
• dma::out_int_ch::st::R
• ds::BOX_MEM
• ds::DATE
• ds::IV_MEM
• ds::M_MEM
• ds::QUERY_BUSY
• ds::QUERY_CHECK
• ds::QUERY_KEY_WRONG
• ds::RB_MEM
• ds::SET_CONTINUE
• ds::SET_FINISH
• ds::SET_START
• ds::X_MEM
• ds::Y_MEM
• ds::Z_MEM
• ds::box_mem::R
• ds::box_mem::W
• ds::date::DATE_R
• ds::date::DATE_W
• ds::date::R
• ds::date::W
• ds::iv_mem::R
• ds::iv_mem::W
• ds::m_mem::R
• ds::m_mem::W
• ds::query_busy::QUERY_BUSY_R
• ds::query_busy::R
• ds::query_check::MD_ERROR_R
• ds::query_check::PADDING_BAD_R
• ds::query_check::R
• ds::query_key_wrong::QUERY_KEY_WRONG_R
• ds::query_key_wrong::R
• ds::rb_mem::R
• ds::rb_mem::W
• ds::set_continue::SET_CONTINUE_W
• ds::set_continue::W
• ds::set_finish::SET_FINISH_W
• ds::set_finish::W
• ds::set_start::SET_START_W
• ds::set_start::W
• ds::x_mem::R
• ds::x_mem::W
• ds::y_mem::R
• ds::y_mem::W
• ds::z_mem::R
• ds::z_mem::W
• ecc::K_MEM
• ecc::MULT_CONF
• ecc::MULT_DATE
• ecc::MULT_INT_CLR
• ecc::MULT_INT_ENA
• ecc::MULT_INT_RAW
• ecc::MULT_INT_ST
• ecc::PX_MEM
• ecc::PY_MEM
• ecc::k_mem::R
• ecc::k_mem::W
• ecc::mult_conf::CLK_EN_R
• ecc::mult_conf::CLK_EN_W
• ecc::mult_conf::KEY_LENGTH_R
• ecc::mult_conf::KEY_LENGTH_W
• ecc::mult_conf::MEM_CLOCK_GATE_FORCE_ON_R
• ecc::mult_conf::MEM_CLOCK_GATE_FORCE_ON_W
• ecc::mult_conf::R
• ecc::mult_conf::RESET_W
• ecc::mult_conf::SECURITY_MODE_R
• ecc::mult_conf::SECURITY_MODE_W
• ecc::mult_conf::START_R
• ecc::mult_conf::START_W
• ecc::mult_conf::VERIFICATION_RESULT_R
• ecc::mult_conf::W
• ecc::mult_conf::WORK_MODE_R
• ecc::mult_conf::WORK_MODE_W
• ecc::mult_date::DATE_R
• ecc::mult_date::DATE_W
• ecc::mult_date::R
• ecc::mult_date::W
• ecc::mult_int_clr::CALC_DONE_W
• ecc::mult_int_clr::W
• ecc::mult_int_ena::CALC_DONE_R
• ecc::mult_int_ena::CALC_DONE_W
• ecc::mult_int_ena::R
• ecc::mult_int_ena::W
• ecc::mult_int_raw::CALC_DONE_R
• ecc::mult_int_raw::R
• ecc::mult_int_st::CALC_DONE_R
• ecc::mult_int_st::R
• ecc::px_mem::R
• ecc::px_mem::W
• ecc::py_mem::R
• ecc::py_mem::W
• efuse::CLK
• efuse::CMD
• efuse::CONF
• efuse::DAC_CONF
• efuse::DATE
• efuse::INT_CLR
• efuse::INT_ENA
• efuse::INT_RAW
• efuse::INT_ST
• efuse::PGM_CHECK_VALUE0
• efuse::PGM_CHECK_VALUE1
• efuse::PGM_CHECK_VALUE2
• efuse::PGM_DATA0
• efuse::PGM_DATA1
• efuse::PGM_DATA2
• efuse::PGM_DATA3
• efuse::PGM_DATA4
• efuse::PGM_DATA5
• efuse::PGM_DATA6
• efuse::PGM_DATA7
• efuse::RD_KEY0_DATA0
• efuse::RD_KEY0_DATA1
• efuse::RD_KEY0_DATA2
• efuse::RD_KEY0_DATA3
• efuse::RD_KEY0_DATA4
• efuse::RD_KEY0_DATA5
• efuse::RD_KEY0_DATA6
• efuse::RD_KEY0_DATA7
• efuse::RD_KEY1_DATA0
• efuse::RD_KEY1_DATA1
• efuse::RD_KEY1_DATA2
• efuse::RD_KEY1_DATA3
• efuse::RD_KEY1_DATA4
• efuse::RD_KEY1_DATA5
• efuse::RD_KEY1_DATA6
• efuse::RD_KEY1_DATA7
• efuse::RD_KEY2_DATA0
• efuse::RD_KEY2_DATA1
• efuse::RD_KEY2_DATA2
• efuse::RD_KEY2_DATA3
• efuse::RD_KEY2_DATA4
• efuse::RD_KEY2_DATA5
• efuse::RD_KEY2_DATA6
• efuse::RD_KEY2_DATA7
• efuse::RD_KEY3_DATA0
• efuse::RD_KEY3_DATA1
• efuse::RD_KEY3_DATA2
• efuse::RD_KEY3_DATA3
• efuse::RD_KEY3_DATA4
• efuse::RD_KEY3_DATA5
• efuse::RD_KEY3_DATA6
• efuse::RD_KEY3_DATA7
• efuse::RD_KEY4_DATA0
• efuse::RD_KEY4_DATA1
• efuse::RD_KEY4_DATA2
• efuse::RD_KEY4_DATA3
• efuse::RD_KEY4_DATA4
• efuse::RD_KEY4_DATA5
• efuse::RD_KEY4_DATA6
• efuse::RD_KEY4_DATA7
• efuse::RD_KEY5_DATA0
• efuse::RD_KEY5_DATA1
• efuse::RD_KEY5_DATA2
• efuse::RD_KEY5_DATA3
• efuse::RD_KEY5_DATA4
• efuse::RD_KEY5_DATA5
• efuse::RD_KEY5_DATA6
• efuse::RD_KEY5_DATA7
• efuse::RD_MAC_SPI_SYS_0
• efuse::RD_MAC_SPI_SYS_1
• efuse::RD_MAC_SPI_SYS_2
• efuse::RD_MAC_SPI_SYS_3
• efuse::RD_MAC_SPI_SYS_4
• efuse::RD_MAC_SPI_SYS_5
• efuse::RD_REPEAT_DATA0
• efuse::RD_REPEAT_DATA1
• efuse::RD_REPEAT_DATA2
• efuse::RD_REPEAT_DATA3
• efuse::RD_REPEAT_DATA4
• efuse::RD_REPEAT_ERR0
• efuse::RD_REPEAT_ERR1
• efuse::RD_REPEAT_ERR2
• efuse::RD_REPEAT_ERR3
• efuse::RD_REPEAT_ERR4
• efuse::RD_RS_ERR0
• efuse::RD_RS_ERR1
• efuse::RD_SYS_PART1_DATA0
• efuse::RD_SYS_PART1_DATA1
• efuse::RD_SYS_PART1_DATA2
• efuse::RD_SYS_PART1_DATA3
• efuse::RD_SYS_PART1_DATA4
• efuse::RD_SYS_PART1_DATA5
• efuse::RD_SYS_PART1_DATA6
• efuse::RD_SYS_PART1_DATA7
• efuse::RD_SYS_PART2_DATA0
• efuse::RD_SYS_PART2_DATA1
• efuse::RD_SYS_PART2_DATA2
• efuse::RD_SYS_PART2_DATA3
• efuse::RD_SYS_PART2_DATA4
• efuse::RD_SYS_PART2_DATA5
• efuse::RD_SYS_PART2_DATA6
• efuse::RD_SYS_PART2_DATA7
• efuse::RD_TIM_CONF
• efuse::RD_USR_DATA0
• efuse::RD_USR_DATA1
• efuse::RD_USR_DATA2
• efuse::RD_USR_DATA3
• efuse::RD_USR_DATA4
• efuse::RD_USR_DATA5
• efuse::RD_USR_DATA6
• efuse::RD_USR_DATA7
• efuse::RD_WR_DIS
• efuse::STATUS
• efuse::WR_TIM_CONF0_RS_BYPASS
• efuse::WR_TIM_CONF1
• efuse::WR_TIM_CONF2
• efuse::clk::EN_R
• efuse::clk::EN_W
• efuse::clk::MEM_CLK_FORCE_ON_R
• efuse::clk::MEM_CLK_FORCE_ON_W
• efuse::clk::MEM_FORCE_PD_R
• efuse::clk::MEM_FORCE_PD_W
• efuse::clk::MEM_FORCE_PU_R
• efuse::clk::MEM_FORCE_PU_W
• efuse::clk::R
• efuse::clk::W
• efuse::cmd::BLK_NUM_R
• efuse::cmd::BLK_NUM_W
• efuse::cmd::PGM_CMD_R
• efuse::cmd::PGM_CMD_W
• efuse::cmd::R
• efuse::cmd::READ_CMD_R
• efuse::cmd::READ_CMD_W
• efuse::cmd::W
• efuse::conf::OP_CODE_R
• efuse::conf::OP_CODE_W
• efuse::conf::R
• efuse::conf::W
• efuse::dac_conf::DAC_CLK_DIV_R
• efuse::dac_conf::DAC_CLK_DIV_W
• efuse::dac_conf::DAC_CLK_PAD_SEL_R
• efuse::dac_conf::DAC_CLK_PAD_SEL_W
• efuse::dac_conf::DAC_NUM_R
• efuse::dac_conf::DAC_NUM_W
• efuse::dac_conf::OE_CLR_R
• efuse::dac_conf::OE_CLR_W
• efuse::dac_conf::R
• efuse::dac_conf::W
• efuse::date::DATE_R
• efuse::date::DATE_W
• efuse::date::R
• efuse::date::W
• efuse::int_clr::PGM_DONE_W
• efuse::int_clr::READ_DONE_W
• efuse::int_clr::W
• efuse::int_ena::PGM_DONE_R
• efuse::int_ena::PGM_DONE_W
• efuse::int_ena::R
• efuse::int_ena::READ_DONE_R
• efuse::int_ena::READ_DONE_W
• efuse::int_ena::W
• efuse::int_raw::PGM_DONE_R
• efuse::int_raw::R
• efuse::int_raw::READ_DONE_R
• efuse::int_st::PGM_DONE_R
• efuse::int_st::R
• efuse::int_st::READ_DONE_R
• efuse::pgm_check_value0::PGM_RS_DATA_0_R
• efuse::pgm_check_value0::PGM_RS_DATA_0_W
• efuse::pgm_check_value0::R
• efuse::pgm_check_value0::W
• efuse::pgm_check_value1::PGM_RS_DATA_1_R
• efuse::pgm_check_value1::PGM_RS_DATA_1_W
• efuse::pgm_check_value1::R
• efuse::pgm_check_value1::W
• efuse::pgm_check_value2::PGM_RS_DATA_2_R
• efuse::pgm_check_value2::PGM_RS_DATA_2_W
• efuse::pgm_check_value2::R
• efuse::pgm_check_value2::W
• efuse::pgm_data0::PGM_DATA_0_R
• efuse::pgm_data0::PGM_DATA_0_W
• efuse::pgm_data0::R
• efuse::pgm_data0::W
• efuse::pgm_data1::PGM_DATA_1_R
• efuse::pgm_data1::PGM_DATA_1_W
• efuse::pgm_data1::R
• efuse::pgm_data1::W
• efuse::pgm_data2::PGM_DATA_2_R
• efuse::pgm_data2::PGM_DATA_2_W
• efuse::pgm_data2::R
• efuse::pgm_data2::W
• efuse::pgm_data3::PGM_DATA_3_R
• efuse::pgm_data3::PGM_DATA_3_W
• efuse::pgm_data3::R
• efuse::pgm_data3::W
• efuse::pgm_data4::PGM_DATA_4_R
• efuse::pgm_data4::PGM_DATA_4_W
• efuse::pgm_data4::R
• efuse::pgm_data4::W
• efuse::pgm_data5::PGM_DATA_5_R
• efuse::pgm_data5::PGM_DATA_5_W
• efuse::pgm_data5::R
• efuse::pgm_data5::W
• efuse::pgm_data6::PGM_DATA_6_R
• efuse::pgm_data6::PGM_DATA_6_W
• efuse::pgm_data6::R
• efuse::pgm_data6::W
• efuse::pgm_data7::PGM_DATA_7_R
• efuse::pgm_data7::PGM_DATA_7_W
• efuse::pgm_data7::R
• efuse::pgm_data7::W
• efuse::rd_key0_data0::KEY0_DATA0_R
• efuse::rd_key0_data0::R
• efuse::rd_key0_data1::KEY0_DATA1_R
• efuse::rd_key0_data1::R
• efuse::rd_key0_data2::KEY0_DATA2_R
• efuse::rd_key0_data2::R
• efuse::rd_key0_data3::KEY0_DATA3_R
• efuse::rd_key0_data3::R
• efuse::rd_key0_data4::KEY0_DATA4_R
• efuse::rd_key0_data4::R
• efuse::rd_key0_data5::KEY0_DATA5_R
• efuse::rd_key0_data5::R
• efuse::rd_key0_data6::KEY0_DATA6_R
• efuse::rd_key0_data6::R
• efuse::rd_key0_data7::KEY0_DATA7_R
• efuse::rd_key0_data7::R
• efuse::rd_key1_data0::KEY1_DATA0_R
• efuse::rd_key1_data0::R
• efuse::rd_key1_data1::KEY1_DATA1_R
• efuse::rd_key1_data1::R
• efuse::rd_key1_data2::KEY1_DATA2_R
• efuse::rd_key1_data2::R
• efuse::rd_key1_data3::KEY1_DATA3_R
• efuse::rd_key1_data3::R
• efuse::rd_key1_data4::KEY1_DATA4_R
• efuse::rd_key1_data4::R
• efuse::rd_key1_data5::KEY1_DATA5_R
• efuse::rd_key1_data5::R
• efuse::rd_key1_data6::KEY1_DATA6_R
• efuse::rd_key1_data6::R
• efuse::rd_key1_data7::KEY1_DATA7_R
• efuse::rd_key1_data7::R
• efuse::rd_key2_data0::KEY2_DATA0_R
• efuse::rd_key2_data0::R
• efuse::rd_key2_data1::KEY2_DATA1_R
• efuse::rd_key2_data1::R
• efuse::rd_key2_data2::KEY2_DATA2_R
• efuse::rd_key2_data2::R
• efuse::rd_key2_data3::KEY2_DATA3_R
• efuse::rd_key2_data3::R
• efuse::rd_key2_data4::KEY2_DATA4_R
• efuse::rd_key2_data4::R
• efuse::rd_key2_data5::KEY2_DATA5_R
• efuse::rd_key2_data5::R
• efuse::rd_key2_data6::KEY2_DATA6_R
• efuse::rd_key2_data6::R
• efuse::rd_key2_data7::KEY2_DATA7_R
• efuse::rd_key2_data7::R
• efuse::rd_key3_data0::KEY3_DATA0_R
• efuse::rd_key3_data0::R
• efuse::rd_key3_data1::KEY3_DATA1_R
• efuse::rd_key3_data1::R
• efuse::rd_key3_data2::KEY3_DATA2_R
• efuse::rd_key3_data2::R
• efuse::rd_key3_data3::KEY3_DATA3_R
• efuse::rd_key3_data3::R
• efuse::rd_key3_data4::KEY3_DATA4_R
• efuse::rd_key3_data4::R
• efuse::rd_key3_data5::KEY3_DATA5_R
• efuse::rd_key3_data5::R
• efuse::rd_key3_data6::KEY3_DATA6_R
• efuse::rd_key3_data6::R
• efuse::rd_key3_data7::KEY3_DATA7_R
• efuse::rd_key3_data7::R
• efuse::rd_key4_data0::KEY4_DATA0_R
• efuse::rd_key4_data0::R
• efuse::rd_key4_data1::KEY4_DATA1_R
• efuse::rd_key4_data1::R
• efuse::rd_key4_data2::KEY4_DATA2_R
• efuse::rd_key4_data2::R
• efuse::rd_key4_data3::KEY4_DATA3_R
• efuse::rd_key4_data3::R
• efuse::rd_key4_data4::KEY4_DATA4_R
• efuse::rd_key4_data4::R
• efuse::rd_key4_data5::KEY4_DATA5_R
• efuse::rd_key4_data5::R
• efuse::rd_key4_data6::KEY4_DATA6_R
• efuse::rd_key4_data6::R
• efuse::rd_key4_data7::KEY4_DATA7_R
• efuse::rd_key4_data7::R
• efuse::rd_key5_data0::KEY5_DATA0_R
• efuse::rd_key5_data0::R
• efuse::rd_key5_data1::KEY5_DATA1_R
• efuse::rd_key5_data1::R
• efuse::rd_key5_data2::KEY5_DATA2_R
• efuse::rd_key5_data2::R
• efuse::rd_key5_data3::KEY5_DATA3_R
• efuse::rd_key5_data3::R
• efuse::rd_key5_data4::KEY5_DATA4_R
• efuse::rd_key5_data4::R
• efuse::rd_key5_data5::KEY5_DATA5_R
• efuse::rd_key5_data5::R
• efuse::rd_key5_data6::KEY5_DATA6_R
• efuse::rd_key5_data6::R
• efuse::rd_key5_data7::KEY5_DATA7_R
• efuse::rd_key5_data7::R
• efuse::rd_mac_spi_sys_0::MAC_0_R
• efuse::rd_mac_spi_sys_0::R
• efuse::rd_mac_spi_sys_1::MAC_1_R
• efuse::rd_mac_spi_sys_1::MAC_EXT_R
• efuse::rd_mac_spi_sys_1::R
• efuse::rd_mac_spi_sys_2::ACTIVE_HP_DBIAS_R
• efuse::rd_mac_spi_sys_2::ACTIVE_LP_DBIAS_R
• efuse::rd_mac_spi_sys_2::DBIAS_VOL_GAP_R
• efuse::rd_mac_spi_sys_2::DSLP_LP_DBG_R
• efuse::rd_mac_spi_sys_2::DSLP_LP_DBIAS_R
• efuse::rd_mac_spi_sys_2::LSLP_HP_DBG_R
• efuse::rd_mac_spi_sys_2::LSLP_HP_DBIAS_R
• efuse::rd_mac_spi_sys_2::R
• efuse::rd_mac_spi_sys_2::SPI_PAD_CONF_1_R
• efuse::rd_mac_spi_sys_3::R
• efuse::rd_mac_spi_sys_3::SPI_PAD_CONF_2_R
• efuse::rd_mac_spi_sys_3::SYS_DATA_PART0_0_R
• efuse::rd_mac_spi_sys_4::R
• efuse::rd_mac_spi_sys_4::SYS_DATA_PART0_1_R
• efuse::rd_mac_spi_sys_5::R
• efuse::rd_mac_spi_sys_5::SYS_DATA_PART0_2_R
• efuse::rd_repeat_data0::DIS_CAN_R
• efuse::rd_repeat_data0::DIS_DOWNLOAD_ICACHE_R
• efuse::rd_repeat_data0::DIS_DOWNLOAD_MANUAL_ENCRYPT_R
• efuse::rd_repeat_data0::DIS_FORCE_DOWNLOAD_R
• efuse::rd_repeat_data0::DIS_ICACHE_R
• efuse::rd_repeat_data0::DIS_PAD_JTAG_R
• efuse::rd_repeat_data0::DIS_USB_JTAG_R
• efuse::rd_repeat_data0::DIS_USB_SERIAL_JTAG_R
• efuse::rd_repeat_data0::JTAG_SEL_ENABLE_R
• efuse::rd_repeat_data0::R
• efuse::rd_repeat_data0::RD_DIS_R
• efuse::rd_repeat_data0::RPT4_RESERVED0_0_R
• efuse::rd_repeat_data0::RPT4_RESERVED0_1_R
• efuse::rd_repeat_data0::RPT4_RESERVED0_2_R
• efuse::rd_repeat_data0::SOFT_DIS_JTAG_R
• efuse::rd_repeat_data0::SPI_DOWNLOAD_MSPI_DIS_R
• efuse::rd_repeat_data0::SWAP_UART_SDIO_EN_R
• efuse::rd_repeat_data0::USB_DREFH_R
• efuse::rd_repeat_data0::USB_DREFL_R
• efuse::rd_repeat_data0::USB_EXCHG_PINS_R
• efuse::rd_repeat_data0::VDD_SPI_AS_GPIO_R
• efuse::rd_repeat_data1::KEY_PURPOSE_0_R
• efuse::rd_repeat_data1::KEY_PURPOSE_1_R
• efuse::rd_repeat_data1::R
• efuse::rd_repeat_data1::RPT4_RESERVED1_0_R
• efuse::rd_repeat_data1::SECURE_BOOT_KEY_REVOKE0_R
• efuse::rd_repeat_data1::SECURE_BOOT_KEY_REVOKE1_R
• efuse::rd_repeat_data1::SECURE_BOOT_KEY_REVOKE2_R
• efuse::rd_repeat_data1::SPI_BOOT_CRYPT_CNT_R
• efuse::rd_repeat_data1::WDT_DELAY_SEL_R
• efuse::rd_repeat_data2::CRYPT_DPA_ENABLE_R
• efuse::rd_repeat_data2::DPA_SEC_LEVEL_R
• efuse::rd_repeat_data2::FLASH_TPUW_R
• efuse::rd_repeat_data2::KEY_PURPOSE_2_R
• efuse::rd_repeat_data2::KEY_PURPOSE_3_R
• efuse::rd_repeat_data2::KEY_PURPOSE_4_R
• efuse::rd_repeat_data2::KEY_PURPOSE_5_R
• efuse::rd_repeat_data2::R
• efuse::rd_repeat_data2::RPT4_RESERVED2_0_R
• efuse::rd_repeat_data2::RPT4_RESERVED2_1_R
• efuse::rd_repeat_data2::SECURE_BOOT_AGGRESSIVE_REVOKE_R
• efuse::rd_repeat_data2::SECURE_BOOT_EN_R
• efuse::rd_repeat_data3::DIS_DIRECT_BOOT_R
• efuse::rd_repeat_data3::DIS_DOWNLOAD_MODE_R
• efuse::rd_repeat_data3::DIS_USB_PRINT_R
• efuse::rd_repeat_data3::DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_R
• efuse::rd_repeat_data3::ENABLE_SECURITY_DOWNLOAD_R
• efuse::rd_repeat_data3::FORCE_SEND_RESUME_R
• efuse::rd_repeat_data3::R
• efuse::rd_repeat_data3::RPT4_RESERVED3_0_R
• efuse::rd_repeat_data3::RPT4_RESERVED3_1_R
• efuse::rd_repeat_data3::RPT4_RESERVED3_2_R
• efuse::rd_repeat_data3::RPT4_RESERVED3_3_R
• efuse::rd_repeat_data3::RPT4_RESERVED3_4_R
• efuse::rd_repeat_data3::RPT4_RESERVED3_5_R
• efuse::rd_repeat_data3::SECURE_BOOT_DISABLE_FAST_WAKE_R
• efuse::rd_repeat_data3::SECURE_VERSION_R
• efuse::rd_repeat_data3::UART_PRINT_CONTROL_R
• efuse::rd_repeat_data4::R
• efuse::rd_repeat_data4::RPT4_RESERVED4_0_R
• efuse::rd_repeat_data4::RPT4_RESERVED4_1_R
• efuse::rd_repeat_err0::DIS_DOWNLOAD_ICACHE_ERR_R
• efuse::rd_repeat_err0::DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_R
• efuse::rd_repeat_err0::DIS_FORCE_DOWNLOAD_ERR_R
• efuse::rd_repeat_err0::DIS_ICACHE_ERR_R
• efuse::rd_repeat_err0::DIS_PAD_JTAG_ERR_R
• efuse::rd_repeat_err0::DIS_TWAI_ERR_R
• efuse::rd_repeat_err0::DIS_USB_JTAG_ERR_R
• efuse::rd_repeat_err0::DIS_USB_SERIAL_JTAG_ERR_R
• efuse::rd_repeat_err0::JTAG_SEL_ENABLE_ERR_R
• efuse::rd_repeat_err0::R
• efuse::rd_repeat_err0::RD_DIS_ERR_R
• efuse::rd_repeat_err0::RPT4_RESERVED0_ERR_0_R
• efuse::rd_repeat_err0::RPT4_RESERVED0_ERR_1_R
• efuse::rd_repeat_err0::RPT4_RESERVED0_ERR_2_R
• efuse::rd_repeat_err0::SOFT_DIS_JTAG_ERR_R
• efuse::rd_repeat_err0::SPI_DOWNLOAD_MSPI_DIS_ERR_R
• efuse::rd_repeat_err0::SWAP_UART_SDIO_EN_ERR_R
• efuse::rd_repeat_err0::USB_DREFH_ERR_R
• efuse::rd_repeat_err0::USB_DREFL_ERR_R
• efuse::rd_repeat_err0::USB_EXCHG_PINS_ERR_R
• efuse::rd_repeat_err0::VDD_SPI_AS_GPIO_ERR_R
• efuse::rd_repeat_err1::KEY_PURPOSE_0_ERR_R
• efuse::rd_repeat_err1::KEY_PURPOSE_1_ERR_R
• efuse::rd_repeat_err1::R
• efuse::rd_repeat_err1::RPT4_RESERVED1_ERR_0_R
• efuse::rd_repeat_err1::SECURE_BOOT_KEY_REVOKE0_ERR_R
• efuse::rd_repeat_err1::SECURE_BOOT_KEY_REVOKE1_ERR_R
• efuse::rd_repeat_err1::SECURE_BOOT_KEY_REVOKE2_ERR_R
• efuse::rd_repeat_err1::SPI_BOOT_CRYPT_CNT_ERR_R
• efuse::rd_repeat_err1::WDT_DELAY_SEL_ERR_R
• efuse::rd_repeat_err2::CRYPT_DPA_ENABLE_ERR_R
• efuse::rd_repeat_err2::FLASH_TPUW_ERR_R
• efuse::rd_repeat_err2::KEY_PURPOSE_2_ERR_R
• efuse::rd_repeat_err2::KEY_PURPOSE_3_ERR_R
• efuse::rd_repeat_err2::KEY_PURPOSE_4_ERR_R
• efuse::rd_repeat_err2::KEY_PURPOSE_5_ERR_R
• efuse::rd_repeat_err2::R
• efuse::rd_repeat_err2::RPT4_RESERVED2_ERR_0_R
• efuse::rd_repeat_err2::RPT4_RESERVED2_ERR_1_R
• efuse::rd_repeat_err2::SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_R
• efuse::rd_repeat_err2::SECURE_BOOT_EN_ERR_R
• efuse::rd_repeat_err2::SEC_DPA_LEVEL_ERR_R
• efuse::rd_repeat_err3::DIS_DIRECT_BOOT_ERR_R
• efuse::rd_repeat_err3::DIS_DOWNLOAD_MODE_ERR_R
• efuse::rd_repeat_err3::DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_ERR_R
• efuse::rd_repeat_err3::ENABLE_SECURITY_DOWNLOAD_ERR_R
• efuse::rd_repeat_err3::FORCE_SEND_RESUME_ERR_R
• efuse::rd_repeat_err3::R
• efuse::rd_repeat_err3::RPT4_RESERVED3_ERR_0_R
• efuse::rd_repeat_err3::RPT4_RESERVED3_ERR_1_R
• efuse::rd_repeat_err3::RPT4_RESERVED3_ERR_2_R
• efuse::rd_repeat_err3::RPT4_RESERVED3_ERR_3_R
• efuse::rd_repeat_err3::RPT4_RESERVED3_ERR_4_R
• efuse::rd_repeat_err3::RPT4_RESERVED3_ERR_5_R
• efuse::rd_repeat_err3::SECURE_VERSION_ERR_R
• efuse::rd_repeat_err3::UART_PRINT_CONTROL_ERR_R
• efuse::rd_repeat_err3::USB_PRINT_ERR_R
• efuse::rd_repeat_err4::R
• efuse::rd_repeat_err4::RPT4_RESERVED4_ERR_0_R
• efuse::rd_repeat_err4::RPT4_RESERVED4_ERR_1_R
• efuse::rd_rs_err0::KEY0_ERR_NUM_R
• efuse::rd_rs_err0::KEY0_FAIL_R
• efuse::rd_rs_err0::KEY1_ERR_NUM_R
• efuse::rd_rs_err0::KEY1_FAIL_R
• efuse::rd_rs_err0::KEY2_ERR_NUM_R
• efuse::rd_rs_err0::KEY2_FAIL_R
• efuse::rd_rs_err0::KEY3_ERR_NUM_R
• efuse::rd_rs_err0::KEY3_FAIL_R
• efuse::rd_rs_err0::KEY4_ERR_NUM_R
• efuse::rd_rs_err0::KEY4_FAIL_R
• efuse::rd_rs_err0::MAC_SPI_8M_ERR_NUM_R
• efuse::rd_rs_err0::MAC_SPI_8M_FAIL_R
• efuse::rd_rs_err0::R
• efuse::rd_rs_err0::SYS_PART1_FAIL_R
• efuse::rd_rs_err0::SYS_PART1_NUM_R
• efuse::rd_rs_err0::USR_DATA_ERR_NUM_R
• efuse::rd_rs_err0::USR_DATA_FAIL_R
• efuse::rd_rs_err1::KEY5_ERR_NUM_R
• efuse::rd_rs_err1::KEY5_FAIL_R
• efuse::rd_rs_err1::R
• efuse::rd_rs_err1::SYS_PART2_ERR_NUM_R
• efuse::rd_rs_err1::SYS_PART2_FAIL_R
• efuse::rd_sys_part1_data0::R
• efuse::rd_sys_part1_data0::SYS_DATA_PART1_0_R
• efuse::rd_sys_part1_data1::R
• efuse::rd_sys_part1_data1::SYS_DATA_PART1_1_R
• efuse::rd_sys_part1_data2::R
• efuse::rd_sys_part1_data2::SYS_DATA_PART1_2_R
• efuse::rd_sys_part1_data3::R
• efuse::rd_sys_part1_data3::SYS_DATA_PART1_3_R
• efuse::rd_sys_part1_data4::R
• efuse::rd_sys_part1_data4::SYS_DATA_PART1_4_R
• efuse::rd_sys_part1_data5::R
• efuse::rd_sys_part1_data5::SYS_DATA_PART1_5_R
• efuse::rd_sys_part1_data6::R
• efuse::rd_sys_part1_data6::SYS_DATA_PART1_6_R
• efuse::rd_sys_part1_data7::R
• efuse::rd_sys_part1_data7::SYS_DATA_PART1_7_R
• efuse::rd_sys_part2_data0::R
• efuse::rd_sys_part2_data0::SYS_DATA_PART2_0_R
• efuse::rd_sys_part2_data1::R
• efuse::rd_sys_part2_data1::SYS_DATA_PART2_1_R
• efuse::rd_sys_part2_data2::R
• efuse::rd_sys_part2_data2::SYS_DATA_PART2_2_R
• efuse::rd_sys_part2_data3::R
• efuse::rd_sys_part2_data3::SYS_DATA_PART2_3_R
• efuse::rd_sys_part2_data4::R
• efuse::rd_sys_part2_data4::SYS_DATA_PART2_4_R
• efuse::rd_sys_part2_data5::R
• efuse::rd_sys_part2_data5::SYS_DATA_PART2_5_R
• efuse::rd_sys_part2_data6::R
• efuse::rd_sys_part2_data6::SYS_DATA_PART2_6_R
• efuse::rd_sys_part2_data7::R
• efuse::rd_sys_part2_data7::SYS_DATA_PART2_7_R
• efuse::rd_tim_conf::R
• efuse::rd_tim_conf::READ_INIT_NUM_R
• efuse::rd_tim_conf::READ_INIT_NUM_W
• efuse::rd_tim_conf::THR_A_R
• efuse::rd_tim_conf::THR_A_W
• efuse::rd_tim_conf::TRD_R
• efuse::rd_tim_conf::TRD_W
• efuse::rd_tim_conf::TSUR_A_R
• efuse::rd_tim_conf::TSUR_A_W
• efuse::rd_tim_conf::W
• efuse::rd_usr_data0::R
• efuse::rd_usr_data0::USR_DATA0_R
• efuse::rd_usr_data1::R
• efuse::rd_usr_data1::USR_DATA1_R
• efuse::rd_usr_data2::R
• efuse::rd_usr_data2::USR_DATA2_R
• efuse::rd_usr_data3::R
• efuse::rd_usr_data3::USR_DATA3_R
• efuse::rd_usr_data4::R
• efuse::rd_usr_data4::USR_DATA4_R
• efuse::rd_usr_data5::R
• efuse::rd_usr_data5::USR_DATA5_R
• efuse::rd_usr_data6::R
• efuse::rd_usr_data6::USR_DATA6_R
• efuse::rd_usr_data7::R
• efuse::rd_usr_data7::USR_DATA7_R
• efuse::rd_wr_dis::R
• efuse::rd_wr_dis::WR_DIS_R
• efuse::status::BLK0_VALID_BIT_CNT_R
• efuse::status::OTP_CSB_SW_R
• efuse::status::OTP_LOAD_SW_R
• efuse::status::OTP_PGENB_SW_R
• efuse::status::OTP_STROBE_SW_R
• efuse::status::OTP_VDDQ_C_SYNC2_R
• efuse::status::OTP_VDDQ_IS_SW_R
• efuse::status::R
• efuse::status::STATE_R
• efuse::wr_tim_conf0_rs_bypass::BYPASS_RS_BLK_NUM_R
• efuse::wr_tim_conf0_rs_bypass::BYPASS_RS_BLK_NUM_W
• efuse::wr_tim_conf0_rs_bypass::BYPASS_RS_CORRECTION_R
• efuse::wr_tim_conf0_rs_bypass::BYPASS_RS_CORRECTION_W
• efuse::wr_tim_conf0_rs_bypass::R
• efuse::wr_tim_conf0_rs_bypass::TPGM_INACTIVE_R
• efuse::wr_tim_conf0_rs_bypass::TPGM_INACTIVE_W
• efuse::wr_tim_conf0_rs_bypass::UPDATE_W
• efuse::wr_tim_conf0_rs_bypass::W
• efuse::wr_tim_conf1::PWR_ON_NUM_R
• efuse::wr_tim_conf1::PWR_ON_NUM_W
• efuse::wr_tim_conf1::R
• efuse::wr_tim_conf1::THP_A_R
• efuse::wr_tim_conf1::THP_A_W
• efuse::wr_tim_conf1::TSUP_A_R
• efuse::wr_tim_conf1::TSUP_A_W
• efuse::wr_tim_conf1::W
• efuse::wr_tim_conf2::PWR_OFF_NUM_R
• efuse::wr_tim_conf2::PWR_OFF_NUM_W
• efuse::wr_tim_conf2::R
• efuse::wr_tim_conf2::TPGM_R
• efuse::wr_tim_conf2::TPGM_W
• efuse::wr_tim_conf2::W
• extmem::CACHE_LOCK_ADDR
• extmem::CACHE_LOCK_CTRL
• extmem::CACHE_LOCK_MAP
• extmem::CACHE_LOCK_SIZE
• extmem::CACHE_SYNC_ADDR
• extmem::CACHE_SYNC_CTRL
• extmem::CACHE_SYNC_MAP
• extmem::CACHE_SYNC_SIZE
• extmem::CLOCK_GATE
• extmem::DATE
• extmem::L1_BUS0_ACS_CONFLICT_CNT
• extmem::L1_BUS0_ACS_HIT_CNT
• extmem::L1_BUS0_ACS_MISS_CNT
• extmem::L1_BUS0_ACS_NXTLVL_CNT
• extmem::L1_BUS1_ACS_CONFLICT_CNT
• extmem::L1_BUS1_ACS_HIT_CNT
• extmem::L1_BUS1_ACS_MISS_CNT
• extmem::L1_BUS1_ACS_NXTLVL_CNT
• extmem::L1_BYPASS_CACHE_CONF
• extmem::L1_CACHE_ACS_CNT_CTRL
• extmem::L1_CACHE_ACS_CNT_INT_CLR
• extmem::L1_CACHE_ACS_CNT_INT_ENA
• extmem::L1_CACHE_ACS_CNT_INT_RAW
• extmem::L1_CACHE_ACS_CNT_INT_ST
• extmem::L1_CACHE_ACS_FAIL_ID_ATTR
• extmem::L1_CACHE_ACS_FAIL_INT_CLR
• extmem::L1_CACHE_ACS_FAIL_INT_ENA
• extmem::L1_CACHE_ACS_FAIL_INT_RAW
• extmem::L1_CACHE_ACS_FAIL_INT_ST
• extmem::L1_CACHE_ATOMIC_CONF
• extmem::L1_CACHE_AUTOLOAD_BUF_CLR_CTRL
• extmem::L1_CACHE_AUTOLOAD_CTRL
• extmem::L1_CACHE_AUTOLOAD_SCT0_ADDR
• extmem::L1_CACHE_AUTOLOAD_SCT0_SIZE
• extmem::L1_CACHE_AUTOLOAD_SCT1_ADDR
• extmem::L1_CACHE_AUTOLOAD_SCT1_SIZE
• extmem::L1_CACHE_AUTOLOAD_SCT2_ADDR
• extmem::L1_CACHE_AUTOLOAD_SCT2_SIZE
• extmem::L1_CACHE_AUTOLOAD_SCT3_ADDR
• extmem::L1_CACHE_AUTOLOAD_SCT3_SIZE
• extmem::L1_CACHE_BLOCKSIZE_CONF
• extmem::L1_CACHE_CACHESIZE_CONF
• extmem::L1_CACHE_CTRL
• extmem::L1_CACHE_DATA_MEM_ACS_CONF
• extmem::L1_CACHE_DATA_MEM_POWER_CTRL
• extmem::L1_CACHE_DEBUG_BUS
• extmem::L1_CACHE_FREEZE_CTRL
• extmem::L1_CACHE_OBJECT_CTRL
• extmem::L1_CACHE_PRELOAD_CTRL
• extmem::L1_CACHE_PRELOAD_RST_CTRL
• extmem::L1_CACHE_PRELOCK_CONF
• extmem::L1_CACHE_PRELOCK_SCT0_ADDR
• extmem::L1_CACHE_SYNC_PRELOAD_EXCEPTION
• extmem::L1_CACHE_SYNC_PRELOAD_INT_CLR
• extmem::L1_CACHE_SYNC_PRELOAD_INT_ENA
• extmem::L1_CACHE_SYNC_PRELOAD_INT_RAW
• extmem::L1_CACHE_SYNC_PRELOAD_INT_ST
• extmem::L1_CACHE_SYNC_RST_CTRL
• extmem::L1_CACHE_TAG_MEM_ACS_CONF
• extmem::L1_CACHE_TAG_MEM_POWER_CTRL
• extmem::L1_CACHE_VADDR
• extmem::L1_CACHE_WAY_OBJECT
• extmem::L1_CACHE_WRAP_AROUND_CTRL
• extmem::L1_DBUS2_ACS_CONFLICT_CNT
• extmem::L1_DBUS2_ACS_HIT_CNT
• extmem::L1_DBUS2_ACS_MISS_CNT
• extmem::L1_DBUS2_ACS_NXTLVL_CNT
• extmem::L1_DBUS3_ACS_CONFLICT_CNT
• extmem::L1_DBUS3_ACS_HIT_CNT
• extmem::L1_DBUS3_ACS_MISS_CNT
• extmem::L1_DBUS3_ACS_NXTLVL_CNT
• extmem::L1_DCACHE_ACS_FAIL_ADDR
• extmem::L1_DCACHE_PRELOAD_ADDR
• extmem::L1_DCACHE_PRELOAD_SIZE
• extmem::L1_DCACHE_PRELOCK_SCT1_ADDR
• extmem::L1_DCACHE_PRELOCK_SCT_SIZE
• extmem::L1_IBUS0_ACS_CONFLICT_CNT
• extmem::L1_IBUS0_ACS_HIT_CNT
• extmem::L1_IBUS0_ACS_MISS_CNT
• extmem::L1_IBUS0_ACS_NXTLVL_CNT
• extmem::L1_IBUS1_ACS_CONFLICT_CNT
• extmem::L1_IBUS1_ACS_HIT_CNT
• extmem::L1_IBUS1_ACS_MISS_CNT
• extmem::L1_IBUS1_ACS_NXTLVL_CNT
• extmem::L1_IBUS2_ACS_CONFLICT_CNT
• extmem::L1_IBUS2_ACS_HIT_CNT
• extmem::L1_IBUS2_ACS_MISS_CNT
• extmem::L1_IBUS2_ACS_NXTLVL_CNT
• extmem::L1_IBUS3_ACS_CONFLICT_CNT
• extmem::L1_IBUS3_ACS_HIT_CNT
• extmem::L1_IBUS3_ACS_MISS_CNT
• extmem::L1_IBUS3_ACS_NXTLVL_CNT
• extmem::L1_ICACHE0_ACS_FAIL_ADDR
• extmem::L1_ICACHE0_ACS_FAIL_ID_ATTR
• extmem::L1_ICACHE0_AUTOLOAD_CTRL
• extmem::L1_ICACHE0_AUTOLOAD_SCT0_ADDR
• extmem::L1_ICACHE0_AUTOLOAD_SCT0_SIZE
• extmem::L1_ICACHE0_AUTOLOAD_SCT1_ADDR
• extmem::L1_ICACHE0_AUTOLOAD_SCT1_SIZE
• extmem::L1_ICACHE0_PRELOAD_ADDR
• extmem::L1_ICACHE0_PRELOAD_CTRL
• extmem::L1_ICACHE0_PRELOAD_SIZE
• extmem::L1_ICACHE0_PRELOCK_CONF
• extmem::L1_ICACHE0_PRELOCK_SCT0_ADDR
• extmem::L1_ICACHE0_PRELOCK_SCT1_ADDR
• extmem::L1_ICACHE0_PRELOCK_SCT_SIZE
• extmem::L1_ICACHE1_ACS_FAIL_ADDR
• extmem::L1_ICACHE1_ACS_FAIL_ID_ATTR
• extmem::L1_ICACHE1_AUTOLOAD_CTRL
• extmem::L1_ICACHE1_AUTOLOAD_SCT0_ADDR
• extmem::L1_ICACHE1_AUTOLOAD_SCT0_SIZE
• extmem::L1_ICACHE1_AUTOLOAD_SCT1_ADDR
• extmem::L1_ICACHE1_AUTOLOAD_SCT1_SIZE
• extmem::L1_ICACHE1_PRELOAD_ADDR
• extmem::L1_ICACHE1_PRELOAD_CTRL
• extmem::L1_ICACHE1_PRELOAD_SIZE
• extmem::L1_ICACHE1_PRELOCK_CONF
• extmem::L1_ICACHE1_PRELOCK_SCT0_ADDR
• extmem::L1_ICACHE1_PRELOCK_SCT1_ADDR
• extmem::L1_ICACHE1_PRELOCK_SCT_SIZE
• extmem::L1_ICACHE2_ACS_FAIL_ADDR
• extmem::L1_ICACHE2_ACS_FAIL_ID_ATTR
• extmem::L1_ICACHE2_AUTOLOAD_CTRL
• extmem::L1_ICACHE2_AUTOLOAD_SCT0_ADDR
• extmem::L1_ICACHE2_AUTOLOAD_SCT0_SIZE
• extmem::L1_ICACHE2_AUTOLOAD_SCT1_ADDR
• extmem::L1_ICACHE2_AUTOLOAD_SCT1_SIZE
• extmem::L1_ICACHE2_PRELOAD_ADDR
• extmem::L1_ICACHE2_PRELOAD_CTRL
• extmem::L1_ICACHE2_PRELOAD_SIZE
• extmem::L1_ICACHE2_PRELOCK_CONF
• extmem::L1_ICACHE2_PRELOCK_SCT0_ADDR
• extmem::L1_ICACHE2_PRELOCK_SCT1_ADDR
• extmem::L1_ICACHE2_PRELOCK_SCT_SIZE
• extmem::L1_ICACHE3_ACS_FAIL_ADDR
• extmem::L1_ICACHE3_ACS_FAIL_ID_ATTR
• extmem::L1_ICACHE3_AUTOLOAD_CTRL
• extmem::L1_ICACHE3_AUTOLOAD_SCT0_ADDR
• extmem::L1_ICACHE3_AUTOLOAD_SCT0_SIZE
• extmem::L1_ICACHE3_AUTOLOAD_SCT1_ADDR
• extmem::L1_ICACHE3_AUTOLOAD_SCT1_SIZE
• extmem::L1_ICACHE3_PRELOAD_ADDR
• extmem::L1_ICACHE3_PRELOAD_CTRL
• extmem::L1_ICACHE3_PRELOAD_SIZE
• extmem::L1_ICACHE3_PRELOCK_CONF
• extmem::L1_ICACHE3_PRELOCK_SCT0_ADDR
• extmem::L1_ICACHE3_PRELOCK_SCT1_ADDR
• extmem::L1_ICACHE3_PRELOCK_SCT_SIZE
• extmem::L1_ICACHE_BLOCKSIZE_CONF
• extmem::L1_ICACHE_CACHESIZE_CONF
• extmem::L1_ICACHE_CTRL
• extmem::L1_UNALLOCATE_BUFFER_CLEAR
• extmem::L2_BYPASS_CACHE_CONF
• extmem::L2_CACHE_ACCESS_ATTR_CTRL
• extmem::L2_CACHE_ACS_CNT_CTRL
• extmem::L2_CACHE_ACS_CNT_INT_CLR
• extmem::L2_CACHE_ACS_CNT_INT_ENA
• extmem::L2_CACHE_ACS_CNT_INT_RAW
• extmem::L2_CACHE_ACS_CNT_INT_ST
• extmem::L2_CACHE_ACS_FAIL_ADDR
• extmem::L2_CACHE_ACS_FAIL_ID_ATTR
• extmem::L2_CACHE_ACS_FAIL_INT_CLR
• extmem::L2_CACHE_ACS_FAIL_INT_ENA
• extmem::L2_CACHE_ACS_FAIL_INT_RAW
• extmem::L2_CACHE_ACS_FAIL_INT_ST
• extmem::L2_CACHE_AUTOLOAD_BUF_CLR_CTRL
• extmem::L2_CACHE_AUTOLOAD_CTRL
• extmem::L2_CACHE_AUTOLOAD_SCT0_ADDR
• extmem::L2_CACHE_AUTOLOAD_SCT0_SIZE
• extmem::L2_CACHE_AUTOLOAD_SCT1_ADDR
• extmem::L2_CACHE_AUTOLOAD_SCT1_SIZE
• extmem::L2_CACHE_AUTOLOAD_SCT2_ADDR
• extmem::L2_CACHE_AUTOLOAD_SCT2_SIZE
• extmem::L2_CACHE_AUTOLOAD_SCT3_ADDR
• extmem::L2_CACHE_AUTOLOAD_SCT3_SIZE
• extmem::L2_CACHE_BLOCKSIZE_CONF
• extmem::L2_CACHE_CACHESIZE_CONF
• extmem::L2_CACHE_CTRL
• extmem::L2_CACHE_DATA_MEM_ACS_CONF
• extmem::L2_CACHE_DATA_MEM_POWER_CTRL
• extmem::L2_CACHE_DEBUG_BUS
• extmem::L2_CACHE_FREEZE_CTRL
• extmem::L2_CACHE_OBJECT_CTRL
• extmem::L2_CACHE_PRELOAD_ADDR
• extmem::L2_CACHE_PRELOAD_CTRL
• extmem::L2_CACHE_PRELOAD_RST_CTRL
• extmem::L2_CACHE_PRELOAD_SIZE
• extmem::L2_CACHE_PRELOCK_CONF
• extmem::L2_CACHE_PRELOCK_SCT0_ADDR
• extmem::L2_CACHE_PRELOCK_SCT1_ADDR
• extmem::L2_CACHE_PRELOCK_SCT_SIZE
• extmem::L2_CACHE_SYNC_PRELOAD_EXCEPTION
• extmem::L2_CACHE_SYNC_PRELOAD_INT_CLR
• extmem::L2_CACHE_SYNC_PRELOAD_INT_ENA
• extmem::L2_CACHE_SYNC_PRELOAD_INT_RAW
• extmem::L2_CACHE_SYNC_PRELOAD_INT_ST
• extmem::L2_CACHE_SYNC_RST_CTRL
• extmem::L2_CACHE_TAG_MEM_ACS_CONF
• extmem::L2_CACHE_TAG_MEM_POWER_CTRL
• extmem::L2_CACHE_VADDR
• extmem::L2_CACHE_WAY_OBJECT
• extmem::L2_CACHE_WRAP_AROUND_CTRL
• extmem::L2_DBUS0_ACS_CONFLICT_CNT
• extmem::L2_DBUS0_ACS_HIT_CNT
• extmem::L2_DBUS0_ACS_MISS_CNT
• extmem::L2_DBUS0_ACS_NXTLVL_CNT
• extmem::L2_DBUS1_ACS_CONFLICT_CNT
• extmem::L2_DBUS1_ACS_HIT_CNT
• extmem::L2_DBUS1_ACS_MISS_CNT
• extmem::L2_DBUS1_ACS_NXTLVL_CNT
• extmem::L2_DBUS2_ACS_CONFLICT_CNT
• extmem::L2_DBUS2_ACS_HIT_CNT
• extmem::L2_DBUS2_ACS_MISS_CNT
• extmem::L2_DBUS2_ACS_NXTLVL_CNT
• extmem::L2_DBUS3_ACS_CONFLICT_CNT
• extmem::L2_DBUS3_ACS_HIT_CNT
• extmem::L2_DBUS3_ACS_MISS_CNT
• extmem::L2_DBUS3_ACS_NXTLVL_CNT
• extmem::L2_IBUS0_ACS_CONFLICT_CNT
• extmem::L2_IBUS0_ACS_HIT_CNT
• extmem::L2_IBUS0_ACS_MISS_CNT
• extmem::L2_IBUS0_ACS_NXTLVL_CNT
• extmem::L2_IBUS1_ACS_CONFLICT_CNT
• extmem::L2_IBUS1_ACS_HIT_CNT
• extmem::L2_IBUS1_ACS_MISS_CNT
• extmem::L2_IBUS1_ACS_NXTLVL_CNT
• extmem::L2_IBUS2_ACS_CONFLICT_CNT
• extmem::L2_IBUS2_ACS_HIT_CNT
• extmem::L2_IBUS2_ACS_MISS_CNT
• extmem::L2_IBUS2_ACS_NXTLVL_CNT
• extmem::L2_IBUS3_ACS_CONFLICT_CNT
• extmem::L2_IBUS3_ACS_HIT_CNT
• extmem::L2_IBUS3_ACS_MISS_CNT
• extmem::L2_IBUS3_ACS_NXTLVL_CNT
• extmem::L2_UNALLOCATE_BUFFER_CLEAR
• extmem::LEVEL_SPLIT0
• extmem::LEVEL_SPLIT1
• extmem::REDUNDANCY_SIG0
• extmem::REDUNDANCY_SIG1
• extmem::REDUNDANCY_SIG2
• extmem::REDUNDANCY_SIG3
• extmem::REDUNDANCY_SIG4
• extmem::cache_lock_addr::CACHE_LOCK_ADDR_R
• extmem::cache_lock_addr::CACHE_LOCK_ADDR_W
• extmem::cache_lock_addr::R
• extmem::cache_lock_addr::W
• extmem::cache_lock_ctrl::CACHE_LOCK_DONE_R
• extmem::cache_lock_ctrl::CACHE_LOCK_ENA_R
• extmem::cache_lock_ctrl::CACHE_LOCK_ENA_W
• extmem::cache_lock_ctrl::CACHE_LOCK_RGID_R
• extmem::cache_lock_ctrl::CACHE_UNLOCK_ENA_R
• extmem::cache_lock_ctrl::CACHE_UNLOCK_ENA_W
• extmem::cache_lock_ctrl::R
• extmem::cache_lock_ctrl::W
• extmem::cache_lock_map::CACHE_LOCK_MAP_R
• extmem::cache_lock_map::CACHE_LOCK_MAP_W
• extmem::cache_lock_map::R
• extmem::cache_lock_map::W
• extmem::cache_lock_size::CACHE_LOCK_SIZE_R
• extmem::cache_lock_size::CACHE_LOCK_SIZE_W
• extmem::cache_lock_size::R
• extmem::cache_lock_size::W
• extmem::cache_sync_addr::CACHE_SYNC_ADDR_R
• extmem::cache_sync_addr::CACHE_SYNC_ADDR_W
• extmem::cache_sync_addr::R
• extmem::cache_sync_addr::W
• extmem::cache_sync_ctrl::CACHE_CLEAN_ENA_R
• extmem::cache_sync_ctrl::CACHE_CLEAN_ENA_W
• extmem::cache_sync_ctrl::CACHE_INVALIDATE_ENA_R
• extmem::cache_sync_ctrl::CACHE_INVALIDATE_ENA_W
• extmem::cache_sync_ctrl::CACHE_SYNC_DONE_R
• extmem::cache_sync_ctrl::CACHE_SYNC_RGID_R
• extmem::cache_sync_ctrl::CACHE_WRITEBACK_ENA_R
• extmem::cache_sync_ctrl::CACHE_WRITEBACK_ENA_W
• extmem::cache_sync_ctrl::CACHE_WRITEBACK_INVALIDATE_ENA_R
• extmem::cache_sync_ctrl::CACHE_WRITEBACK_INVALIDATE_ENA_W
• extmem::cache_sync_ctrl::R
• extmem::cache_sync_ctrl::W
• extmem::cache_sync_map::CACHE_SYNC_MAP_R
• extmem::cache_sync_map::CACHE_SYNC_MAP_W
• extmem::cache_sync_map::R
• extmem::cache_sync_map::W
• extmem::cache_sync_size::CACHE_SYNC_SIZE_R
• extmem::cache_sync_size::CACHE_SYNC_SIZE_W
• extmem::cache_sync_size::R
• extmem::cache_sync_size::W
• extmem::clock_gate::CLK_EN_R
• extmem::clock_gate::CLK_EN_W
• extmem::clock_gate::R
• extmem::clock_gate::W
• extmem::date::DATE_R
• extmem::date::DATE_W
• extmem::date::R
• extmem::date::W
• extmem::l1_bus0_acs_conflict_cnt::L1_BUS0_CONFLICT_CNT_R
• extmem::l1_bus0_acs_conflict_cnt::R
• extmem::l1_bus0_acs_hit_cnt::L1_BUS0_HIT_CNT_R
• extmem::l1_bus0_acs_hit_cnt::R
• extmem::l1_bus0_acs_miss_cnt::L1_BUS0_MISS_CNT_R
• extmem::l1_bus0_acs_miss_cnt::R
• extmem::l1_bus0_acs_nxtlvl_cnt::L1_BUS0_NXTLVL_CNT_R
• extmem::l1_bus0_acs_nxtlvl_cnt::R
• extmem::l1_bus1_acs_conflict_cnt::L1_BUS1_CONFLICT_CNT_R
• extmem::l1_bus1_acs_conflict_cnt::R
• extmem::l1_bus1_acs_hit_cnt::L1_BUS1_HIT_CNT_R
• extmem::l1_bus1_acs_hit_cnt::R
• extmem::l1_bus1_acs_miss_cnt::L1_BUS1_MISS_CNT_R
• extmem::l1_bus1_acs_miss_cnt::R
• extmem::l1_bus1_acs_nxtlvl_cnt::L1_BUS1_NXTLVL_CNT_R
• extmem::l1_bus1_acs_nxtlvl_cnt::R
• extmem::l1_bypass_cache_conf::BYPASS_L1_DCACHE_EN_R
• extmem::l1_bypass_cache_conf::BYPASS_L1_ICACHE0_EN_R
• extmem::l1_bypass_cache_conf::BYPASS_L1_ICACHE1_EN_R
• extmem::l1_bypass_cache_conf::BYPASS_L1_ICACHE2_EN_R
• extmem::l1_bypass_cache_conf::BYPASS_L1_ICACHE3_EN_R
• extmem::l1_bypass_cache_conf::R
• extmem::l1_cache_acs_cnt_ctrl::L1_BUS0_CNT_CLR_W
• extmem::l1_cache_acs_cnt_ctrl::L1_BUS0_CNT_ENA_R
• extmem::l1_cache_acs_cnt_ctrl::L1_BUS0_CNT_ENA_W
• extmem::l1_cache_acs_cnt_ctrl::L1_BUS1_CNT_CLR_W
• extmem::l1_cache_acs_cnt_ctrl::L1_BUS1_CNT_ENA_R
• extmem::l1_cache_acs_cnt_ctrl::L1_BUS1_CNT_ENA_W
• extmem::l1_cache_acs_cnt_ctrl::L1_DBUS2_CNT_CLR_R
• extmem::l1_cache_acs_cnt_ctrl::L1_DBUS2_CNT_ENA_R
• extmem::l1_cache_acs_cnt_ctrl::L1_DBUS3_CNT_CLR_R
• extmem::l1_cache_acs_cnt_ctrl::L1_DBUS3_CNT_ENA_R
• extmem::l1_cache_acs_cnt_ctrl::L1_IBUS0_CNT_CLR_R
• extmem::l1_cache_acs_cnt_ctrl::L1_IBUS0_CNT_ENA_R
• extmem::l1_cache_acs_cnt_ctrl::L1_IBUS1_CNT_CLR_R
• extmem::l1_cache_acs_cnt_ctrl::L1_IBUS1_CNT_ENA_R
• extmem::l1_cache_acs_cnt_ctrl::L1_IBUS2_CNT_CLR_R
• extmem::l1_cache_acs_cnt_ctrl::L1_IBUS2_CNT_ENA_R
• extmem::l1_cache_acs_cnt_ctrl::L1_IBUS3_CNT_CLR_R
• extmem::l1_cache_acs_cnt_ctrl::L1_IBUS3_CNT_ENA_R
• extmem::l1_cache_acs_cnt_ctrl::R
• extmem::l1_cache_acs_cnt_ctrl::W
• extmem::l1_cache_acs_cnt_int_clr::L1_BUS0_OVF_INT_CLR_W
• extmem::l1_cache_acs_cnt_int_clr::L1_BUS1_OVF_INT_CLR_W
• extmem::l1_cache_acs_cnt_int_clr::L1_DBUS2_OVF_INT_CLR_R
• extmem::l1_cache_acs_cnt_int_clr::L1_DBUS3_OVF_INT_CLR_R
• extmem::l1_cache_acs_cnt_int_clr::L1_IBUS0_OVF_INT_CLR_R
• extmem::l1_cache_acs_cnt_int_clr::L1_IBUS1_OVF_INT_CLR_R
• extmem::l1_cache_acs_cnt_int_clr::L1_IBUS2_OVF_INT_CLR_R
• extmem::l1_cache_acs_cnt_int_clr::L1_IBUS3_OVF_INT_CLR_R
• extmem::l1_cache_acs_cnt_int_clr::R
• extmem::l1_cache_acs_cnt_int_clr::W
• extmem::l1_cache_acs_cnt_int_ena::L1_BUS0_OVF_INT_ENA_R
• extmem::l1_cache_acs_cnt_int_ena::L1_BUS0_OVF_INT_ENA_W
• extmem::l1_cache_acs_cnt_int_ena::L1_BUS1_OVF_INT_ENA_R
• extmem::l1_cache_acs_cnt_int_ena::L1_BUS1_OVF_INT_ENA_W
• extmem::l1_cache_acs_cnt_int_ena::L1_DBUS2_OVF_INT_ENA_R
• extmem::l1_cache_acs_cnt_int_ena::L1_DBUS3_OVF_INT_ENA_R
• extmem::l1_cache_acs_cnt_int_ena::L1_IBUS0_OVF_INT_ENA_R
• extmem::l1_cache_acs_cnt_int_ena::L1_IBUS1_OVF_INT_ENA_R
• extmem::l1_cache_acs_cnt_int_ena::L1_IBUS2_OVF_INT_ENA_R
• extmem::l1_cache_acs_cnt_int_ena::L1_IBUS3_OVF_INT_ENA_R
• extmem::l1_cache_acs_cnt_int_ena::R
• extmem::l1_cache_acs_cnt_int_ena::W
• extmem::l1_cache_acs_cnt_int_raw::L1_BUS0_OVF_INT_RAW_R
• extmem::l1_cache_acs_cnt_int_raw::L1_BUS0_OVF_INT_RAW_W
• extmem::l1_cache_acs_cnt_int_raw::L1_BUS1_OVF_INT_RAW_R
• extmem::l1_cache_acs_cnt_int_raw::L1_BUS1_OVF_INT_RAW_W
• extmem::l1_cache_acs_cnt_int_raw::L1_DBUS2_OVF_INT_RAW_R
• extmem::l1_cache_acs_cnt_int_raw::L1_DBUS2_OVF_INT_RAW_W
• extmem::l1_cache_acs_cnt_int_raw::L1_DBUS3_OVF_INT_RAW_R
• extmem::l1_cache_acs_cnt_int_raw::L1_DBUS3_OVF_INT_RAW_W
• extmem::l1_cache_acs_cnt_int_raw::L1_IBUS0_OVF_INT_RAW_R
• extmem::l1_cache_acs_cnt_int_raw::L1_IBUS0_OVF_INT_RAW_W
• extmem::l1_cache_acs_cnt_int_raw::L1_IBUS1_OVF_INT_RAW_R
• extmem::l1_cache_acs_cnt_int_raw::L1_IBUS1_OVF_INT_RAW_W
• extmem::l1_cache_acs_cnt_int_raw::L1_IBUS2_OVF_INT_RAW_R
• extmem::l1_cache_acs_cnt_int_raw::L1_IBUS2_OVF_INT_RAW_W
• extmem::l1_cache_acs_cnt_int_raw::L1_IBUS3_OVF_INT_RAW_R
• extmem::l1_cache_acs_cnt_int_raw::L1_IBUS3_OVF_INT_RAW_W
• extmem::l1_cache_acs_cnt_int_raw::R
• extmem::l1_cache_acs_cnt_int_raw::W
• extmem::l1_cache_acs_cnt_int_st::L1_BUS0_OVF_INT_ST_R
• extmem::l1_cache_acs_cnt_int_st::L1_BUS1_OVF_INT_ST_R
• extmem::l1_cache_acs_cnt_int_st::L1_DBUS2_OVF_INT_ST_R
• extmem::l1_cache_acs_cnt_int_st::L1_DBUS3_OVF_INT_ST_R
• extmem::l1_cache_acs_cnt_int_st::L1_IBUS0_OVF_INT_ST_R
• extmem::l1_cache_acs_cnt_int_st::L1_IBUS1_OVF_INT_ST_R
• extmem::l1_cache_acs_cnt_int_st::L1_IBUS2_OVF_INT_ST_R
• extmem::l1_cache_acs_cnt_int_st::L1_IBUS3_OVF_INT_ST_R
• extmem::l1_cache_acs_cnt_int_st::R
• extmem::l1_cache_acs_fail_id_attr::L1_CACHE_FAIL_ATTR_R
• extmem::l1_cache_acs_fail_id_attr::L1_CACHE_FAIL_ID_R
• extmem::l1_cache_acs_fail_id_attr::R
• extmem::l1_cache_acs_fail_int_clr::L1_CACHE_FAIL_INT_CLR_W
• extmem::l1_cache_acs_fail_int_clr::L1_ICACHE0_FAIL_INT_CLR_R
• extmem::l1_cache_acs_fail_int_clr::L1_ICACHE1_FAIL_INT_CLR_R
• extmem::l1_cache_acs_fail_int_clr::L1_ICACHE2_FAIL_INT_CLR_R
• extmem::l1_cache_acs_fail_int_clr::L1_ICACHE3_FAIL_INT_CLR_R
• extmem::l1_cache_acs_fail_int_clr::R
• extmem::l1_cache_acs_fail_int_clr::W
• extmem::l1_cache_acs_fail_int_ena::L1_CACHE_FAIL_INT_ENA_R
• extmem::l1_cache_acs_fail_int_ena::L1_CACHE_FAIL_INT_ENA_W
• extmem::l1_cache_acs_fail_int_ena::L1_ICACHE0_FAIL_INT_ENA_R
• extmem::l1_cache_acs_fail_int_ena::L1_ICACHE1_FAIL_INT_ENA_R
• extmem::l1_cache_acs_fail_int_ena::L1_ICACHE2_FAIL_INT_ENA_R
• extmem::l1_cache_acs_fail_int_ena::L1_ICACHE3_FAIL_INT_ENA_R
• extmem::l1_cache_acs_fail_int_ena::R
• extmem::l1_cache_acs_fail_int_ena::W
• extmem::l1_cache_acs_fail_int_raw::L1_CACHE_FAIL_INT_RAW_R
• extmem::l1_cache_acs_fail_int_raw::L1_CACHE_FAIL_INT_RAW_W
• extmem::l1_cache_acs_fail_int_raw::L1_ICACHE0_FAIL_INT_RAW_R
• extmem::l1_cache_acs_fail_int_raw::L1_ICACHE0_FAIL_INT_RAW_W
• extmem::l1_cache_acs_fail_int_raw::L1_ICACHE1_FAIL_INT_RAW_R
• extmem::l1_cache_acs_fail_int_raw::L1_ICACHE1_FAIL_INT_RAW_W
• extmem::l1_cache_acs_fail_int_raw::L1_ICACHE2_FAIL_INT_RAW_R
• extmem::l1_cache_acs_fail_int_raw::L1_ICACHE2_FAIL_INT_RAW_W
• extmem::l1_cache_acs_fail_int_raw::L1_ICACHE3_FAIL_INT_RAW_R
• extmem::l1_cache_acs_fail_int_raw::L1_ICACHE3_FAIL_INT_RAW_W
• extmem::l1_cache_acs_fail_int_raw::R
• extmem::l1_cache_acs_fail_int_raw::W
• extmem::l1_cache_acs_fail_int_st::L1_CACHE_FAIL_INT_ST_R
• extmem::l1_cache_acs_fail_int_st::L1_ICACHE0_FAIL_INT_ST_R
• extmem::l1_cache_acs_fail_int_st::L1_ICACHE1_FAIL_INT_ST_R
• extmem::l1_cache_acs_fail_int_st::L1_ICACHE2_FAIL_INT_ST_R
• extmem::l1_cache_acs_fail_int_st::L1_ICACHE3_FAIL_INT_ST_R
• extmem::l1_cache_acs_fail_int_st::R
• extmem::l1_cache_atomic_conf::L1_CACHE_ATOMIC_EN_R
• extmem::l1_cache_atomic_conf::R
• extmem::l1_cache_autoload_buf_clr_ctrl::L1_CACHE_ALD_BUF_CLR_R
• extmem::l1_cache_autoload_buf_clr_ctrl::L1_CACHE_ALD_BUF_CLR_W
• extmem::l1_cache_autoload_buf_clr_ctrl::L1_ICACHE0_ALD_BUF_CLR_R
• extmem::l1_cache_autoload_buf_clr_ctrl::L1_ICACHE1_ALD_BUF_CLR_R
• extmem::l1_cache_autoload_buf_clr_ctrl::L1_ICACHE2_ALD_BUF_CLR_R
• extmem::l1_cache_autoload_buf_clr_ctrl::L1_ICACHE3_ALD_BUF_CLR_R
• extmem::l1_cache_autoload_buf_clr_ctrl::R
• extmem::l1_cache_autoload_buf_clr_ctrl::W
• extmem::l1_cache_autoload_ctrl::L1_CACHE_AUTOLOAD_DONE_R
• extmem::l1_cache_autoload_ctrl::L1_CACHE_AUTOLOAD_ENA_R
• extmem::l1_cache_autoload_ctrl::L1_CACHE_AUTOLOAD_ENA_W
• extmem::l1_cache_autoload_ctrl::L1_CACHE_AUTOLOAD_ORDER_R
• extmem::l1_cache_autoload_ctrl::L1_CACHE_AUTOLOAD_ORDER_W
• extmem::l1_cache_autoload_ctrl::L1_CACHE_AUTOLOAD_RGID_R
• extmem::l1_cache_autoload_ctrl::L1_CACHE_AUTOLOAD_SCT0_ENA_R
• extmem::l1_cache_autoload_ctrl::L1_CACHE_AUTOLOAD_SCT0_ENA_W
• extmem::l1_cache_autoload_ctrl::L1_CACHE_AUTOLOAD_SCT1_ENA_R
• extmem::l1_cache_autoload_ctrl::L1_CACHE_AUTOLOAD_SCT1_ENA_W
• extmem::l1_cache_autoload_ctrl::L1_CACHE_AUTOLOAD_SCT2_ENA_R
• extmem::l1_cache_autoload_ctrl::L1_CACHE_AUTOLOAD_SCT3_ENA_R
• extmem::l1_cache_autoload_ctrl::L1_CACHE_AUTOLOAD_TRIGGER_MODE_R
• extmem::l1_cache_autoload_ctrl::L1_CACHE_AUTOLOAD_TRIGGER_MODE_W
• extmem::l1_cache_autoload_ctrl::R
• extmem::l1_cache_autoload_ctrl::W
• extmem::l1_cache_autoload_sct0_addr::L1_CACHE_AUTOLOAD_SCT0_ADDR_R
• extmem::l1_cache_autoload_sct0_addr::L1_CACHE_AUTOLOAD_SCT0_ADDR_W
• extmem::l1_cache_autoload_sct0_addr::R
• extmem::l1_cache_autoload_sct0_addr::W
• extmem::l1_cache_autoload_sct0_size::L1_CACHE_AUTOLOAD_SCT0_SIZE_R
• extmem::l1_cache_autoload_sct0_size::L1_CACHE_AUTOLOAD_SCT0_SIZE_W
• extmem::l1_cache_autoload_sct0_size::R
• extmem::l1_cache_autoload_sct0_size::W
• extmem::l1_cache_autoload_sct1_addr::L1_CACHE_AUTOLOAD_SCT1_ADDR_R
• extmem::l1_cache_autoload_sct1_addr::L1_CACHE_AUTOLOAD_SCT1_ADDR_W
• extmem::l1_cache_autoload_sct1_addr::R
• extmem::l1_cache_autoload_sct1_addr::W
• extmem::l1_cache_autoload_sct1_size::L1_CACHE_AUTOLOAD_SCT1_SIZE_R
• extmem::l1_cache_autoload_sct1_size::L1_CACHE_AUTOLOAD_SCT1_SIZE_W
• extmem::l1_cache_autoload_sct1_size::R
• extmem::l1_cache_autoload_sct1_size::W
• extmem::l1_cache_autoload_sct2_addr::L1_CACHE_AUTOLOAD_SCT2_ADDR_R
• extmem::l1_cache_autoload_sct2_addr::R
• extmem::l1_cache_autoload_sct2_size::L1_CACHE_AUTOLOAD_SCT2_SIZE_R
• extmem::l1_cache_autoload_sct2_size::R
• extmem::l1_cache_autoload_sct3_addr::L1_CACHE_AUTOLOAD_SCT3_ADDR_R
• extmem::l1_cache_autoload_sct3_addr::R
• extmem::l1_cache_autoload_sct3_size::L1_CACHE_AUTOLOAD_SCT3_SIZE_R
• extmem::l1_cache_autoload_sct3_size::R
• extmem::l1_cache_blocksize_conf::L1_CACHE_BLOCKSIZE_128_R
• extmem::l1_cache_blocksize_conf::L1_CACHE_BLOCKSIZE_16_R
• extmem::l1_cache_blocksize_conf::L1_CACHE_BLOCKSIZE_256_R
• extmem::l1_cache_blocksize_conf::L1_CACHE_BLOCKSIZE_32_R
• extmem::l1_cache_blocksize_conf::L1_CACHE_BLOCKSIZE_64_R
• extmem::l1_cache_blocksize_conf::L1_CACHE_BLOCKSIZE_8_R
• extmem::l1_cache_blocksize_conf::R
• extmem::l1_cache_cachesize_conf::L1_CACHE_CACHESIZE_1024K_R
• extmem::l1_cache_cachesize_conf::L1_CACHE_CACHESIZE_128K_R
• extmem::l1_cache_cachesize_conf::L1_CACHE_CACHESIZE_16K_R
• extmem::l1_cache_cachesize_conf::L1_CACHE_CACHESIZE_1K_R
• extmem::l1_cache_cachesize_conf::L1_CACHE_CACHESIZE_2048K_R
• extmem::l1_cache_cachesize_conf::L1_CACHE_CACHESIZE_256K_R
• extmem::l1_cache_cachesize_conf::L1_CACHE_CACHESIZE_2K_R
• extmem::l1_cache_cachesize_conf::L1_CACHE_CACHESIZE_32K_R
• extmem::l1_cache_cachesize_conf::L1_CACHE_CACHESIZE_4096K_R
• extmem::l1_cache_cachesize_conf::L1_CACHE_CACHESIZE_4K_R
• extmem::l1_cache_cachesize_conf::L1_CACHE_CACHESIZE_512K_R
• extmem::l1_cache_cachesize_conf::L1_CACHE_CACHESIZE_64K_R
• extmem::l1_cache_cachesize_conf::L1_CACHE_CACHESIZE_8K_R
• extmem::l1_cache_cachesize_conf::R
• extmem::l1_cache_ctrl::L1_CACHE_SHUT_BUS0_R
• extmem::l1_cache_ctrl::L1_CACHE_SHUT_BUS0_W
• extmem::l1_cache_ctrl::L1_CACHE_SHUT_BUS1_R
• extmem::l1_cache_ctrl::L1_CACHE_SHUT_BUS1_W
• extmem::l1_cache_ctrl::L1_CACHE_SHUT_DBUS2_R
• extmem::l1_cache_ctrl::L1_CACHE_SHUT_DBUS3_R
• extmem::l1_cache_ctrl::L1_CACHE_SHUT_DMA_R
• extmem::l1_cache_ctrl::L1_CACHE_UNDEF_OP_R
• extmem::l1_cache_ctrl::L1_CACHE_UNDEF_OP_W
• extmem::l1_cache_ctrl::R
• extmem::l1_cache_ctrl::W
• extmem::l1_cache_data_mem_acs_conf::L1_CACHE_DATA_MEM_RD_EN_R
• extmem::l1_cache_data_mem_acs_conf::L1_CACHE_DATA_MEM_RD_EN_W
• extmem::l1_cache_data_mem_acs_conf::L1_CACHE_DATA_MEM_WR_EN_R
• extmem::l1_cache_data_mem_acs_conf::L1_CACHE_DATA_MEM_WR_EN_W
• extmem::l1_cache_data_mem_acs_conf::L1_ICACHE0_DATA_MEM_RD_EN_R
• extmem::l1_cache_data_mem_acs_conf::L1_ICACHE0_DATA_MEM_WR_EN_R
• extmem::l1_cache_data_mem_acs_conf::L1_ICACHE1_DATA_MEM_RD_EN_R
• extmem::l1_cache_data_mem_acs_conf::L1_ICACHE1_DATA_MEM_WR_EN_R
• extmem::l1_cache_data_mem_acs_conf::L1_ICACHE2_DATA_MEM_RD_EN_R
• extmem::l1_cache_data_mem_acs_conf::L1_ICACHE2_DATA_MEM_WR_EN_R
• extmem::l1_cache_data_mem_acs_conf::L1_ICACHE3_DATA_MEM_RD_EN_R
• extmem::l1_cache_data_mem_acs_conf::L1_ICACHE3_DATA_MEM_WR_EN_R
• extmem::l1_cache_data_mem_acs_conf::R
• extmem::l1_cache_data_mem_acs_conf::W
• extmem::l1_cache_data_mem_power_ctrl::L1_CACHE_DATA_MEM_FORCE_ON_R
• extmem::l1_cache_data_mem_power_ctrl::L1_CACHE_DATA_MEM_FORCE_ON_W
• extmem::l1_cache_data_mem_power_ctrl::L1_CACHE_DATA_MEM_FORCE_PD_R
• extmem::l1_cache_data_mem_power_ctrl::L1_CACHE_DATA_MEM_FORCE_PD_W
• extmem::l1_cache_data_mem_power_ctrl::L1_CACHE_DATA_MEM_FORCE_PU_R
• extmem::l1_cache_data_mem_power_ctrl::L1_CACHE_DATA_MEM_FORCE_PU_W
• extmem::l1_cache_data_mem_power_ctrl::L1_ICACHE0_DATA_MEM_FORCE_ON_R
• extmem::l1_cache_data_mem_power_ctrl::L1_ICACHE0_DATA_MEM_FORCE_PD_R
• extmem::l1_cache_data_mem_power_ctrl::L1_ICACHE0_DATA_MEM_FORCE_PU_R
• extmem::l1_cache_data_mem_power_ctrl::L1_ICACHE1_DATA_MEM_FORCE_ON_R
• extmem::l1_cache_data_mem_power_ctrl::L1_ICACHE1_DATA_MEM_FORCE_PD_R
• extmem::l1_cache_data_mem_power_ctrl::L1_ICACHE1_DATA_MEM_FORCE_PU_R
• extmem::l1_cache_data_mem_power_ctrl::L1_ICACHE2_DATA_MEM_FORCE_ON_R
• extmem::l1_cache_data_mem_power_ctrl::L1_ICACHE2_DATA_MEM_FORCE_PD_R
• extmem::l1_cache_data_mem_power_ctrl::L1_ICACHE2_DATA_MEM_FORCE_PU_R
• extmem::l1_cache_data_mem_power_ctrl::L1_ICACHE3_DATA_MEM_FORCE_ON_R
• extmem::l1_cache_data_mem_power_ctrl::L1_ICACHE3_DATA_MEM_FORCE_PD_R
• extmem::l1_cache_data_mem_power_ctrl::L1_ICACHE3_DATA_MEM_FORCE_PU_R
• extmem::l1_cache_data_mem_power_ctrl::R
• extmem::l1_cache_data_mem_power_ctrl::W
• extmem::l1_cache_debug_bus::L1_CACHE_DEBUG_BUS_R
• extmem::l1_cache_debug_bus::L1_CACHE_DEBUG_BUS_W
• extmem::l1_cache_debug_bus::R
• extmem::l1_cache_debug_bus::W
• extmem::l1_cache_freeze_ctrl::L1_CACHE_FREEZE_DONE_R
• extmem::l1_cache_freeze_ctrl::L1_CACHE_FREEZE_EN_R
• extmem::l1_cache_freeze_ctrl::L1_CACHE_FREEZE_EN_W
• extmem::l1_cache_freeze_ctrl::L1_CACHE_FREEZE_MODE_R
• extmem::l1_cache_freeze_ctrl::L1_CACHE_FREEZE_MODE_W
• extmem::l1_cache_freeze_ctrl::L1_ICACHE0_FREEZE_DONE_R
• extmem::l1_cache_freeze_ctrl::L1_ICACHE0_FREEZE_EN_R
• extmem::l1_cache_freeze_ctrl::L1_ICACHE0_FREEZE_MODE_R
• extmem::l1_cache_freeze_ctrl::L1_ICACHE1_FREEZE_DONE_R
• extmem::l1_cache_freeze_ctrl::L1_ICACHE1_FREEZE_EN_R
• extmem::l1_cache_freeze_ctrl::L1_ICACHE1_FREEZE_MODE_R
• extmem::l1_cache_freeze_ctrl::L1_ICACHE2_FREEZE_DONE_R
• extmem::l1_cache_freeze_ctrl::L1_ICACHE2_FREEZE_EN_R
• extmem::l1_cache_freeze_ctrl::L1_ICACHE2_FREEZE_MODE_R
• extmem::l1_cache_freeze_ctrl::L1_ICACHE3_FREEZE_DONE_R
• extmem::l1_cache_freeze_ctrl::L1_ICACHE3_FREEZE_EN_R
• extmem::l1_cache_freeze_ctrl::L1_ICACHE3_FREEZE_MODE_R
• extmem::l1_cache_freeze_ctrl::R
• extmem::l1_cache_freeze_ctrl::W
• extmem::l1_cache_object_ctrl::L1_CACHE_MEM_OBJECT_R
• extmem::l1_cache_object_ctrl::L1_CACHE_MEM_OBJECT_W
• extmem::l1_cache_object_ctrl::L1_CACHE_TAG_OBJECT_R
• extmem::l1_cache_object_ctrl::L1_CACHE_TAG_OBJECT_W
• extmem::l1_cache_object_ctrl::L1_ICACHE0_MEM_OBJECT_R
• extmem::l1_cache_object_ctrl::L1_ICACHE0_TAG_OBJECT_R
• extmem::l1_cache_object_ctrl::L1_ICACHE1_MEM_OBJECT_R
• extmem::l1_cache_object_ctrl::L1_ICACHE1_TAG_OBJECT_R
• extmem::l1_cache_object_ctrl::L1_ICACHE2_MEM_OBJECT_R
• extmem::l1_cache_object_ctrl::L1_ICACHE2_TAG_OBJECT_R
• extmem::l1_cache_object_ctrl::L1_ICACHE3_MEM_OBJECT_R
• extmem::l1_cache_object_ctrl::L1_ICACHE3_TAG_OBJECT_R
• extmem::l1_cache_object_ctrl::R
• extmem::l1_cache_object_ctrl::W
• extmem::l1_cache_preload_ctrl::L1_CACHE_PRELOAD_DONE_R
• extmem::l1_cache_preload_ctrl::L1_CACHE_PRELOAD_ENA_R
• extmem::l1_cache_preload_ctrl::L1_CACHE_PRELOAD_ENA_W
• extmem::l1_cache_preload_ctrl::L1_CACHE_PRELOAD_ORDER_R
• extmem::l1_cache_preload_ctrl::L1_CACHE_PRELOAD_ORDER_W
• extmem::l1_cache_preload_ctrl::L1_CACHE_PRELOAD_RGID_R
• extmem::l1_cache_preload_ctrl::R
• extmem::l1_cache_preload_ctrl::W
• extmem::l1_cache_preload_rst_ctrl::L1_CACHE_PLD_RST_R
• extmem::l1_cache_preload_rst_ctrl::L1_CACHE_PLD_RST_W
• extmem::l1_cache_preload_rst_ctrl::L1_ICACHE0_PLD_RST_R
• extmem::l1_cache_preload_rst_ctrl::L1_ICACHE1_PLD_RST_R
• extmem::l1_cache_preload_rst_ctrl::L1_ICACHE2_PLD_RST_R
• extmem::l1_cache_preload_rst_ctrl::L1_ICACHE3_PLD_RST_R
• extmem::l1_cache_preload_rst_ctrl::R
• extmem::l1_cache_preload_rst_ctrl::W
• extmem::l1_cache_prelock_conf::L1_CACHE_PRELOCK_RGID_R
• extmem::l1_cache_prelock_conf::L1_CACHE_PRELOCK_SCT0_EN_R
• extmem::l1_cache_prelock_conf::L1_CACHE_PRELOCK_SCT0_EN_W
• extmem::l1_cache_prelock_conf::L1_CACHE_PRELOCK_SCT1_EN_R
• extmem::l1_cache_prelock_conf::L1_CACHE_PRELOCK_SCT1_EN_W
• extmem::l1_cache_prelock_conf::R
• extmem::l1_cache_prelock_conf::W
• extmem::l1_cache_prelock_sct0_addr::L1_CACHE_PRELOCK_SCT0_ADDR_R
• extmem::l1_cache_prelock_sct0_addr::L1_CACHE_PRELOCK_SCT0_ADDR_W
• extmem::l1_cache_prelock_sct0_addr::R
• extmem::l1_cache_prelock_sct0_addr::W
• extmem::l1_cache_sync_preload_exception::CACHE_SYNC_ERR_CODE_R
• extmem::l1_cache_sync_preload_exception::L1_CACHE_PLD_ERR_CODE_R
• extmem::l1_cache_sync_preload_exception::L1_ICACHE0_PLD_ERR_CODE_R
• extmem::l1_cache_sync_preload_exception::L1_ICACHE1_PLD_ERR_CODE_R
• extmem::l1_cache_sync_preload_exception::L1_ICACHE2_PLD_ERR_CODE_R
• extmem::l1_cache_sync_preload_exception::L1_ICACHE3_PLD_ERR_CODE_R
• extmem::l1_cache_sync_preload_exception::R
• extmem::l1_cache_sync_preload_int_clr::CACHE_SYNC_DONE_INT_CLR_W
• extmem::l1_cache_sync_preload_int_clr::CACHE_SYNC_ERR_INT_CLR_W
• extmem::l1_cache_sync_preload_int_clr::L1_CACHE_PLD_DONE_INT_CLR_W
• extmem::l1_cache_sync_preload_int_clr::L1_CACHE_PLD_ERR_INT_CLR_W
• extmem::l1_cache_sync_preload_int_clr::L1_ICACHE0_PLD_DONE_INT_CLR_R
• extmem::l1_cache_sync_preload_int_clr::L1_ICACHE0_PLD_ERR_INT_CLR_R
• extmem::l1_cache_sync_preload_int_clr::L1_ICACHE1_PLD_DONE_INT_CLR_R
• extmem::l1_cache_sync_preload_int_clr::L1_ICACHE1_PLD_ERR_INT_CLR_R
• extmem::l1_cache_sync_preload_int_clr::L1_ICACHE2_PLD_DONE_INT_CLR_R
• extmem::l1_cache_sync_preload_int_clr::L1_ICACHE2_PLD_ERR_INT_CLR_R
• extmem::l1_cache_sync_preload_int_clr::L1_ICACHE3_PLD_DONE_INT_CLR_R
• extmem::l1_cache_sync_preload_int_clr::L1_ICACHE3_PLD_ERR_INT_CLR_R
• extmem::l1_cache_sync_preload_int_clr::R
• extmem::l1_cache_sync_preload_int_clr::W
• extmem::l1_cache_sync_preload_int_ena::CACHE_SYNC_DONE_INT_ENA_R
• extmem::l1_cache_sync_preload_int_ena::CACHE_SYNC_DONE_INT_ENA_W
• extmem::l1_cache_sync_preload_int_ena::CACHE_SYNC_ERR_INT_ENA_R
• extmem::l1_cache_sync_preload_int_ena::CACHE_SYNC_ERR_INT_ENA_W
• extmem::l1_cache_sync_preload_int_ena::L1_CACHE_PLD_DONE_INT_ENA_R
• extmem::l1_cache_sync_preload_int_ena::L1_CACHE_PLD_DONE_INT_ENA_W
• extmem::l1_cache_sync_preload_int_ena::L1_CACHE_PLD_ERR_INT_ENA_R
• extmem::l1_cache_sync_preload_int_ena::L1_CACHE_PLD_ERR_INT_ENA_W
• extmem::l1_cache_sync_preload_int_ena::L1_ICACHE0_PLD_DONE_INT_ENA_R
• extmem::l1_cache_sync_preload_int_ena::L1_ICACHE0_PLD_ERR_INT_ENA_R
• extmem::l1_cache_sync_preload_int_ena::L1_ICACHE1_PLD_DONE_INT_ENA_R
• extmem::l1_cache_sync_preload_int_ena::L1_ICACHE1_PLD_ERR_INT_ENA_R
• extmem::l1_cache_sync_preload_int_ena::L1_ICACHE2_PLD_DONE_INT_ENA_R
• extmem::l1_cache_sync_preload_int_ena::L1_ICACHE2_PLD_ERR_INT_ENA_R
• extmem::l1_cache_sync_preload_int_ena::L1_ICACHE3_PLD_DONE_INT_ENA_R
• extmem::l1_cache_sync_preload_int_ena::L1_ICACHE3_PLD_ERR_INT_ENA_R
• extmem::l1_cache_sync_preload_int_ena::R
• extmem::l1_cache_sync_preload_int_ena::W
• extmem::l1_cache_sync_preload_int_raw::CACHE_SYNC_DONE_INT_RAW_R
• extmem::l1_cache_sync_preload_int_raw::CACHE_SYNC_DONE_INT_RAW_W
• extmem::l1_cache_sync_preload_int_raw::CACHE_SYNC_ERR_INT_RAW_R
• extmem::l1_cache_sync_preload_int_raw::CACHE_SYNC_ERR_INT_RAW_W
• extmem::l1_cache_sync_preload_int_raw::L1_CACHE_PLD_DONE_INT_RAW_R
• extmem::l1_cache_sync_preload_int_raw::L1_CACHE_PLD_DONE_INT_RAW_W
• extmem::l1_cache_sync_preload_int_raw::L1_CACHE_PLD_ERR_INT_RAW_R
• extmem::l1_cache_sync_preload_int_raw::L1_CACHE_PLD_ERR_INT_RAW_W
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE0_PLD_DONE_INT_RAW_R
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE0_PLD_DONE_INT_RAW_W
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE0_PLD_ERR_INT_RAW_R
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE0_PLD_ERR_INT_RAW_W
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE1_PLD_DONE_INT_RAW_R
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE1_PLD_DONE_INT_RAW_W
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE1_PLD_ERR_INT_RAW_R
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE1_PLD_ERR_INT_RAW_W
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE2_PLD_DONE_INT_RAW_R
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE2_PLD_DONE_INT_RAW_W
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE2_PLD_ERR_INT_RAW_R
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE2_PLD_ERR_INT_RAW_W
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE3_PLD_DONE_INT_RAW_R
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE3_PLD_DONE_INT_RAW_W
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE3_PLD_ERR_INT_RAW_R
• extmem::l1_cache_sync_preload_int_raw::L1_ICACHE3_PLD_ERR_INT_RAW_W
• extmem::l1_cache_sync_preload_int_raw::R
• extmem::l1_cache_sync_preload_int_raw::W
• extmem::l1_cache_sync_preload_int_st::CACHE_SYNC_DONE_INT_ST_R
• extmem::l1_cache_sync_preload_int_st::CACHE_SYNC_ERR_INT_ST_R
• extmem::l1_cache_sync_preload_int_st::L1_CACHE_PLD_DONE_INT_ST_R
• extmem::l1_cache_sync_preload_int_st::L1_CACHE_PLD_ERR_INT_ST_R
• extmem::l1_cache_sync_preload_int_st::L1_ICACHE0_PLD_DONE_INT_ST_R
• extmem::l1_cache_sync_preload_int_st::L1_ICACHE0_PLD_ERR_INT_ST_R
• extmem::l1_cache_sync_preload_int_st::L1_ICACHE1_PLD_DONE_INT_ST_R
• extmem::l1_cache_sync_preload_int_st::L1_ICACHE1_PLD_ERR_INT_ST_R
• extmem::l1_cache_sync_preload_int_st::L1_ICACHE2_PLD_DONE_INT_ST_R
• extmem::l1_cache_sync_preload_int_st::L1_ICACHE2_PLD_ERR_INT_ST_R
• extmem::l1_cache_sync_preload_int_st::L1_ICACHE3_PLD_DONE_INT_ST_R
• extmem::l1_cache_sync_preload_int_st::L1_ICACHE3_PLD_ERR_INT_ST_R
• extmem::l1_cache_sync_preload_int_st::R
• extmem::l1_cache_sync_rst_ctrl::L1_CACHE_SYNC_RST_R
• extmem::l1_cache_sync_rst_ctrl::L1_CACHE_SYNC_RST_W
• extmem::l1_cache_sync_rst_ctrl::L1_ICACHE0_SYNC_RST_R
• extmem::l1_cache_sync_rst_ctrl::L1_ICACHE1_SYNC_RST_R
• extmem::l1_cache_sync_rst_ctrl::L1_ICACHE2_SYNC_RST_R
• extmem::l1_cache_sync_rst_ctrl::L1_ICACHE3_SYNC_RST_R
• extmem::l1_cache_sync_rst_ctrl::R
• extmem::l1_cache_sync_rst_ctrl::W
• extmem::l1_cache_tag_mem_acs_conf::L1_CACHE_TAG_MEM_RD_EN_R
• extmem::l1_cache_tag_mem_acs_conf::L1_CACHE_TAG_MEM_RD_EN_W
• extmem::l1_cache_tag_mem_acs_conf::L1_CACHE_TAG_MEM_WR_EN_R
• extmem::l1_cache_tag_mem_acs_conf::L1_CACHE_TAG_MEM_WR_EN_W
• extmem::l1_cache_tag_mem_acs_conf::L1_ICACHE0_TAG_MEM_RD_EN_R
• extmem::l1_cache_tag_mem_acs_conf::L1_ICACHE0_TAG_MEM_WR_EN_R
• extmem::l1_cache_tag_mem_acs_conf::L1_ICACHE1_TAG_MEM_RD_EN_R
• extmem::l1_cache_tag_mem_acs_conf::L1_ICACHE1_TAG_MEM_WR_EN_R
• extmem::l1_cache_tag_mem_acs_conf::L1_ICACHE2_TAG_MEM_RD_EN_R
• extmem::l1_cache_tag_mem_acs_conf::L1_ICACHE2_TAG_MEM_WR_EN_R
• extmem::l1_cache_tag_mem_acs_conf::L1_ICACHE3_TAG_MEM_RD_EN_R
• extmem::l1_cache_tag_mem_acs_conf::L1_ICACHE3_TAG_MEM_WR_EN_R
• extmem::l1_cache_tag_mem_acs_conf::R
• extmem::l1_cache_tag_mem_acs_conf::W
• extmem::l1_cache_tag_mem_power_ctrl::L1_CACHE_TAG_MEM_FORCE_ON_R
• extmem::l1_cache_tag_mem_power_ctrl::L1_CACHE_TAG_MEM_FORCE_ON_W
• extmem::l1_cache_tag_mem_power_ctrl::L1_CACHE_TAG_MEM_FORCE_PD_R
• extmem::l1_cache_tag_mem_power_ctrl::L1_CACHE_TAG_MEM_FORCE_PD_W
• extmem::l1_cache_tag_mem_power_ctrl::L1_CACHE_TAG_MEM_FORCE_PU_R
• extmem::l1_cache_tag_mem_power_ctrl::L1_CACHE_TAG_MEM_FORCE_PU_W
• extmem::l1_cache_tag_mem_power_ctrl::L1_ICACHE0_TAG_MEM_FORCE_ON_R
• extmem::l1_cache_tag_mem_power_ctrl::L1_ICACHE0_TAG_MEM_FORCE_PD_R
• extmem::l1_cache_tag_mem_power_ctrl::L1_ICACHE0_TAG_MEM_FORCE_PU_R
• extmem::l1_cache_tag_mem_power_ctrl::L1_ICACHE1_TAG_MEM_FORCE_ON_R
• extmem::l1_cache_tag_mem_power_ctrl::L1_ICACHE1_TAG_MEM_FORCE_PD_R
• extmem::l1_cache_tag_mem_power_ctrl::L1_ICACHE1_TAG_MEM_FORCE_PU_R
• extmem::l1_cache_tag_mem_power_ctrl::L1_ICACHE2_TAG_MEM_FORCE_ON_R
• extmem::l1_cache_tag_mem_power_ctrl::L1_ICACHE2_TAG_MEM_FORCE_PD_R
• extmem::l1_cache_tag_mem_power_ctrl::L1_ICACHE2_TAG_MEM_FORCE_PU_R
• extmem::l1_cache_tag_mem_power_ctrl::L1_ICACHE3_TAG_MEM_FORCE_ON_R
• extmem::l1_cache_tag_mem_power_ctrl::L1_ICACHE3_TAG_MEM_FORCE_PD_R
• extmem::l1_cache_tag_mem_power_ctrl::L1_ICACHE3_TAG_MEM_FORCE_PU_R
• extmem::l1_cache_tag_mem_power_ctrl::R
• extmem::l1_cache_tag_mem_power_ctrl::W
• extmem::l1_cache_vaddr::L1_CACHE_VADDR_R
• extmem::l1_cache_vaddr::L1_CACHE_VADDR_W
• extmem::l1_cache_vaddr::R
• extmem::l1_cache_vaddr::W
• extmem::l1_cache_way_object::L1_CACHE_WAY_OBJECT_R
• extmem::l1_cache_way_object::L1_CACHE_WAY_OBJECT_W
• extmem::l1_cache_way_object::R
• extmem::l1_cache_way_object::W
• extmem::l1_cache_wrap_around_ctrl::L1_CACHE_WRAP_R
• extmem::l1_cache_wrap_around_ctrl::L1_CACHE_WRAP_W
• extmem::l1_cache_wrap_around_ctrl::L1_ICACHE0_WRAP_R
• extmem::l1_cache_wrap_around_ctrl::L1_ICACHE1_WRAP_R
• extmem::l1_cache_wrap_around_ctrl::L1_ICACHE2_WRAP_R
• extmem::l1_cache_wrap_around_ctrl::L1_ICACHE3_WRAP_R
• extmem::l1_cache_wrap_around_ctrl::R
• extmem::l1_cache_wrap_around_ctrl::W
• extmem::l1_dbus2_acs_conflict_cnt::L1_DBUS2_CONFLICT_CNT_R
• extmem::l1_dbus2_acs_conflict_cnt::R
• extmem::l1_dbus2_acs_hit_cnt::L1_DBUS2_HIT_CNT_R
• extmem::l1_dbus2_acs_hit_cnt::R
• extmem::l1_dbus2_acs_miss_cnt::L1_DBUS2_MISS_CNT_R
• extmem::l1_dbus2_acs_miss_cnt::R
• extmem::l1_dbus2_acs_nxtlvl_cnt::L1_DBUS2_NXTLVL_CNT_R
• extmem::l1_dbus2_acs_nxtlvl_cnt::R
• extmem::l1_dbus3_acs_conflict_cnt::L1_DBUS3_CONFLICT_CNT_R
• extmem::l1_dbus3_acs_conflict_cnt::R
• extmem::l1_dbus3_acs_hit_cnt::L1_DBUS3_HIT_CNT_R
• extmem::l1_dbus3_acs_hit_cnt::R
• extmem::l1_dbus3_acs_miss_cnt::L1_DBUS3_MISS_CNT_R
• extmem::l1_dbus3_acs_miss_cnt::R
• extmem::l1_dbus3_acs_nxtlvl_cnt::L1_DBUS3_NXTLVL_CNT_R
• extmem::l1_dbus3_acs_nxtlvl_cnt::R
• extmem::l1_dcache_acs_fail_addr::L1_CACHE_FAIL_ADDR_R
• extmem::l1_dcache_acs_fail_addr::R
• extmem::l1_dcache_preload_addr::L1_CACHE_PRELOAD_ADDR_R
• extmem::l1_dcache_preload_addr::L1_CACHE_PRELOAD_ADDR_W
• extmem::l1_dcache_preload_addr::R
• extmem::l1_dcache_preload_addr::W
• extmem::l1_dcache_preload_size::L1_CACHE_PRELOAD_SIZE_R
• extmem::l1_dcache_preload_size::L1_CACHE_PRELOAD_SIZE_W
• extmem::l1_dcache_preload_size::R
• extmem::l1_dcache_preload_size::W
• extmem::l1_dcache_prelock_sct1_addr::L1_CACHE_PRELOCK_SCT1_ADDR_R
• extmem::l1_dcache_prelock_sct1_addr::L1_CACHE_PRELOCK_SCT1_ADDR_W
• extmem::l1_dcache_prelock_sct1_addr::R
• extmem::l1_dcache_prelock_sct1_addr::W
• extmem::l1_dcache_prelock_sct_size::L1_CACHE_PRELOCK_SCT0_SIZE_R
• extmem::l1_dcache_prelock_sct_size::L1_CACHE_PRELOCK_SCT0_SIZE_W
• extmem::l1_dcache_prelock_sct_size::L1_CACHE_PRELOCK_SCT1_SIZE_R
• extmem::l1_dcache_prelock_sct_size::L1_CACHE_PRELOCK_SCT1_SIZE_W
• extmem::l1_dcache_prelock_sct_size::R
• extmem::l1_dcache_prelock_sct_size::W
• extmem::l1_ibus0_acs_conflict_cnt::L1_IBUS0_CONFLICT_CNT_R
• extmem::l1_ibus0_acs_conflict_cnt::R
• extmem::l1_ibus0_acs_hit_cnt::L1_IBUS0_HIT_CNT_R
• extmem::l1_ibus0_acs_hit_cnt::R
• extmem::l1_ibus0_acs_miss_cnt::L1_IBUS0_MISS_CNT_R
• extmem::l1_ibus0_acs_miss_cnt::R
• extmem::l1_ibus0_acs_nxtlvl_cnt::L1_IBUS0_NXTLVL_CNT_R
• extmem::l1_ibus0_acs_nxtlvl_cnt::R
• extmem::l1_ibus1_acs_conflict_cnt::L1_IBUS1_CONFLICT_CNT_R
• extmem::l1_ibus1_acs_conflict_cnt::R
• extmem::l1_ibus1_acs_hit_cnt::L1_IBUS1_HIT_CNT_R
• extmem::l1_ibus1_acs_hit_cnt::R
• extmem::l1_ibus1_acs_miss_cnt::L1_IBUS1_MISS_CNT_R
• extmem::l1_ibus1_acs_miss_cnt::R
• extmem::l1_ibus1_acs_nxtlvl_cnt::L1_IBUS1_NXTLVL_CNT_R
• extmem::l1_ibus1_acs_nxtlvl_cnt::R
• extmem::l1_ibus2_acs_conflict_cnt::L1_IBUS2_CONFLICT_CNT_R
• extmem::l1_ibus2_acs_conflict_cnt::R
• extmem::l1_ibus2_acs_hit_cnt::L1_IBUS2_HIT_CNT_R
• extmem::l1_ibus2_acs_hit_cnt::R
• extmem::l1_ibus2_acs_miss_cnt::L1_IBUS2_MISS_CNT_R
• extmem::l1_ibus2_acs_miss_cnt::R
• extmem::l1_ibus2_acs_nxtlvl_cnt::L1_IBUS2_NXTLVL_CNT_R
• extmem::l1_ibus2_acs_nxtlvl_cnt::R
• extmem::l1_ibus3_acs_conflict_cnt::L1_IBUS3_CONFLICT_CNT_R
• extmem::l1_ibus3_acs_conflict_cnt::R
• extmem::l1_ibus3_acs_hit_cnt::L1_IBUS3_HIT_CNT_R
• extmem::l1_ibus3_acs_hit_cnt::R
• extmem::l1_ibus3_acs_miss_cnt::L1_IBUS3_MISS_CNT_R
• extmem::l1_ibus3_acs_miss_cnt::R
• extmem::l1_ibus3_acs_nxtlvl_cnt::L1_IBUS3_NXTLVL_CNT_R
• extmem::l1_ibus3_acs_nxtlvl_cnt::R
• extmem::l1_icache0_acs_fail_addr::L1_ICACHE0_FAIL_ADDR_R
• extmem::l1_icache0_acs_fail_addr::R
• extmem::l1_icache0_acs_fail_id_attr::L1_ICACHE0_FAIL_ATTR_R
• extmem::l1_icache0_acs_fail_id_attr::L1_ICACHE0_FAIL_ID_R
• extmem::l1_icache0_acs_fail_id_attr::R
• extmem::l1_icache0_autoload_ctrl::L1_ICACHE0_AUTOLOAD_DONE_R
• extmem::l1_icache0_autoload_ctrl::L1_ICACHE0_AUTOLOAD_ENA_R
• extmem::l1_icache0_autoload_ctrl::L1_ICACHE0_AUTOLOAD_ORDER_R
• extmem::l1_icache0_autoload_ctrl::L1_ICACHE0_AUTOLOAD_RGID_R
• extmem::l1_icache0_autoload_ctrl::L1_ICACHE0_AUTOLOAD_SCT0_ENA_R
• extmem::l1_icache0_autoload_ctrl::L1_ICACHE0_AUTOLOAD_SCT1_ENA_R
• extmem::l1_icache0_autoload_ctrl::L1_ICACHE0_AUTOLOAD_TRIGGER_MODE_R
• extmem::l1_icache0_autoload_ctrl::R
• extmem::l1_icache0_autoload_sct0_addr::L1_ICACHE0_AUTOLOAD_SCT0_ADDR_R
• extmem::l1_icache0_autoload_sct0_addr::R
• extmem::l1_icache0_autoload_sct0_size::L1_ICACHE0_AUTOLOAD_SCT0_SIZE_R
• extmem::l1_icache0_autoload_sct0_size::R
• extmem::l1_icache0_autoload_sct1_addr::L1_ICACHE0_AUTOLOAD_SCT1_ADDR_R
• extmem::l1_icache0_autoload_sct1_addr::R
• extmem::l1_icache0_autoload_sct1_size::L1_ICACHE0_AUTOLOAD_SCT1_SIZE_R
• extmem::l1_icache0_autoload_sct1_size::R
• extmem::l1_icache0_preload_addr::L1_ICACHE0_PRELOAD_ADDR_R
• extmem::l1_icache0_preload_addr::R
• extmem::l1_icache0_preload_ctrl::L1_ICACHE0_PRELOAD_DONE_R
• extmem::l1_icache0_preload_ctrl::L1_ICACHE0_PRELOAD_ENA_R
• extmem::l1_icache0_preload_ctrl::L1_ICACHE0_PRELOAD_ENA_W
• extmem::l1_icache0_preload_ctrl::L1_ICACHE0_PRELOAD_ORDER_R
• extmem::l1_icache0_preload_ctrl::L1_ICACHE0_PRELOAD_RGID_R
• extmem::l1_icache0_preload_ctrl::R
• extmem::l1_icache0_preload_ctrl::W
• extmem::l1_icache0_preload_size::L1_ICACHE0_PRELOAD_SIZE_R
• extmem::l1_icache0_preload_size::R
• extmem::l1_icache0_prelock_conf::L1_ICACHE0_PRELOCK_RGID_R
• extmem::l1_icache0_prelock_conf::L1_ICACHE0_PRELOCK_SCT0_EN_R
• extmem::l1_icache0_prelock_conf::L1_ICACHE0_PRELOCK_SCT1_EN_R
• extmem::l1_icache0_prelock_conf::R
• extmem::l1_icache0_prelock_sct0_addr::L1_ICACHE0_PRELOCK_SCT0_ADDR_R
• extmem::l1_icache0_prelock_sct0_addr::R
• extmem::l1_icache0_prelock_sct1_addr::L1_ICACHE0_PRELOCK_SCT1_ADDR_R
• extmem::l1_icache0_prelock_sct1_addr::R
• extmem::l1_icache0_prelock_sct_size::L1_ICACHE0_PRELOCK_SCT0_SIZE_R
• extmem::l1_icache0_prelock_sct_size::L1_ICACHE0_PRELOCK_SCT1_SIZE_R
• extmem::l1_icache0_prelock_sct_size::R
• extmem::l1_icache1_acs_fail_addr::L1_ICACHE1_FAIL_ADDR_R
• extmem::l1_icache1_acs_fail_addr::R
• extmem::l1_icache1_acs_fail_id_attr::L1_ICACHE1_FAIL_ATTR_R
• extmem::l1_icache1_acs_fail_id_attr::L1_ICACHE1_FAIL_ID_R
• extmem::l1_icache1_acs_fail_id_attr::R
• extmem::l1_icache1_autoload_ctrl::L1_ICACHE1_AUTOLOAD_DONE_R
• extmem::l1_icache1_autoload_ctrl::L1_ICACHE1_AUTOLOAD_ENA_R
• extmem::l1_icache1_autoload_ctrl::L1_ICACHE1_AUTOLOAD_ORDER_R
• extmem::l1_icache1_autoload_ctrl::L1_ICACHE1_AUTOLOAD_RGID_R
• extmem::l1_icache1_autoload_ctrl::L1_ICACHE1_AUTOLOAD_SCT0_ENA_R
• extmem::l1_icache1_autoload_ctrl::L1_ICACHE1_AUTOLOAD_SCT1_ENA_R
• extmem::l1_icache1_autoload_ctrl::L1_ICACHE1_AUTOLOAD_TRIGGER_MODE_R
• extmem::l1_icache1_autoload_ctrl::R
• extmem::l1_icache1_autoload_sct0_addr::L1_ICACHE1_AUTOLOAD_SCT0_ADDR_R
• extmem::l1_icache1_autoload_sct0_addr::R
• extmem::l1_icache1_autoload_sct0_size::L1_ICACHE1_AUTOLOAD_SCT0_SIZE_R
• extmem::l1_icache1_autoload_sct0_size::R
• extmem::l1_icache1_autoload_sct1_addr::L1_ICACHE1_AUTOLOAD_SCT1_ADDR_R
• extmem::l1_icache1_autoload_sct1_addr::R
• extmem::l1_icache1_autoload_sct1_size::L1_ICACHE1_AUTOLOAD_SCT1_SIZE_R
• extmem::l1_icache1_autoload_sct1_size::R
• extmem::l1_icache1_preload_addr::L1_ICACHE1_PRELOAD_ADDR_R
• extmem::l1_icache1_preload_addr::R
• extmem::l1_icache1_preload_ctrl::L1_ICACHE1_PRELOAD_DONE_R
• extmem::l1_icache1_preload_ctrl::L1_ICACHE1_PRELOAD_ENA_R
• extmem::l1_icache1_preload_ctrl::L1_ICACHE1_PRELOAD_ENA_W
• extmem::l1_icache1_preload_ctrl::L1_ICACHE1_PRELOAD_ORDER_R
• extmem::l1_icache1_preload_ctrl::L1_ICACHE1_PRELOAD_RGID_R
• extmem::l1_icache1_preload_ctrl::R
• extmem::l1_icache1_preload_ctrl::W
• extmem::l1_icache1_preload_size::L1_ICACHE1_PRELOAD_SIZE_R
• extmem::l1_icache1_preload_size::R
• extmem::l1_icache1_prelock_conf::L1_ICACHE1_PRELOCK_RGID_R
• extmem::l1_icache1_prelock_conf::L1_ICACHE1_PRELOCK_SCT0_EN_R
• extmem::l1_icache1_prelock_conf::L1_ICACHE1_PRELOCK_SCT1_EN_R
• extmem::l1_icache1_prelock_conf::R
• extmem::l1_icache1_prelock_sct0_addr::L1_ICACHE1_PRELOCK_SCT0_ADDR_R
• extmem::l1_icache1_prelock_sct0_addr::R
• extmem::l1_icache1_prelock_sct1_addr::L1_ICACHE1_PRELOCK_SCT1_ADDR_R
• extmem::l1_icache1_prelock_sct1_addr::R
• extmem::l1_icache1_prelock_sct_size::L1_ICACHE1_PRELOCK_SCT0_SIZE_R
• extmem::l1_icache1_prelock_sct_size::L1_ICACHE1_PRELOCK_SCT1_SIZE_R
• extmem::l1_icache1_prelock_sct_size::R
• extmem::l1_icache2_acs_fail_addr::L1_ICACHE2_FAIL_ADDR_R
• extmem::l1_icache2_acs_fail_addr::R
• extmem::l1_icache2_acs_fail_id_attr::L1_ICACHE2_FAIL_ATTR_R
• extmem::l1_icache2_acs_fail_id_attr::L1_ICACHE2_FAIL_ID_R
• extmem::l1_icache2_acs_fail_id_attr::R
• extmem::l1_icache2_autoload_ctrl::L1_ICACHE2_AUTOLOAD_DONE_R
• extmem::l1_icache2_autoload_ctrl::L1_ICACHE2_AUTOLOAD_ENA_R
• extmem::l1_icache2_autoload_ctrl::L1_ICACHE2_AUTOLOAD_ORDER_R
• extmem::l1_icache2_autoload_ctrl::L1_ICACHE2_AUTOLOAD_RGID_R
• extmem::l1_icache2_autoload_ctrl::L1_ICACHE2_AUTOLOAD_SCT0_ENA_R
• extmem::l1_icache2_autoload_ctrl::L1_ICACHE2_AUTOLOAD_SCT1_ENA_R
• extmem::l1_icache2_autoload_ctrl::L1_ICACHE2_AUTOLOAD_TRIGGER_MODE_R
• extmem::l1_icache2_autoload_ctrl::R
• extmem::l1_icache2_autoload_sct0_addr::L1_ICACHE2_AUTOLOAD_SCT0_ADDR_R
• extmem::l1_icache2_autoload_sct0_addr::R
• extmem::l1_icache2_autoload_sct0_size::L1_ICACHE2_AUTOLOAD_SCT0_SIZE_R
• extmem::l1_icache2_autoload_sct0_size::R
• extmem::l1_icache2_autoload_sct1_addr::L1_ICACHE2_AUTOLOAD_SCT1_ADDR_R
• extmem::l1_icache2_autoload_sct1_addr::R
• extmem::l1_icache2_autoload_sct1_size::L1_ICACHE2_AUTOLOAD_SCT1_SIZE_R
• extmem::l1_icache2_autoload_sct1_size::R
• extmem::l1_icache2_preload_addr::L1_ICACHE2_PRELOAD_ADDR_R
• extmem::l1_icache2_preload_addr::R
• extmem::l1_icache2_preload_ctrl::L1_ICACHE2_PRELOAD_DONE_R
• extmem::l1_icache2_preload_ctrl::L1_ICACHE2_PRELOAD_ENA_R
• extmem::l1_icache2_preload_ctrl::L1_ICACHE2_PRELOAD_ENA_W
• extmem::l1_icache2_preload_ctrl::L1_ICACHE2_PRELOAD_ORDER_R
• extmem::l1_icache2_preload_ctrl::L1_ICACHE2_PRELOAD_RGID_R
• extmem::l1_icache2_preload_ctrl::R
• extmem::l1_icache2_preload_ctrl::W
• extmem::l1_icache2_preload_size::L1_ICACHE2_PRELOAD_SIZE_R
• extmem::l1_icache2_preload_size::R
• extmem::l1_icache2_prelock_conf::L1_ICACHE2_PRELOCK_RGID_R
• extmem::l1_icache2_prelock_conf::L1_ICACHE2_PRELOCK_SCT0_EN_R
• extmem::l1_icache2_prelock_conf::L1_ICACHE2_PRELOCK_SCT1_EN_R
• extmem::l1_icache2_prelock_conf::R
• extmem::l1_icache2_prelock_sct0_addr::L1_ICACHE2_PRELOCK_SCT0_ADDR_R
• extmem::l1_icache2_prelock_sct0_addr::R
• extmem::l1_icache2_prelock_sct1_addr::L1_ICACHE2_PRELOCK_SCT1_ADDR_R
• extmem::l1_icache2_prelock_sct1_addr::R
• extmem::l1_icache2_prelock_sct_size::L1_ICACHE2_PRELOCK_SCT0_SIZE_R
• extmem::l1_icache2_prelock_sct_size::L1_ICACHE2_PRELOCK_SCT1_SIZE_R
• extmem::l1_icache2_prelock_sct_size::R
• extmem::l1_icache3_acs_fail_addr::L1_ICACHE3_FAIL_ADDR_R
• extmem::l1_icache3_acs_fail_addr::R
• extmem::l1_icache3_acs_fail_id_attr::L1_ICACHE3_FAIL_ATTR_R
• extmem::l1_icache3_acs_fail_id_attr::L1_ICACHE3_FAIL_ID_R
• extmem::l1_icache3_acs_fail_id_attr::R
• extmem::l1_icache3_autoload_ctrl::L1_ICACHE3_AUTOLOAD_DONE_R
• extmem::l1_icache3_autoload_ctrl::L1_ICACHE3_AUTOLOAD_ENA_R
• extmem::l1_icache3_autoload_ctrl::L1_ICACHE3_AUTOLOAD_ORDER_R
• extmem::l1_icache3_autoload_ctrl::L1_ICACHE3_AUTOLOAD_RGID_R
• extmem::l1_icache3_autoload_ctrl::L1_ICACHE3_AUTOLOAD_SCT0_ENA_R
• extmem::l1_icache3_autoload_ctrl::L1_ICACHE3_AUTOLOAD_SCT1_ENA_R
• extmem::l1_icache3_autoload_ctrl::L1_ICACHE3_AUTOLOAD_TRIGGER_MODE_R
• extmem::l1_icache3_autoload_ctrl::R
• extmem::l1_icache3_autoload_sct0_addr::L1_ICACHE3_AUTOLOAD_SCT0_ADDR_R
• extmem::l1_icache3_autoload_sct0_addr::R
• extmem::l1_icache3_autoload_sct0_size::L1_ICACHE3_AUTOLOAD_SCT0_SIZE_R
• extmem::l1_icache3_autoload_sct0_size::R
• extmem::l1_icache3_autoload_sct1_addr::L1_ICACHE3_AUTOLOAD_SCT1_ADDR_R
• extmem::l1_icache3_autoload_sct1_addr::R
• extmem::l1_icache3_autoload_sct1_size::L1_ICACHE3_AUTOLOAD_SCT1_SIZE_R
• extmem::l1_icache3_autoload_sct1_size::R
• extmem::l1_icache3_preload_addr::L1_ICACHE3_PRELOAD_ADDR_R
• extmem::l1_icache3_preload_addr::R
• extmem::l1_icache3_preload_ctrl::L1_ICACHE3_PRELOAD_DONE_R
• extmem::l1_icache3_preload_ctrl::L1_ICACHE3_PRELOAD_ENA_R
• extmem::l1_icache3_preload_ctrl::L1_ICACHE3_PRELOAD_ENA_W
• extmem::l1_icache3_preload_ctrl::L1_ICACHE3_PRELOAD_ORDER_R
• extmem::l1_icache3_preload_ctrl::L1_ICACHE3_PRELOAD_RGID_R
• extmem::l1_icache3_preload_ctrl::R
• extmem::l1_icache3_preload_ctrl::W
• extmem::l1_icache3_preload_size::L1_ICACHE3_PRELOAD_SIZE_R
• extmem::l1_icache3_preload_size::R
• extmem::l1_icache3_prelock_conf::L1_ICACHE3_PRELOCK_RGID_R
• extmem::l1_icache3_prelock_conf::L1_ICACHE3_PRELOCK_SCT0_EN_R
• extmem::l1_icache3_prelock_conf::L1_ICACHE3_PRELOCK_SCT1_EN_R
• extmem::l1_icache3_prelock_conf::R
• extmem::l1_icache3_prelock_sct0_addr::L1_ICACHE3_PRELOCK_SCT0_ADDR_R
• extmem::l1_icache3_prelock_sct0_addr::R
• extmem::l1_icache3_prelock_sct1_addr::L1_ICACHE3_PRELOCK_SCT1_ADDR_R
• extmem::l1_icache3_prelock_sct1_addr::R
• extmem::l1_icache3_prelock_sct_size::L1_ICACHE3_PRELOCK_SCT0_SIZE_R
• extmem::l1_icache3_prelock_sct_size::L1_ICACHE3_PRELOCK_SCT1_SIZE_R
• extmem::l1_icache3_prelock_sct_size::R
• extmem::l1_icache_blocksize_conf::L1_ICACHE_BLOCKSIZE_128_R
• extmem::l1_icache_blocksize_conf::L1_ICACHE_BLOCKSIZE_16_R
• extmem::l1_icache_blocksize_conf::L1_ICACHE_BLOCKSIZE_256_R
• extmem::l1_icache_blocksize_conf::L1_ICACHE_BLOCKSIZE_32_R
• extmem::l1_icache_blocksize_conf::L1_ICACHE_BLOCKSIZE_64_R
• extmem::l1_icache_blocksize_conf::L1_ICACHE_BLOCKSIZE_8_R
• extmem::l1_icache_blocksize_conf::R
• extmem::l1_icache_cachesize_conf::L1_ICACHE_CACHESIZE_1024K_R
• extmem::l1_icache_cachesize_conf::L1_ICACHE_CACHESIZE_128K_R
• extmem::l1_icache_cachesize_conf::L1_ICACHE_CACHESIZE_16K_R
• extmem::l1_icache_cachesize_conf::L1_ICACHE_CACHESIZE_1K_R
• extmem::l1_icache_cachesize_conf::L1_ICACHE_CACHESIZE_2048K_R
• extmem::l1_icache_cachesize_conf::L1_ICACHE_CACHESIZE_256K_R
• extmem::l1_icache_cachesize_conf::L1_ICACHE_CACHESIZE_2K_R
• extmem::l1_icache_cachesize_conf::L1_ICACHE_CACHESIZE_32K_R
• extmem::l1_icache_cachesize_conf::L1_ICACHE_CACHESIZE_4096K_R
• extmem::l1_icache_cachesize_conf::L1_ICACHE_CACHESIZE_4K_R
• extmem::l1_icache_cachesize_conf::L1_ICACHE_CACHESIZE_512K_R
• extmem::l1_icache_cachesize_conf::L1_ICACHE_CACHESIZE_64K_R
• extmem::l1_icache_cachesize_conf::L1_ICACHE_CACHESIZE_8K_R
• extmem::l1_icache_cachesize_conf::R
• extmem::l1_icache_ctrl::L1_ICACHE_SHUT_IBUS0_R
• extmem::l1_icache_ctrl::L1_ICACHE_SHUT_IBUS1_R
• extmem::l1_icache_ctrl::L1_ICACHE_SHUT_IBUS2_R
• extmem::l1_icache_ctrl::L1_ICACHE_SHUT_IBUS3_R
• extmem::l1_icache_ctrl::L1_ICACHE_UNDEF_OP_R
• extmem::l1_icache_ctrl::R
• extmem::l1_unallocate_buffer_clear::L1_CACHE_UNALLOC_CLR_R
• extmem::l1_unallocate_buffer_clear::L1_CACHE_UNALLOC_CLR_W
• extmem::l1_unallocate_buffer_clear::L1_ICACHE0_UNALLOC_CLR_R
• extmem::l1_unallocate_buffer_clear::L1_ICACHE1_UNALLOC_CLR_R
• extmem::l1_unallocate_buffer_clear::L1_ICACHE2_UNALLOC_CLR_R
• extmem::l1_unallocate_buffer_clear::L1_ICACHE3_UNALLOC_CLR_R
• extmem::l1_unallocate_buffer_clear::R
• extmem::l1_unallocate_buffer_clear::W
• extmem::l2_bypass_cache_conf::BYPASS_L2_CACHE_EN_R
• extmem::l2_bypass_cache_conf::R
• extmem::l2_cache_access_attr_ctrl::L2_CACHE_ACCESS_FORCE_CC_R
• extmem::l2_cache_access_attr_ctrl::L2_CACHE_ACCESS_FORCE_RMA_R
• extmem::l2_cache_access_attr_ctrl::L2_CACHE_ACCESS_FORCE_WB_R
• extmem::l2_cache_access_attr_ctrl::L2_CACHE_ACCESS_FORCE_WMA_R
• extmem::l2_cache_access_attr_ctrl::R
• extmem::l2_cache_acs_cnt_ctrl::L2_DBUS0_CNT_CLR_R
• extmem::l2_cache_acs_cnt_ctrl::L2_DBUS0_CNT_ENA_R
• extmem::l2_cache_acs_cnt_ctrl::L2_DBUS1_CNT_CLR_R
• extmem::l2_cache_acs_cnt_ctrl::L2_DBUS1_CNT_ENA_R
• extmem::l2_cache_acs_cnt_ctrl::L2_DBUS2_CNT_CLR_R
• extmem::l2_cache_acs_cnt_ctrl::L2_DBUS2_CNT_ENA_R
• extmem::l2_cache_acs_cnt_ctrl::L2_DBUS3_CNT_CLR_R
• extmem::l2_cache_acs_cnt_ctrl::L2_DBUS3_CNT_ENA_R
• extmem::l2_cache_acs_cnt_ctrl::L2_IBUS0_CNT_CLR_R
• extmem::l2_cache_acs_cnt_ctrl::L2_IBUS0_CNT_ENA_R
• extmem::l2_cache_acs_cnt_ctrl::L2_IBUS1_CNT_CLR_R
• extmem::l2_cache_acs_cnt_ctrl::L2_IBUS1_CNT_ENA_R
• extmem::l2_cache_acs_cnt_ctrl::L2_IBUS2_CNT_CLR_R
• extmem::l2_cache_acs_cnt_ctrl::L2_IBUS2_CNT_ENA_R
• extmem::l2_cache_acs_cnt_ctrl::L2_IBUS3_CNT_CLR_R
• extmem::l2_cache_acs_cnt_ctrl::L2_IBUS3_CNT_ENA_R
• extmem::l2_cache_acs_cnt_ctrl::R
• extmem::l2_cache_acs_cnt_int_clr::L2_DBUS0_OVF_INT_CLR_R
• extmem::l2_cache_acs_cnt_int_clr::L2_DBUS1_OVF_INT_CLR_R
• extmem::l2_cache_acs_cnt_int_clr::L2_DBUS2_OVF_INT_CLR_R
• extmem::l2_cache_acs_cnt_int_clr::L2_DBUS3_OVF_INT_CLR_R
• extmem::l2_cache_acs_cnt_int_clr::L2_IBUS0_OVF_INT_CLR_R
• extmem::l2_cache_acs_cnt_int_clr::L2_IBUS1_OVF_INT_CLR_R
• extmem::l2_cache_acs_cnt_int_clr::L2_IBUS2_OVF_INT_CLR_R
• extmem::l2_cache_acs_cnt_int_clr::L2_IBUS3_OVF_INT_CLR_R
• extmem::l2_cache_acs_cnt_int_clr::R
• extmem::l2_cache_acs_cnt_int_ena::L2_DBUS0_OVF_INT_ENA_R
• extmem::l2_cache_acs_cnt_int_ena::L2_DBUS1_OVF_INT_ENA_R
• extmem::l2_cache_acs_cnt_int_ena::L2_DBUS2_OVF_INT_ENA_R
• extmem::l2_cache_acs_cnt_int_ena::L2_DBUS3_OVF_INT_ENA_R
• extmem::l2_cache_acs_cnt_int_ena::L2_IBUS0_OVF_INT_ENA_R
• extmem::l2_cache_acs_cnt_int_ena::L2_IBUS1_OVF_INT_ENA_R
• extmem::l2_cache_acs_cnt_int_ena::L2_IBUS2_OVF_INT_ENA_R
• extmem::l2_cache_acs_cnt_int_ena::L2_IBUS3_OVF_INT_ENA_R
• extmem::l2_cache_acs_cnt_int_ena::R
• extmem::l2_cache_acs_cnt_int_raw::L2_DBUS0_OVF_INT_RAW_R
• extmem::l2_cache_acs_cnt_int_raw::L2_DBUS0_OVF_INT_RAW_W
• extmem::l2_cache_acs_cnt_int_raw::L2_DBUS1_OVF_INT_RAW_R
• extmem::l2_cache_acs_cnt_int_raw::L2_DBUS1_OVF_INT_RAW_W
• extmem::l2_cache_acs_cnt_int_raw::L2_DBUS2_OVF_INT_RAW_R
• extmem::l2_cache_acs_cnt_int_raw::L2_DBUS2_OVF_INT_RAW_W
• extmem::l2_cache_acs_cnt_int_raw::L2_DBUS3_OVF_INT_RAW_R
• extmem::l2_cache_acs_cnt_int_raw::L2_DBUS3_OVF_INT_RAW_W
• extmem::l2_cache_acs_cnt_int_raw::L2_IBUS0_OVF_INT_RAW_R
• extmem::l2_cache_acs_cnt_int_raw::L2_IBUS0_OVF_INT_RAW_W
• extmem::l2_cache_acs_cnt_int_raw::L2_IBUS1_OVF_INT_RAW_R
• extmem::l2_cache_acs_cnt_int_raw::L2_IBUS1_OVF_INT_RAW_W
• extmem::l2_cache_acs_cnt_int_raw::L2_IBUS2_OVF_INT_RAW_R
• extmem::l2_cache_acs_cnt_int_raw::L2_IBUS2_OVF_INT_RAW_W
• extmem::l2_cache_acs_cnt_int_raw::L2_IBUS3_OVF_INT_RAW_R
• extmem::l2_cache_acs_cnt_int_raw::L2_IBUS3_OVF_INT_RAW_W
• extmem::l2_cache_acs_cnt_int_raw::R
• extmem::l2_cache_acs_cnt_int_raw::W
• extmem::l2_cache_acs_cnt_int_st::L2_DBUS0_OVF_INT_ST_R
• extmem::l2_cache_acs_cnt_int_st::L2_DBUS1_OVF_INT_ST_R
• extmem::l2_cache_acs_cnt_int_st::L2_DBUS2_OVF_INT_ST_R
• extmem::l2_cache_acs_cnt_int_st::L2_DBUS3_OVF_INT_ST_R
• extmem::l2_cache_acs_cnt_int_st::L2_IBUS0_OVF_INT_ST_R
• extmem::l2_cache_acs_cnt_int_st::L2_IBUS1_OVF_INT_ST_R
• extmem::l2_cache_acs_cnt_int_st::L2_IBUS2_OVF_INT_ST_R
• extmem::l2_cache_acs_cnt_int_st::L2_IBUS3_OVF_INT_ST_R
• extmem::l2_cache_acs_cnt_int_st::R
• extmem::l2_cache_acs_fail_addr::L2_CACHE_FAIL_ADDR_R
• extmem::l2_cache_acs_fail_addr::R
• extmem::l2_cache_acs_fail_id_attr::L2_CACHE_FAIL_ATTR_R
• extmem::l2_cache_acs_fail_id_attr::L2_CACHE_FAIL_ID_R
• extmem::l2_cache_acs_fail_id_attr::R
• extmem::l2_cache_acs_fail_int_clr::L2_CACHE_FAIL_INT_CLR_R
• extmem::l2_cache_acs_fail_int_clr::R
• extmem::l2_cache_acs_fail_int_ena::L2_CACHE_FAIL_INT_ENA_R
• extmem::l2_cache_acs_fail_int_ena::R
• extmem::l2_cache_acs_fail_int_raw::L2_CACHE_FAIL_INT_RAW_R
• extmem::l2_cache_acs_fail_int_raw::L2_CACHE_FAIL_INT_RAW_W
• extmem::l2_cache_acs_fail_int_raw::R
• extmem::l2_cache_acs_fail_int_raw::W
• extmem::l2_cache_acs_fail_int_st::L2_CACHE_FAIL_INT_ST_R
• extmem::l2_cache_acs_fail_int_st::R
• extmem::l2_cache_autoload_buf_clr_ctrl::L2_CACHE_ALD_BUF_CLR_R
• extmem::l2_cache_autoload_buf_clr_ctrl::R
• extmem::l2_cache_autoload_ctrl::L2_CACHE_AUTOLOAD_DONE_R
• extmem::l2_cache_autoload_ctrl::L2_CACHE_AUTOLOAD_ENA_R
• extmem::l2_cache_autoload_ctrl::L2_CACHE_AUTOLOAD_ORDER_R
• extmem::l2_cache_autoload_ctrl::L2_CACHE_AUTOLOAD_RGID_R
• extmem::l2_cache_autoload_ctrl::L2_CACHE_AUTOLOAD_SCT0_ENA_R
• extmem::l2_cache_autoload_ctrl::L2_CACHE_AUTOLOAD_SCT1_ENA_R
• extmem::l2_cache_autoload_ctrl::L2_CACHE_AUTOLOAD_SCT2_ENA_R
• extmem::l2_cache_autoload_ctrl::L2_CACHE_AUTOLOAD_SCT3_ENA_R
• extmem::l2_cache_autoload_ctrl::L2_CACHE_AUTOLOAD_TRIGGER_MODE_R
• extmem::l2_cache_autoload_ctrl::R
• extmem::l2_cache_autoload_sct0_addr::L2_CACHE_AUTOLOAD_SCT0_ADDR_R
• extmem::l2_cache_autoload_sct0_addr::R
• extmem::l2_cache_autoload_sct0_size::L2_CACHE_AUTOLOAD_SCT0_SIZE_R
• extmem::l2_cache_autoload_sct0_size::R
• extmem::l2_cache_autoload_sct1_addr::L2_CACHE_AUTOLOAD_SCT1_ADDR_R
• extmem::l2_cache_autoload_sct1_addr::R
• extmem::l2_cache_autoload_sct1_size::L2_CACHE_AUTOLOAD_SCT1_SIZE_R
• extmem::l2_cache_autoload_sct1_size::R
• extmem::l2_cache_autoload_sct2_addr::L2_CACHE_AUTOLOAD_SCT2_ADDR_R
• extmem::l2_cache_autoload_sct2_addr::R
• extmem::l2_cache_autoload_sct2_size::L2_CACHE_AUTOLOAD_SCT2_SIZE_R
• extmem::l2_cache_autoload_sct2_size::R
• extmem::l2_cache_autoload_sct3_addr::L2_CACHE_AUTOLOAD_SCT3_ADDR_R
• extmem::l2_cache_autoload_sct3_addr::R
• extmem::l2_cache_autoload_sct3_size::L2_CACHE_AUTOLOAD_SCT3_SIZE_R
• extmem::l2_cache_autoload_sct3_size::R
• extmem::l2_cache_blocksize_conf::L2_CACHE_BLOCKSIZE_128_R
• extmem::l2_cache_blocksize_conf::L2_CACHE_BLOCKSIZE_16_R
• extmem::l2_cache_blocksize_conf::L2_CACHE_BLOCKSIZE_256_R
• extmem::l2_cache_blocksize_conf::L2_CACHE_BLOCKSIZE_32_R
• extmem::l2_cache_blocksize_conf::L2_CACHE_BLOCKSIZE_64_R
• extmem::l2_cache_blocksize_conf::L2_CACHE_BLOCKSIZE_8_R
• extmem::l2_cache_blocksize_conf::R
• extmem::l2_cache_cachesize_conf::L2_CACHE_CACHESIZE_1024K_R
• extmem::l2_cache_cachesize_conf::L2_CACHE_CACHESIZE_128K_R
• extmem::l2_cache_cachesize_conf::L2_CACHE_CACHESIZE_16K_R
• extmem::l2_cache_cachesize_conf::L2_CACHE_CACHESIZE_1K_R
• extmem::l2_cache_cachesize_conf::L2_CACHE_CACHESIZE_2048K_R
• extmem::l2_cache_cachesize_conf::L2_CACHE_CACHESIZE_256K_R
• extmem::l2_cache_cachesize_conf::L2_CACHE_CACHESIZE_2K_R
• extmem::l2_cache_cachesize_conf::L2_CACHE_CACHESIZE_32K_R
• extmem::l2_cache_cachesize_conf::L2_CACHE_CACHESIZE_4096K_R
• extmem::l2_cache_cachesize_conf::L2_CACHE_CACHESIZE_4K_R
• extmem::l2_cache_cachesize_conf::L2_CACHE_CACHESIZE_512K_R
• extmem::l2_cache_cachesize_conf::L2_CACHE_CACHESIZE_64K_R
• extmem::l2_cache_cachesize_conf::L2_CACHE_CACHESIZE_8K_R
• extmem::l2_cache_cachesize_conf::R
• extmem::l2_cache_ctrl::L2_CACHE_SHUT_DMA_R
• extmem::l2_cache_ctrl::L2_CACHE_UNDEF_OP_R
• extmem::l2_cache_ctrl::R
• extmem::l2_cache_data_mem_acs_conf::L2_CACHE_DATA_MEM_RD_EN_R
• extmem::l2_cache_data_mem_acs_conf::L2_CACHE_DATA_MEM_WR_EN_R
• extmem::l2_cache_data_mem_acs_conf::R
• extmem::l2_cache_data_mem_power_ctrl::L2_CACHE_DATA_MEM_FORCE_ON_R
• extmem::l2_cache_data_mem_power_ctrl::L2_CACHE_DATA_MEM_FORCE_PD_R
• extmem::l2_cache_data_mem_power_ctrl::L2_CACHE_DATA_MEM_FORCE_PU_R
• extmem::l2_cache_data_mem_power_ctrl::R
• extmem::l2_cache_debug_bus::L2_CACHE_DEBUG_BUS_R
• extmem::l2_cache_debug_bus::R
• extmem::l2_cache_freeze_ctrl::L2_CACHE_FREEZE_DONE_R
• extmem::l2_cache_freeze_ctrl::L2_CACHE_FREEZE_EN_R
• extmem::l2_cache_freeze_ctrl::L2_CACHE_FREEZE_MODE_R
• extmem::l2_cache_freeze_ctrl::R
• extmem::l2_cache_object_ctrl::L2_CACHE_MEM_OBJECT_R
• extmem::l2_cache_object_ctrl::L2_CACHE_TAG_OBJECT_R
• extmem::l2_cache_object_ctrl::R
• extmem::l2_cache_preload_addr::L2_CACHE_PRELOAD_ADDR_R
• extmem::l2_cache_preload_addr::R
• extmem::l2_cache_preload_ctrl::L2_CACHE_PRELOAD_DONE_R
• extmem::l2_cache_preload_ctrl::L2_CACHE_PRELOAD_ENA_R
• extmem::l2_cache_preload_ctrl::L2_CACHE_PRELOAD_ENA_W
• extmem::l2_cache_preload_ctrl::L2_CACHE_PRELOAD_ORDER_R
• extmem::l2_cache_preload_ctrl::L2_CACHE_PRELOAD_RGID_R
• extmem::l2_cache_preload_ctrl::R
• extmem::l2_cache_preload_ctrl::W
• extmem::l2_cache_preload_rst_ctrl::L2_CACHE_PLD_RST_R
• extmem::l2_cache_preload_rst_ctrl::R
• extmem::l2_cache_preload_size::L2_CACHE_PRELOAD_SIZE_R
• extmem::l2_cache_preload_size::R
• extmem::l2_cache_prelock_conf::L2_CACHE_PRELOCK_RGID_R
• extmem::l2_cache_prelock_conf::L2_CACHE_PRELOCK_SCT0_EN_R
• extmem::l2_cache_prelock_conf::L2_CACHE_PRELOCK_SCT1_EN_R
• extmem::l2_cache_prelock_conf::R
• extmem::l2_cache_prelock_sct0_addr::L2_CACHE_PRELOCK_SCT0_ADDR_R
• extmem::l2_cache_prelock_sct0_addr::R
• extmem::l2_cache_prelock_sct1_addr::L2_CACHE_PRELOCK_SCT1_ADDR_R
• extmem::l2_cache_prelock_sct1_addr::R
• extmem::l2_cache_prelock_sct_size::L2_CACHE_PRELOCK_SCT0_SIZE_R
• extmem::l2_cache_prelock_sct_size::L2_CACHE_PRELOCK_SCT1_SIZE_R
• extmem::l2_cache_prelock_sct_size::R
• extmem::l2_cache_sync_preload_exception::L2_CACHE_PLD_ERR_CODE_R
• extmem::l2_cache_sync_preload_exception::R
• extmem::l2_cache_sync_preload_int_clr::L2_CACHE_PLD_DONE_INT_CLR_R
• extmem::l2_cache_sync_preload_int_clr::L2_CACHE_PLD_ERR_INT_CLR_R
• extmem::l2_cache_sync_preload_int_clr::R
• extmem::l2_cache_sync_preload_int_ena::L2_CACHE_PLD_DONE_INT_ENA_R
• extmem::l2_cache_sync_preload_int_ena::L2_CACHE_PLD_ERR_INT_ENA_R
• extmem::l2_cache_sync_preload_int_ena::R
• extmem::l2_cache_sync_preload_int_raw::L2_CACHE_PLD_DONE_INT_RAW_R
• extmem::l2_cache_sync_preload_int_raw::L2_CACHE_PLD_DONE_INT_RAW_W
• extmem::l2_cache_sync_preload_int_raw::L2_CACHE_PLD_ERR_INT_RAW_R
• extmem::l2_cache_sync_preload_int_raw::L2_CACHE_PLD_ERR_INT_RAW_W
• extmem::l2_cache_sync_preload_int_raw::R
• extmem::l2_cache_sync_preload_int_raw::W
• extmem::l2_cache_sync_preload_int_st::L2_CACHE_PLD_DONE_INT_ST_R
• extmem::l2_cache_sync_preload_int_st::L2_CACHE_PLD_ERR_INT_ST_R
• extmem::l2_cache_sync_preload_int_st::R
• extmem::l2_cache_sync_rst_ctrl::L2_CACHE_SYNC_RST_R
• extmem::l2_cache_sync_rst_ctrl::R
• extmem::l2_cache_tag_mem_acs_conf::L2_CACHE_TAG_MEM_RD_EN_R
• extmem::l2_cache_tag_mem_acs_conf::L2_CACHE_TAG_MEM_WR_EN_R
• extmem::l2_cache_tag_mem_acs_conf::R
• extmem::l2_cache_tag_mem_power_ctrl::L2_CACHE_TAG_MEM_FORCE_ON_R
• extmem::l2_cache_tag_mem_power_ctrl::L2_CACHE_TAG_MEM_FORCE_PD_R
• extmem::l2_cache_tag_mem_power_ctrl::L2_CACHE_TAG_MEM_FORCE_PU_R
• extmem::l2_cache_tag_mem_power_ctrl::R
• extmem::l2_cache_vaddr::L2_CACHE_VADDR_R
• extmem::l2_cache_vaddr::R
• extmem::l2_cache_way_object::L2_CACHE_WAY_OBJECT_R
• extmem::l2_cache_way_object::R
• extmem::l2_cache_wrap_around_ctrl::L2_CACHE_WRAP_R
• extmem::l2_cache_wrap_around_ctrl::R
• extmem::l2_dbus0_acs_conflict_cnt::L2_DBUS0_CONFLICT_CNT_R
• extmem::l2_dbus0_acs_conflict_cnt::R
• extmem::l2_dbus0_acs_hit_cnt::L2_DBUS0_HIT_CNT_R
• extmem::l2_dbus0_acs_hit_cnt::R
• extmem::l2_dbus0_acs_miss_cnt::L2_DBUS0_MISS_CNT_R
• extmem::l2_dbus0_acs_miss_cnt::R
• extmem::l2_dbus0_acs_nxtlvl_cnt::L2_DBUS0_NXTLVL_CNT_R
• extmem::l2_dbus0_acs_nxtlvl_cnt::R
• extmem::l2_dbus1_acs_conflict_cnt::L2_DBUS1_CONFLICT_CNT_R
• extmem::l2_dbus1_acs_conflict_cnt::R
• extmem::l2_dbus1_acs_hit_cnt::L2_DBUS1_HIT_CNT_R
• extmem::l2_dbus1_acs_hit_cnt::R
• extmem::l2_dbus1_acs_miss_cnt::L2_DBUS1_MISS_CNT_R
• extmem::l2_dbus1_acs_miss_cnt::R
• extmem::l2_dbus1_acs_nxtlvl_cnt::L2_DBUS1_NXTLVL_CNT_R
• extmem::l2_dbus1_acs_nxtlvl_cnt::R
• extmem::l2_dbus2_acs_conflict_cnt::L2_DBUS2_CONFLICT_CNT_R
• extmem::l2_dbus2_acs_conflict_cnt::R
• extmem::l2_dbus2_acs_hit_cnt::L2_DBUS2_HIT_CNT_R
• extmem::l2_dbus2_acs_hit_cnt::R
• extmem::l2_dbus2_acs_miss_cnt::L2_DBUS2_MISS_CNT_R
• extmem::l2_dbus2_acs_miss_cnt::R
• extmem::l2_dbus2_acs_nxtlvl_cnt::L2_DBUS2_NXTLVL_CNT_R
• extmem::l2_dbus2_acs_nxtlvl_cnt::R
• extmem::l2_dbus3_acs_conflict_cnt::L2_DBUS3_CONFLICT_CNT_R
• extmem::l2_dbus3_acs_conflict_cnt::R
• extmem::l2_dbus3_acs_hit_cnt::L2_DBUS3_HIT_CNT_R
• extmem::l2_dbus3_acs_hit_cnt::R
• extmem::l2_dbus3_acs_miss_cnt::L2_DBUS3_MISS_CNT_R
• extmem::l2_dbus3_acs_miss_cnt::R
• extmem::l2_dbus3_acs_nxtlvl_cnt::L2_DBUS3_NXTLVL_CNT_R
• extmem::l2_dbus3_acs_nxtlvl_cnt::R
• extmem::l2_ibus0_acs_conflict_cnt::L2_IBUS0_CONFLICT_CNT_R
• extmem::l2_ibus0_acs_conflict_cnt::R
• extmem::l2_ibus0_acs_hit_cnt::L2_IBUS0_HIT_CNT_R
• extmem::l2_ibus0_acs_hit_cnt::R
• extmem::l2_ibus0_acs_miss_cnt::L2_IBUS0_MISS_CNT_R
• extmem::l2_ibus0_acs_miss_cnt::R
• extmem::l2_ibus0_acs_nxtlvl_cnt::L2_IBUS0_NXTLVL_CNT_R
• extmem::l2_ibus0_acs_nxtlvl_cnt::R
• extmem::l2_ibus1_acs_conflict_cnt::L2_IBUS1_CONFLICT_CNT_R
• extmem::l2_ibus1_acs_conflict_cnt::R
• extmem::l2_ibus1_acs_hit_cnt::L2_IBUS1_HIT_CNT_R
• extmem::l2_ibus1_acs_hit_cnt::R
• extmem::l2_ibus1_acs_miss_cnt::L2_IBUS1_MISS_CNT_R
• extmem::l2_ibus1_acs_miss_cnt::R
• extmem::l2_ibus1_acs_nxtlvl_cnt::L2_IBUS1_NXTLVL_CNT_R
• extmem::l2_ibus1_acs_nxtlvl_cnt::R
• extmem::l2_ibus2_acs_conflict_cnt::L2_IBUS2_CONFLICT_CNT_R
• extmem::l2_ibus2_acs_conflict_cnt::R
• extmem::l2_ibus2_acs_hit_cnt::L2_IBUS2_HIT_CNT_R
• extmem::l2_ibus2_acs_hit_cnt::R
• extmem::l2_ibus2_acs_miss_cnt::L2_IBUS2_MISS_CNT_R
• extmem::l2_ibus2_acs_miss_cnt::R
• extmem::l2_ibus2_acs_nxtlvl_cnt::L2_IBUS2_NXTLVL_CNT_R
• extmem::l2_ibus2_acs_nxtlvl_cnt::R
• extmem::l2_ibus3_acs_conflict_cnt::L2_IBUS3_CONFLICT_CNT_R
• extmem::l2_ibus3_acs_conflict_cnt::R
• extmem::l2_ibus3_acs_hit_cnt::L2_IBUS3_HIT_CNT_R
• extmem::l2_ibus3_acs_hit_cnt::R
• extmem::l2_ibus3_acs_miss_cnt::L2_IBUS3_MISS_CNT_R
• extmem::l2_ibus3_acs_miss_cnt::R
• extmem::l2_ibus3_acs_nxtlvl_cnt::L2_IBUS3_NXTLVL_CNT_R
• extmem::l2_ibus3_acs_nxtlvl_cnt::R
• extmem::l2_unallocate_buffer_clear::L2_CACHE_UNALLOC_CLR_R
• extmem::l2_unallocate_buffer_clear::R
• extmem::level_split0::LEVEL_SPLIT0_R
• extmem::level_split0::R
• extmem::level_split1::LEVEL_SPLIT1_R
• extmem::level_split1::R
• extmem::redundancy_sig0::CACHE_REDCY_SIG0_R
• extmem::redundancy_sig0::CACHE_REDCY_SIG0_W
• extmem::redundancy_sig0::R
• extmem::redundancy_sig0::W
• extmem::redundancy_sig1::CACHE_REDCY_SIG1_R
• extmem::redundancy_sig1::CACHE_REDCY_SIG1_W
• extmem::redundancy_sig1::R
• extmem::redundancy_sig1::W
• extmem::redundancy_sig2::CACHE_REDCY_SIG2_R
• extmem::redundancy_sig2::CACHE_REDCY_SIG2_W
• extmem::redundancy_sig2::R
• extmem::redundancy_sig2::W
• extmem::redundancy_sig3::CACHE_REDCY_SIG3_R
• extmem::redundancy_sig3::CACHE_REDCY_SIG3_W
• extmem::redundancy_sig3::R
• extmem::redundancy_sig3::W
• extmem::redundancy_sig4::CACHE_REDCY_SIG4_R
• extmem::redundancy_sig4::R
• generic::BitReader
• generic::BitWriter
• generic::BitWriter0C
• generic::BitWriter0S
• generic::BitWriter0T
• generic::BitWriter1C
• generic::BitWriter1S
• generic::BitWriter1T
• generic::FieldReader
• generic::FieldWriter
• generic::R
• generic::W
• gpio::BT_SELECT
• gpio::CLOCK_GATE
• gpio::CPUSDIO_INT
• gpio::CPUSDIO_INT1
• gpio::DATE
• gpio::ENABLE
• gpio::ENABLE1
• gpio::ENABLE1_W1TC
• gpio::ENABLE1_W1TS
• gpio::ENABLE_W1TC
• gpio::ENABLE_W1TS
• gpio::FUNC_IN_SEL_CFG
• gpio::FUNC_OUT_SEL_CFG
• gpio::IN
• gpio::IN1
• gpio::OUT
• gpio::OUT1
• gpio::OUT1_W1TC
• gpio::OUT1_W1TS
• gpio::OUT_W1TC
• gpio::OUT_W1TS
• gpio::PCPU_INT
• gpio::PCPU_INT1
• gpio::PCPU_NMI_INT
• gpio::PCPU_NMI_INT1
• gpio::PIN
• gpio::SDIO_SELECT
• gpio::STATUS
• gpio::STATUS1
• gpio::STATUS1_W1TC
• gpio::STATUS1_W1TS
• gpio::STATUS_NEXT
• gpio::STATUS_NEXT1
• gpio::STATUS_W1TC
• gpio::STATUS_W1TS
• gpio::STRAP
• gpio::bt_select::BT_SEL_R
• gpio::bt_select::BT_SEL_W
• gpio::bt_select::R
• gpio::bt_select::W
• gpio::clock_gate::CLK_EN_R
• gpio::clock_gate::CLK_EN_W
• gpio::clock_gate::R
• gpio::clock_gate::W
• gpio::cpusdio_int1::R
• gpio::cpusdio_int1::SDIO_INT1_R
• gpio::cpusdio_int::R
• gpio::cpusdio_int::SDIO_INT_R
• gpio::date::DATE_R
• gpio::date::DATE_W
• gpio::date::R
• gpio::date::W
• gpio::enable1::DATA_R
• gpio::enable1::DATA_W
• gpio::enable1::R
• gpio::enable1::W
• gpio::enable1_w1tc::ENABLE1_W1TC_W
• gpio::enable1_w1tc::W
• gpio::enable1_w1ts::ENABLE1_W1TS_W
• gpio::enable1_w1ts::W
• gpio::enable::DATA_R
• gpio::enable::DATA_W
• gpio::enable::R
• gpio::enable::W
• gpio::enable_w1tc::ENABLE_W1TC_W
• gpio::enable_w1tc::W
• gpio::enable_w1ts::ENABLE_W1TS_W
• gpio::enable_w1ts::W
• gpio::func_in_sel_cfg::IN_INV_SEL_R
• gpio::func_in_sel_cfg::IN_INV_SEL_W
• gpio::func_in_sel_cfg::IN_SEL_R
• gpio::func_in_sel_cfg::IN_SEL_W
• gpio::func_in_sel_cfg::R
• gpio::func_in_sel_cfg::SEL_R
• gpio::func_in_sel_cfg::SEL_W
• gpio::func_in_sel_cfg::W
• gpio::func_out_sel_cfg::INV_SEL_R
• gpio::func_out_sel_cfg::INV_SEL_W
• gpio::func_out_sel_cfg::OEN_INV_SEL_R
• gpio::func_out_sel_cfg::OEN_INV_SEL_W
• gpio::func_out_sel_cfg::OEN_SEL_R
• gpio::func_out_sel_cfg::OEN_SEL_W
• gpio::func_out_sel_cfg::OUT_SEL_R
• gpio::func_out_sel_cfg::OUT_SEL_W
• gpio::func_out_sel_cfg::R
• gpio::func_out_sel_cfg::W
• gpio::in1::DATA_NEXT_R
• gpio::in1::R
• gpio::in_::DATA_NEXT_R
• gpio::in_::R
• gpio::out1::DATA_ORIG_R
• gpio::out1::DATA_ORIG_W
• gpio::out1::R
• gpio::out1::W
• gpio::out1_w1tc::OUT1_W1TC_W
• gpio::out1_w1tc::W
• gpio::out1_w1ts::OUT1_W1TS_W
• gpio::out1_w1ts::W
• gpio::out::DATA_ORIG_R
• gpio::out::DATA_ORIG_W
• gpio::out::R
• gpio::out::W
• gpio::out_w1tc::OUT_W1TC_W
• gpio::out_w1tc::W
• gpio::out_w1ts::OUT_W1TS_W
• gpio::out_w1ts::W
• gpio::pcpu_int1::PROCPU_INT1_R
• gpio::pcpu_int1::R
• gpio::pcpu_int::PROCPU_INT_R
• gpio::pcpu_int::R
• gpio::pcpu_nmi_int1::PROCPU_NMI_INT1_R
• gpio::pcpu_nmi_int1::R
• gpio::pcpu_nmi_int::PROCPU_NMI_INT_R
• gpio::pcpu_nmi_int::R
• gpio::pin::CONFIG_R
• gpio::pin::CONFIG_W
• gpio::pin::INT_ENA_R
• gpio::pin::INT_ENA_W
• gpio::pin::INT_TYPE_R
• gpio::pin::INT_TYPE_W
• gpio::pin::PAD_DRIVER_R
• gpio::pin::PAD_DRIVER_W
• gpio::pin::R
• gpio::pin::SYNC1_BYPASS_R
• gpio::pin::SYNC1_BYPASS_W
• gpio::pin::SYNC2_BYPASS_R
• gpio::pin::SYNC2_BYPASS_W
• gpio::pin::W
• gpio::pin::WAKEUP_ENABLE_R
• gpio::pin::WAKEUP_ENABLE_W
• gpio::sdio_select::R
• gpio::sdio_select::SDIO_SEL_R
• gpio::sdio_select::SDIO_SEL_W
• gpio::sdio_select::W
• gpio::status1::INTERRUPT_R
• gpio::status1::INTERRUPT_W
• gpio::status1::R
• gpio::status1::W
• gpio::status1_w1tc::STATUS1_W1TC_W
• gpio::status1_w1tc::W
• gpio::status1_w1ts::STATUS1_W1TS_W
• gpio::status1_w1ts::W
• gpio::status::INTERRUPT_R
• gpio::status::INTERRUPT_W
• gpio::status::R
• gpio::status::W
• gpio::status_next1::R
• gpio::status_next1::STATUS_INTERRUPT_NEXT1_R
• gpio::status_next::R
• gpio::status_next::STATUS_INTERRUPT_NEXT_R
• gpio::status_w1tc::STATUS_W1TC_W
• gpio::status_w1tc::W
• gpio::status_w1ts::STATUS_W1TS_W
• gpio::status_w1ts::W
• gpio::strap::R
• gpio::strap::STRAPPING_R
• gpio_sd::CLOCK_GATE
• gpio_sd::ETM_EVENT_CH_CFG
• gpio_sd::ETM_TASK_P0_CFG
• gpio_sd::ETM_TASK_P1_CFG
• gpio_sd::ETM_TASK_P2_CFG
• gpio_sd::ETM_TASK_P3_CFG
• gpio_sd::ETM_TASK_P4_CFG
• gpio_sd::ETM_TASK_P5_CFG
• gpio_sd::ETM_TASK_P6_CFG
• gpio_sd::ETM_TASK_P7_CFG
• gpio_sd::GLITCH_FILTER_CH
• gpio_sd::SIGMADELTA
• gpio_sd::SIGMADELTA_MISC
• gpio_sd::VERSION
• gpio_sd::clock_gate::CLK_EN_R
• gpio_sd::clock_gate::CLK_EN_W
• gpio_sd::clock_gate::R
• gpio_sd::clock_gate::W
• gpio_sd::etm_event_ch_cfg::EVENT_EN_R
• gpio_sd::etm_event_ch_cfg::EVENT_EN_W
• gpio_sd::etm_event_ch_cfg::EVENT_SEL_R
• gpio_sd::etm_event_ch_cfg::EVENT_SEL_W
• gpio_sd::etm_event_ch_cfg::R
• gpio_sd::etm_event_ch_cfg::W
• gpio_sd::etm_task_p0_cfg::GPIO_EN_R
• gpio_sd::etm_task_p0_cfg::GPIO_EN_W
• gpio_sd::etm_task_p0_cfg::GPIO_SEL_R
• gpio_sd::etm_task_p0_cfg::GPIO_SEL_W
• gpio_sd::etm_task_p0_cfg::R
• gpio_sd::etm_task_p0_cfg::W
• gpio_sd::etm_task_p1_cfg::GPIO_EN_R
• gpio_sd::etm_task_p1_cfg::GPIO_EN_W
• gpio_sd::etm_task_p1_cfg::GPIO_SEL_R
• gpio_sd::etm_task_p1_cfg::GPIO_SEL_W
• gpio_sd::etm_task_p1_cfg::R
• gpio_sd::etm_task_p1_cfg::W
• gpio_sd::etm_task_p2_cfg::GPIO_EN_R
• gpio_sd::etm_task_p2_cfg::GPIO_EN_W
• gpio_sd::etm_task_p2_cfg::GPIO_SEL_R
• gpio_sd::etm_task_p2_cfg::GPIO_SEL_W
• gpio_sd::etm_task_p2_cfg::R
• gpio_sd::etm_task_p2_cfg::W
• gpio_sd::etm_task_p3_cfg::GPIO_EN_R
• gpio_sd::etm_task_p3_cfg::GPIO_EN_W
• gpio_sd::etm_task_p3_cfg::GPIO_SEL_R
• gpio_sd::etm_task_p3_cfg::GPIO_SEL_W
• gpio_sd::etm_task_p3_cfg::R
• gpio_sd::etm_task_p3_cfg::W
• gpio_sd::etm_task_p4_cfg::GPIO_EN_R
• gpio_sd::etm_task_p4_cfg::GPIO_EN_W
• gpio_sd::etm_task_p4_cfg::GPIO_SEL_R
• gpio_sd::etm_task_p4_cfg::GPIO_SEL_W
• gpio_sd::etm_task_p4_cfg::R
• gpio_sd::etm_task_p4_cfg::W
• gpio_sd::etm_task_p5_cfg::GPIO_EN_R
• gpio_sd::etm_task_p5_cfg::GPIO_EN_W
• gpio_sd::etm_task_p5_cfg::GPIO_SEL_R
• gpio_sd::etm_task_p5_cfg::GPIO_SEL_W
• gpio_sd::etm_task_p5_cfg::R
• gpio_sd::etm_task_p5_cfg::W
• gpio_sd::etm_task_p6_cfg::GPIO_EN_R
• gpio_sd::etm_task_p6_cfg::GPIO_EN_W
• gpio_sd::etm_task_p6_cfg::GPIO_SEL_R
• gpio_sd::etm_task_p6_cfg::GPIO_SEL_W
• gpio_sd::etm_task_p6_cfg::R
• gpio_sd::etm_task_p6_cfg::W
• gpio_sd::etm_task_p7_cfg::GPIO_EN_R
• gpio_sd::etm_task_p7_cfg::GPIO_EN_W
• gpio_sd::etm_task_p7_cfg::GPIO_SEL_R
• gpio_sd::etm_task_p7_cfg::GPIO_SEL_W
• gpio_sd::etm_task_p7_cfg::R
• gpio_sd::etm_task_p7_cfg::W
• gpio_sd::glitch_filter_ch::EN_R
• gpio_sd::glitch_filter_ch::EN_W
• gpio_sd::glitch_filter_ch::INPUT_IO_NUM_R
• gpio_sd::glitch_filter_ch::INPUT_IO_NUM_W
• gpio_sd::glitch_filter_ch::R
• gpio_sd::glitch_filter_ch::W
• gpio_sd::glitch_filter_ch::WINDOW_THRES_R
• gpio_sd::glitch_filter_ch::WINDOW_THRES_W
• gpio_sd::glitch_filter_ch::WINDOW_WIDTH_R
• gpio_sd::glitch_filter_ch::WINDOW_WIDTH_W
• gpio_sd::sigmadelta::IN_R
• gpio_sd::sigmadelta::IN_W
• gpio_sd::sigmadelta::PRESCALE_R
• gpio_sd::sigmadelta::PRESCALE_W
• gpio_sd::sigmadelta::R
• gpio_sd::sigmadelta::W
• gpio_sd::sigmadelta_misc::FUNCTION_CLK_EN_R
• gpio_sd::sigmadelta_misc::FUNCTION_CLK_EN_W
• gpio_sd::sigmadelta_misc::R
• gpio_sd::sigmadelta_misc::SPI_SWAP_R
• gpio_sd::sigmadelta_misc::SPI_SWAP_W
• gpio_sd::sigmadelta_misc::W
• gpio_sd::version::GPIO_SD_DATE_R
• gpio_sd::version::GPIO_SD_DATE_W
• gpio_sd::version::R
• gpio_sd::version::W
• hinf::CFG_DATA0
• hinf::CFG_DATA1
• hinf::CFG_DATA16
• hinf::CFG_DATA7
• hinf::CFG_TIMING
• hinf::CFG_UHS1_INT_MODE
• hinf::CFG_UPDATE
• hinf::CIS_CONF_W0
• hinf::CIS_CONF_W1
• hinf::CIS_CONF_W2
• hinf::CIS_CONF_W3
• hinf::CIS_CONF_W4
• hinf::CIS_CONF_W5
• hinf::CIS_CONF_W6
• hinf::CIS_CONF_W7
• hinf::CONF_STATUS
• hinf::SDIO_DATE
• hinf::SDIO_SLAVE_ECO_CONF
• hinf::SDIO_SLAVE_ECO_HIGH
• hinf::SDIO_SLAVE_ECO_LOW
• hinf::SDIO_SLAVE_LDO_CONF
• hinf::cfg_data0::DEVICE_ID_FN1_R
• hinf::cfg_data0::DEVICE_ID_FN1_W
• hinf::cfg_data0::R
• hinf::cfg_data0::USER_ID_FN1_R
• hinf::cfg_data0::USER_ID_FN1_W
• hinf::cfg_data0::W
• hinf::cfg_data16::DEVICE_ID_FN2_R
• hinf::cfg_data16::DEVICE_ID_FN2_W
• hinf::cfg_data16::R
• hinf::cfg_data16::USER_ID_FN2_R
• hinf::cfg_data16::USER_ID_FN2_W
• hinf::cfg_data16::W
• hinf::cfg_data1::CD_DISABLE_R
• hinf::cfg_data1::EMP_R
• hinf::cfg_data1::FUNC1_EPS_R
• hinf::cfg_data1::FUNC2_EPS_R
• hinf::cfg_data1::HIGHSPEED_ENABLE_R
• hinf::cfg_data1::HIGHSPEED_ENABLE_W
• hinf::cfg_data1::HIGHSPEED_MODE_R
• hinf::cfg_data1::IOENABLE1_R
• hinf::cfg_data1::IOENABLE2_R
• hinf::cfg_data1::R
• hinf::cfg_data1::SDIO20_CONF_R
• hinf::cfg_data1::SDIO20_CONF_W
• hinf::cfg_data1::SDIO_CD_ENABLE_R
• hinf::cfg_data1::SDIO_CD_ENABLE_W
• hinf::cfg_data1::SDIO_ENABLE_R
• hinf::cfg_data1::SDIO_ENABLE_W
• hinf::cfg_data1::SDIO_INT_MASK_R
• hinf::cfg_data1::SDIO_INT_MASK_W
• hinf::cfg_data1::SDIO_IOREADY1_R
• hinf::cfg_data1::SDIO_IOREADY1_W
• hinf::cfg_data1::SDIO_IOREADY2_R
• hinf::cfg_data1::SDIO_IOREADY2_W
• hinf::cfg_data1::SDIO_VER_R
• hinf::cfg_data1::SDIO_VER_W
• hinf::cfg_data1::W
• hinf::cfg_data7::CHIP_STATE_R
• hinf::cfg_data7::CHIP_STATE_W
• hinf::cfg_data7::CLK_EN_R
• hinf::cfg_data7::CLK_EN_W
• hinf::cfg_data7::DDR50_BLK_LEN_FIX_EN_R
• hinf::cfg_data7::DDR50_BLK_LEN_FIX_EN_W
• hinf::cfg_data7::ESDIO_DATA1_INT_EN_R
• hinf::cfg_data7::ESDIO_DATA1_INT_EN_W
• hinf::cfg_data7::PIN_STATE_R
• hinf::cfg_data7::PIN_STATE_W
• hinf::cfg_data7::R
• hinf::cfg_data7::SAI_R
• hinf::cfg_data7::SAI_W
• hinf::cfg_data7::SDDR50_R
• hinf::cfg_data7::SDDR50_W
• hinf::cfg_data7::SDIO_IOREADY0_R
• hinf::cfg_data7::SDIO_IOREADY0_W
• hinf::cfg_data7::SDIO_MEM_PD_R
• hinf::cfg_data7::SDIO_MEM_PD_W
• hinf::cfg_data7::SDIO_RST_R
• hinf::cfg_data7::SDIO_RST_W
• hinf::cfg_data7::SDIO_SWITCH_VOLT_SW_R
• hinf::cfg_data7::SDIO_SWITCH_VOLT_SW_W
• hinf::cfg_data7::SDIO_WAKEUP_CLR_W
• hinf::cfg_data7::SDTA_R
• hinf::cfg_data7::SDTA_W
• hinf::cfg_data7::SDTC_R
• hinf::cfg_data7::SDTC_W
• hinf::cfg_data7::SDTD_R
• hinf::cfg_data7::SDTD_W
• hinf::cfg_data7::SSDR104_R
• hinf::cfg_data7::SSDR104_W
• hinf::cfg_data7::SSDR50_R
• hinf::cfg_data7::SSDR50_W
• hinf::cfg_data7::W
• hinf::cfg_timing::NCRC_R
• hinf::cfg_timing::NCRC_W
• hinf::cfg_timing::PST_END_CMD_LOW_VALUE_R
• hinf::cfg_timing::PST_END_CMD_LOW_VALUE_W
• hinf::cfg_timing::PST_END_DATA_LOW_VALUE_R
• hinf::cfg_timing::PST_END_DATA_LOW_VALUE_W
• hinf::cfg_timing::R
• hinf::cfg_timing::SAMPLE_CLK_DIVIDER_R
• hinf::cfg_timing::SAMPLE_CLK_DIVIDER_W
• hinf::cfg_timing::SDCLK_STOP_THRES_R
• hinf::cfg_timing::SDCLK_STOP_THRES_W
• hinf::cfg_timing::W
• hinf::cfg_uhs1_int_mode::INTOE_END_AHEAD_MODE_R
• hinf::cfg_uhs1_int_mode::INTOE_END_AHEAD_MODE_W
• hinf::cfg_uhs1_int_mode::INTOE_ST_AHEAD_MODE_R
• hinf::cfg_uhs1_int_mode::INTOE_ST_AHEAD_MODE_W
• hinf::cfg_uhs1_int_mode::INT_END_AHEAD_MODE_R
• hinf::cfg_uhs1_int_mode::INT_END_AHEAD_MODE_W
• hinf::cfg_uhs1_int_mode::INT_ST_AHEAD_MODE_R
• hinf::cfg_uhs1_int_mode::INT_ST_AHEAD_MODE_W
• hinf::cfg_uhs1_int_mode::R
• hinf::cfg_uhs1_int_mode::W
• hinf::cfg_update::CONF_UPDATE_W
• hinf::cfg_update::W
• hinf::cis_conf_w0::CIS_CONF_W0_R
• hinf::cis_conf_w0::CIS_CONF_W0_W
• hinf::cis_conf_w0::R
• hinf::cis_conf_w0::W
• hinf::cis_conf_w1::CIS_CONF_W1_R
• hinf::cis_conf_w1::CIS_CONF_W1_W
• hinf::cis_conf_w1::R
• hinf::cis_conf_w1::W
• hinf::cis_conf_w2::CIS_CONF_W2_R
• hinf::cis_conf_w2::CIS_CONF_W2_W
• hinf::cis_conf_w2::R
• hinf::cis_conf_w2::W
• hinf::cis_conf_w3::CIS_CONF_W3_R
• hinf::cis_conf_w3::CIS_CONF_W3_W
• hinf::cis_conf_w3::R
• hinf::cis_conf_w3::W
• hinf::cis_conf_w4::CIS_CONF_W4_R
• hinf::cis_conf_w4::CIS_CONF_W4_W
• hinf::cis_conf_w4::R
• hinf::cis_conf_w4::W
• hinf::cis_conf_w5::CIS_CONF_W5_R
• hinf::cis_conf_w5::CIS_CONF_W5_W
• hinf::cis_conf_w5::R
• hinf::cis_conf_w5::W
• hinf::cis_conf_w6::CIS_CONF_W6_R
• hinf::cis_conf_w6::CIS_CONF_W6_W
• hinf::cis_conf_w6::R
• hinf::cis_conf_w6::W
• hinf::cis_conf_w7::CIS_CONF_W7_R
• hinf::cis_conf_w7::CIS_CONF_W7_W
• hinf::cis_conf_w7::R
• hinf::cis_conf_w7::W
• hinf::conf_status::DDR50_ST_R
• hinf::conf_status::FUNC0_CONFIG0_R
• hinf::conf_status::R
• hinf::conf_status::SDIO_SWITCH_END_R
• hinf::conf_status::SDIO_SWITCH_VOLT_ST_R
• hinf::conf_status::SDR104_ST_R
• hinf::conf_status::SDR25_ST_R
• hinf::conf_status::SDR50_ST_R
• hinf::conf_status::TUNE_ST_R
• hinf::sdio_date::R
• hinf::sdio_date::SDIO_DATE_R
• hinf::sdio_date::SDIO_DATE_W
• hinf::sdio_date::W
• hinf::sdio_slave_eco_conf::R
• hinf::sdio_slave_eco_conf::SDIO_SLAVE_RDN_ENA_R
• hinf::sdio_slave_eco_conf::SDIO_SLAVE_RDN_ENA_W
• hinf::sdio_slave_eco_conf::SDIO_SLAVE_RDN_RESULT_R
• hinf::sdio_slave_eco_conf::SDIO_SLAVE_SDCLK_PAD_RDN_ENA_R
• hinf::sdio_slave_eco_conf::SDIO_SLAVE_SDCLK_PAD_RDN_ENA_W
• hinf::sdio_slave_eco_conf::SDIO_SLAVE_SDCLK_PAD_RDN_RESULT_R
• hinf::sdio_slave_eco_conf::SDIO_SLAVE_SDIO_CLK_RDN_ENA_R
• hinf::sdio_slave_eco_conf::SDIO_SLAVE_SDIO_CLK_RDN_ENA_W
• hinf::sdio_slave_eco_conf::SDIO_SLAVE_SDIO_CLK_RDN_RESULT_R
• hinf::sdio_slave_eco_conf::W
• hinf::sdio_slave_eco_high::R
• hinf::sdio_slave_eco_high::RDN_ECO_HIGH_R
• hinf::sdio_slave_eco_high::RDN_ECO_HIGH_W
• hinf::sdio_slave_eco_high::W
• hinf::sdio_slave_eco_low::R
• hinf::sdio_slave_eco_low::RDN_ECO_LOW_R
• hinf::sdio_slave_eco_low::RDN_ECO_LOW_W
• hinf::sdio_slave_eco_low::W
• hinf::sdio_slave_ldo_conf::LDO_READY_CTL_IN_EN_R
• hinf::sdio_slave_ldo_conf::LDO_READY_CTL_IN_EN_W
• hinf::sdio_slave_ldo_conf::LDO_READY_IGNORE_EN_R
• hinf::sdio_slave_ldo_conf::LDO_READY_IGNORE_EN_W
• hinf::sdio_slave_ldo_conf::LDO_READY_THRES_R
• hinf::sdio_slave_ldo_conf::LDO_READY_THRES_W
• hinf::sdio_slave_ldo_conf::R
• hinf::sdio_slave_ldo_conf::W
• hmac::DATE
• hmac::ONE_BLOCK
• hmac::QUERY_BUSY
• hmac::QUERY_ERROR
• hmac::RD_RESULT_MEM
• hmac::SET_INVALIDATE_DS
• hmac::SET_INVALIDATE_JTAG
• hmac::SET_MESSAGE_END
• hmac::SET_MESSAGE_ING
• hmac::SET_MESSAGE_ONE
• hmac::SET_MESSAGE_PAD
• hmac::SET_PARA_FINISH
• hmac::SET_PARA_KEY
• hmac::SET_PARA_PURPOSE
• hmac::SET_RESULT_FINISH
• hmac::SET_START
• hmac::SOFT_JTAG_CTRL
• hmac::WR_JTAG
• hmac::WR_MESSAGE_MEM
• hmac::date::DATE_R
• hmac::date::DATE_W
• hmac::date::R
• hmac::date::W
• hmac::one_block::SET_ONE_BLOCK_W
• hmac::one_block::W
• hmac::query_busy::BUSY_STATE_R
• hmac::query_busy::R
• hmac::query_error::QUERY_CHECK_R
• hmac::query_error::R
• hmac::rd_result_mem::R
• hmac::rd_result_mem::W
• hmac::set_invalidate_ds::SET_INVALIDATE_DS_W
• hmac::set_invalidate_ds::W
• hmac::set_invalidate_jtag::SET_INVALIDATE_JTAG_W
• hmac::set_invalidate_jtag::W
• hmac::set_message_end::SET_TEXT_END_W
• hmac::set_message_end::W
• hmac::set_message_ing::SET_TEXT_ING_W
• hmac::set_message_ing::W
• hmac::set_message_one::SET_TEXT_ONE_W
• hmac::set_message_one::W
• hmac::set_message_pad::SET_TEXT_PAD_W
• hmac::set_message_pad::W
• hmac::set_para_finish::SET_PARA_END_W
• hmac::set_para_finish::W
• hmac::set_para_key::KEY_SET_W
• hmac::set_para_key::W
• hmac::set_para_purpose::PURPOSE_SET_W
• hmac::set_para_purpose::W
• hmac::set_result_finish::SET_RESULT_END_W
• hmac::set_result_finish::W
• hmac::set_start::SET_START_W
• hmac::set_start::W
• hmac::soft_jtag_ctrl::SOFT_JTAG_CTRL_W
• hmac::soft_jtag_ctrl::W
• hmac::wr_jtag::W
• hmac::wr_jtag::WR_JTAG_W
• hmac::wr_message_mem::R
• hmac::wr_message_mem::W
• hp_apm::CLOCK_GATE
• hp_apm::DATE
• hp_apm::FUNC_CTRL
• hp_apm::INT_EN
• hp_apm::REGION_FILTER_EN
• hp_apm::clock_gate::CLK_EN_R
• hp_apm::clock_gate::CLK_EN_W
• hp_apm::clock_gate::R
• hp_apm::clock_gate::W
• hp_apm::date::DATE_R
• hp_apm::date::DATE_W
• hp_apm::date::R
• hp_apm::date::W
• hp_apm::func_ctrl::M_PMS_FUNC_EN_R
• hp_apm::func_ctrl::M_PMS_FUNC_EN_W
• hp_apm::func_ctrl::R
• hp_apm::func_ctrl::W
• hp_apm::int_en::M_APM_R
• hp_apm::int_en::M_APM_W
• hp_apm::int_en::R
• hp_apm::int_en::W
• hp_apm::m::EXCEPTION_INFO0
• hp_apm::m::EXCEPTION_INFO1
• hp_apm::m::STATUS
• hp_apm::m::STATUS_CLR
• hp_apm::m::exception_info0::EXCEPTION_ID_R
• hp_apm::m::exception_info0::EXCEPTION_MODE_R
• hp_apm::m::exception_info0::EXCEPTION_REGION_R
• hp_apm::m::exception_info0::R
• hp_apm::m::exception_info1::EXCEPTION_ADDR_R
• hp_apm::m::exception_info1::R
• hp_apm::m::status::EXCEPTION_STATUS_R
• hp_apm::m::status::R
• hp_apm::m::status_clr::REGION_STATUS_CLR_W
• hp_apm::m::status_clr::W
• hp_apm::region::ADDR_END
• hp_apm::region::ADDR_START
• hp_apm::region::PMS_ATTR
• hp_apm::region::addr_end::ADDR_END_R
• hp_apm::region::addr_end::ADDR_END_W
• hp_apm::region::addr_end::R
• hp_apm::region::addr_end::W
• hp_apm::region::addr_start::ADDR_START_R
• hp_apm::region::addr_start::ADDR_START_W
• hp_apm::region::addr_start::R
• hp_apm::region::addr_start::W
• hp_apm::region::pms_attr::R
• hp_apm::region::pms_attr::R_PMS_R_R
• hp_apm::region::pms_attr::R_PMS_R_W
• hp_apm::region::pms_attr::R_PMS_W_R
• hp_apm::region::pms_attr::R_PMS_W_W
• hp_apm::region::pms_attr::R_PMS_X_R
• hp_apm::region::pms_attr::R_PMS_X_W
• hp_apm::region::pms_attr::W
• hp_apm::region_filter_en::R
• hp_apm::region_filter_en::REGION_FILTER_EN_R
• hp_apm::region_filter_en::REGION_FILTER_EN_W
• hp_apm::region_filter_en::W
• hp_sys::CLOCK_GATE
• hp_sys::CORE_DEBUG_RUNSTALL_CONF
• hp_sys::CPU_PERI_TIMEOUT_ADDR
• hp_sys::CPU_PERI_TIMEOUT_CONF
• hp_sys::CPU_PERI_TIMEOUT_UID
• hp_sys::DATE
• hp_sys::EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL
• hp_sys::HP_PERI_TIMEOUT_ADDR
• hp_sys::HP_PERI_TIMEOUT_CONF
• hp_sys::HP_PERI_TIMEOUT_UID
• hp_sys::MEM_TEST_CONF
• hp_sys::MODEM_PERI_TIMEOUT_ADDR
• hp_sys::MODEM_PERI_TIMEOUT_CONF
• hp_sys::MODEM_PERI_TIMEOUT_UID
• hp_sys::RETENTION_CONF
• hp_sys::RND_ECO
• hp_sys::RND_ECO_HIGH
• hp_sys::RND_ECO_LOW
• hp_sys::ROM_TABLE
• hp_sys::ROM_TABLE_LOCK
• hp_sys::SDIO_CTRL
• hp_sys::SEC_DPA_CONF
• hp_sys::SRAM_USAGE_CONF
• hp_sys::clock_gate::CLK_EN_R
• hp_sys::clock_gate::CLK_EN_W
• hp_sys::clock_gate::R
• hp_sys::clock_gate::W
• hp_sys::core_debug_runstall_conf::CORE_DEBUG_RUNSTALL_ENABLE_R
• hp_sys::core_debug_runstall_conf::CORE_DEBUG_RUNSTALL_ENABLE_W
• hp_sys::core_debug_runstall_conf::R
• hp_sys::core_debug_runstall_conf::W
• hp_sys::cpu_peri_timeout_addr::CPU_PERI_TIMEOUT_ADDR_R
• hp_sys::cpu_peri_timeout_addr::R
• hp_sys::cpu_peri_timeout_conf::CPU_PERI_TIMEOUT_INT_CLEAR_W
• hp_sys::cpu_peri_timeout_conf::CPU_PERI_TIMEOUT_PROTECT_EN_R
• hp_sys::cpu_peri_timeout_conf::CPU_PERI_TIMEOUT_PROTECT_EN_W
• hp_sys::cpu_peri_timeout_conf::CPU_PERI_TIMEOUT_THRES_R
• hp_sys::cpu_peri_timeout_conf::CPU_PERI_TIMEOUT_THRES_W
• hp_sys::cpu_peri_timeout_conf::R
• hp_sys::cpu_peri_timeout_conf::W
• hp_sys::cpu_peri_timeout_uid::CPU_PERI_TIMEOUT_UID_R
• hp_sys::cpu_peri_timeout_uid::R
• hp_sys::date::DATE_R
• hp_sys::date::DATE_W
• hp_sys::date::R
• hp_sys::date::W
• hp_sys::external_device_encrypt_decrypt_control::ENABLE_DOWNLOAD_DB_ENCRYPT_R
• hp_sys::external_device_encrypt_decrypt_control::ENABLE_DOWNLOAD_DB_ENCRYPT_W
• hp_sys::external_device_encrypt_decrypt_control::ENABLE_DOWNLOAD_G0CB_DECRYPT_R
• hp_sys::external_device_encrypt_decrypt_control::ENABLE_DOWNLOAD_G0CB_DECRYPT_W
• hp_sys::external_device_encrypt_decrypt_control::ENABLE_DOWNLOAD_MANUAL_ENCRYPT_R
• hp_sys::external_device_encrypt_decrypt_control::ENABLE_DOWNLOAD_MANUAL_ENCRYPT_W
• hp_sys::external_device_encrypt_decrypt_control::ENABLE_SPI_MANUAL_ENCRYPT_R
• hp_sys::external_device_encrypt_decrypt_control::ENABLE_SPI_MANUAL_ENCRYPT_W
• hp_sys::external_device_encrypt_decrypt_control::R
• hp_sys::external_device_encrypt_decrypt_control::W
• hp_sys::hp_peri_timeout_addr::HP_PERI_TIMEOUT_ADDR_R
• hp_sys::hp_peri_timeout_addr::R
• hp_sys::hp_peri_timeout_conf::HP_PERI_TIMEOUT_INT_CLEAR_W
• hp_sys::hp_peri_timeout_conf::HP_PERI_TIMEOUT_PROTECT_EN_R
• hp_sys::hp_peri_timeout_conf::HP_PERI_TIMEOUT_PROTECT_EN_W
• hp_sys::hp_peri_timeout_conf::HP_PERI_TIMEOUT_THRES_R
• hp_sys::hp_peri_timeout_conf::HP_PERI_TIMEOUT_THRES_W
• hp_sys::hp_peri_timeout_conf::R
• hp_sys::hp_peri_timeout_conf::W
• hp_sys::hp_peri_timeout_uid::HP_PERI_TIMEOUT_UID_R
• hp_sys::hp_peri_timeout_uid::R
• hp_sys::mem_test_conf::HP_MEM_RA_R
• hp_sys::mem_test_conf::HP_MEM_RA_W
• hp_sys::mem_test_conf::HP_MEM_WA_R
• hp_sys::mem_test_conf::HP_MEM_WA_W
• hp_sys::mem_test_conf::HP_MEM_WPULSE_R
• hp_sys::mem_test_conf::HP_MEM_WPULSE_W
• hp_sys::mem_test_conf::R
• hp_sys::mem_test_conf::W
• hp_sys::modem_peri_timeout_addr::MODEM_PERI_TIMEOUT_ADDR_R
• hp_sys::modem_peri_timeout_addr::R
• hp_sys::modem_peri_timeout_conf::MODEM_PERI_TIMEOUT_INT_CLEAR_W
• hp_sys::modem_peri_timeout_conf::MODEM_PERI_TIMEOUT_PROTECT_EN_R
• hp_sys::modem_peri_timeout_conf::MODEM_PERI_TIMEOUT_PROTECT_EN_W
• hp_sys::modem_peri_timeout_conf::MODEM_PERI_TIMEOUT_THRES_R
• hp_sys::modem_peri_timeout_conf::MODEM_PERI_TIMEOUT_THRES_W
• hp_sys::modem_peri_timeout_conf::R
• hp_sys::modem_peri_timeout_conf::W
• hp_sys::modem_peri_timeout_uid::MODEM_PERI_TIMEOUT_UID_R
• hp_sys::modem_peri_timeout_uid::R
• hp_sys::retention_conf::R
• hp_sys::retention_conf::RETENTION_DISABLE_R
• hp_sys::retention_conf::RETENTION_DISABLE_W
• hp_sys::retention_conf::W
• hp_sys::rnd_eco::R
• hp_sys::rnd_eco::REDCY_ENA_R
• hp_sys::rnd_eco::REDCY_ENA_W
• hp_sys::rnd_eco::REDCY_RESULT_R
• hp_sys::rnd_eco::W
• hp_sys::rnd_eco_high::R
• hp_sys::rnd_eco_high::REDCY_HIGH_R
• hp_sys::rnd_eco_high::REDCY_HIGH_W
• hp_sys::rnd_eco_high::W
• hp_sys::rnd_eco_low::R
• hp_sys::rnd_eco_low::REDCY_LOW_R
• hp_sys::rnd_eco_low::REDCY_LOW_W
• hp_sys::rnd_eco_low::W
• hp_sys::rom_table::R
• hp_sys::rom_table::ROM_TABLE_R
• hp_sys::rom_table::ROM_TABLE_W
• hp_sys::rom_table::W
• hp_sys::rom_table_lock::R
• hp_sys::rom_table_lock::ROM_TABLE_LOCK_R
• hp_sys::rom_table_lock::ROM_TABLE_LOCK_W
• hp_sys::rom_table_lock::W
• hp_sys::sdio_ctrl::DIS_SDIO_PROB_R
• hp_sys::sdio_ctrl::DIS_SDIO_PROB_W
• hp_sys::sdio_ctrl::R
• hp_sys::sdio_ctrl::SDIO_WIN_ACCESS_EN_R
• hp_sys::sdio_ctrl::SDIO_WIN_ACCESS_EN_W
• hp_sys::sdio_ctrl::W
• hp_sys::sec_dpa_conf::R
• hp_sys::sec_dpa_conf::SEC_DPA_CFG_SEL_R
• hp_sys::sec_dpa_conf::SEC_DPA_CFG_SEL_W
• hp_sys::sec_dpa_conf::SEC_DPA_LEVEL_R
• hp_sys::sec_dpa_conf::SEC_DPA_LEVEL_W
• hp_sys::sec_dpa_conf::W
• hp_sys::sram_usage_conf::CACHE_USAGE_R
• hp_sys::sram_usage_conf::MAC_DUMP_ALLOC_R
• hp_sys::sram_usage_conf::MAC_DUMP_ALLOC_W
• hp_sys::sram_usage_conf::R
• hp_sys::sram_usage_conf::SRAM_USAGE_R
• hp_sys::sram_usage_conf::SRAM_USAGE_W
• hp_sys::sram_usage_conf::W
• i2c0::CLK_CONF
• i2c0::COMD
• i2c0::CTR
• i2c0::DATA
• i2c0::DATE
• i2c0::FIFO_CONF
• i2c0::FIFO_ST
• i2c0::FILTER_CFG
• i2c0::INT_CLR
• i2c0::INT_ENA
• i2c0::INT_RAW
• i2c0::INT_ST
• i2c0::RXFIFO_START_ADDR
• i2c0::SCL_HIGH_PERIOD
• i2c0::SCL_LOW_PERIOD
• i2c0::SCL_MAIN_ST_TIME_OUT
• i2c0::SCL_RSTART_SETUP
• i2c0::SCL_SP_CONF
• i2c0::SCL_START_HOLD
• i2c0::SCL_STOP_HOLD
• i2c0::SCL_STOP_SETUP
• i2c0::SCL_STRETCH_CONF
• i2c0::SCL_ST_TIME_OUT
• i2c0::SDA_HOLD
• i2c0::SDA_SAMPLE
• i2c0::SLAVE_ADDR
• i2c0::SR
• i2c0::TO
• i2c0::TXFIFO_START_ADDR
• i2c0::clk_conf::R
• i2c0::clk_conf::SCLK_ACTIVE_R
• i2c0::clk_conf::SCLK_ACTIVE_W
• i2c0::clk_conf::SCLK_DIV_A_R
• i2c0::clk_conf::SCLK_DIV_A_W
• i2c0::clk_conf::SCLK_DIV_B_R
• i2c0::clk_conf::SCLK_DIV_B_W
• i2c0::clk_conf::SCLK_DIV_NUM_R
• i2c0::clk_conf::SCLK_DIV_NUM_W
• i2c0::clk_conf::SCLK_SEL_R
• i2c0::clk_conf::SCLK_SEL_W
• i2c0::clk_conf::W
• i2c0::comd::ACK_CHECK_EN_R
• i2c0::comd::ACK_CHECK_EN_W
• i2c0::comd::ACK_EXP_R
• i2c0::comd::ACK_EXP_W
• i2c0::comd::ACK_VALUE_R
• i2c0::comd::ACK_VALUE_W
• i2c0::comd::BYTE_NUM_R
• i2c0::comd::BYTE_NUM_W
• i2c0::comd::COMMAND_DONE_R
• i2c0::comd::COMMAND_DONE_W
• i2c0::comd::OPCODE_R
• i2c0::comd::OPCODE_W
• i2c0::comd::R
• i2c0::comd::W
• i2c0::ctr::ADDR_10BIT_RW_CHECK_EN_R
• i2c0::ctr::ADDR_10BIT_RW_CHECK_EN_W
• i2c0::ctr::ADDR_BROADCASTING_EN_R
• i2c0::ctr::ADDR_BROADCASTING_EN_W
• i2c0::ctr::ARBITRATION_EN_R
• i2c0::ctr::ARBITRATION_EN_W
• i2c0::ctr::CLK_EN_R
• i2c0::ctr::CLK_EN_W
• i2c0::ctr::CONF_UPGATE_W
• i2c0::ctr::FSM_RST_W
• i2c0::ctr::MS_MODE_R
• i2c0::ctr::MS_MODE_W
• i2c0::ctr::R
• i2c0::ctr::RX_FULL_ACK_LEVEL_R
• i2c0::ctr::RX_FULL_ACK_LEVEL_W
• i2c0::ctr::RX_LSB_FIRST_R
• i2c0::ctr::RX_LSB_FIRST_W
• i2c0::ctr::SAMPLE_SCL_LEVEL_R
• i2c0::ctr::SAMPLE_SCL_LEVEL_W
• i2c0::ctr::SCL_FORCE_OUT_R
• i2c0::ctr::SCL_FORCE_OUT_W
• i2c0::ctr::SDA_FORCE_OUT_R
• i2c0::ctr::SDA_FORCE_OUT_W
• i2c0::ctr::SLV_TX_AUTO_START_EN_R
• i2c0::ctr::SLV_TX_AUTO_START_EN_W
• i2c0::ctr::TRANS_START_W
• i2c0::ctr::TX_LSB_FIRST_R
• i2c0::ctr::TX_LSB_FIRST_W
• i2c0::ctr::W
• i2c0::data::FIFO_RDATA_R
• i2c0::data::FIFO_RDATA_W
• i2c0::data::R
• i2c0::data::W
• i2c0::date::DATE_R
• i2c0::date::DATE_W
• i2c0::date::R
• i2c0::date::W
• i2c0::fifo_conf::FIFO_ADDR_CFG_EN_R
• i2c0::fifo_conf::FIFO_ADDR_CFG_EN_W
• i2c0::fifo_conf::FIFO_PRT_EN_R
• i2c0::fifo_conf::FIFO_PRT_EN_W
• i2c0::fifo_conf::NONFIFO_EN_R
• i2c0::fifo_conf::NONFIFO_EN_W
• i2c0::fifo_conf::R
• i2c0::fifo_conf::RXFIFO_WM_THRHD_R
• i2c0::fifo_conf::RXFIFO_WM_THRHD_W
• i2c0::fifo_conf::RX_FIFO_RST_R
• i2c0::fifo_conf::RX_FIFO_RST_W
• i2c0::fifo_conf::TXFIFO_WM_THRHD_R
• i2c0::fifo_conf::TXFIFO_WM_THRHD_W
• i2c0::fifo_conf::TX_FIFO_RST_R
• i2c0::fifo_conf::TX_FIFO_RST_W
• i2c0::fifo_conf::W
• i2c0::fifo_st::R
• i2c0::fifo_st::RXFIFO_RADDR_R
• i2c0::fifo_st::RXFIFO_WADDR_R
• i2c0::fifo_st::SLAVE_RW_POINT_R
• i2c0::fifo_st::TXFIFO_RADDR_R
• i2c0::fifo_st::TXFIFO_WADDR_R
• i2c0::filter_cfg::R
• i2c0::filter_cfg::SCL_FILTER_EN_R
• i2c0::filter_cfg::SCL_FILTER_EN_W
• i2c0::filter_cfg::SCL_FILTER_THRES_R
• i2c0::filter_cfg::SCL_FILTER_THRES_W
• i2c0::filter_cfg::SDA_FILTER_EN_R
• i2c0::filter_cfg::SDA_FILTER_EN_W
• i2c0::filter_cfg::SDA_FILTER_THRES_R
• i2c0::filter_cfg::SDA_FILTER_THRES_W
• i2c0::filter_cfg::W
• i2c0::int_clr::ARBITRATION_LOST_W
• i2c0::int_clr::BYTE_TRANS_DONE_W
• i2c0::int_clr::DET_START_W
• i2c0::int_clr::END_DETECT_W
• i2c0::int_clr::GENERAL_CALL_W
• i2c0::int_clr::MST_TXFIFO_UDF_W
• i2c0::int_clr::NACK_W
• i2c0::int_clr::RXFIFO_OVF_W
• i2c0::int_clr::RXFIFO_UDF_W
• i2c0::int_clr::RXFIFO_WM_W
• i2c0::int_clr::SCL_MAIN_ST_TO_W
• i2c0::int_clr::SCL_ST_TO_W
• i2c0::int_clr::SLAVE_ADDR_UNMATCH_W
• i2c0::int_clr::SLAVE_STRETCH_W
• i2c0::int_clr::TIME_OUT_W
• i2c0::int_clr::TRANS_COMPLETE_W
• i2c0::int_clr::TRANS_START_W
• i2c0::int_clr::TXFIFO_OVF_W
• i2c0::int_clr::TXFIFO_WM_W
• i2c0::int_clr::W
• i2c0::int_ena::ARBITRATION_LOST_R
• i2c0::int_ena::ARBITRATION_LOST_W
• i2c0::int_ena::BYTE_TRANS_DONE_R
• i2c0::int_ena::BYTE_TRANS_DONE_W
• i2c0::int_ena::DET_START_R
• i2c0::int_ena::DET_START_W
• i2c0::int_ena::END_DETECT_R
• i2c0::int_ena::END_DETECT_W
• i2c0::int_ena::GENERAL_CALL_R
• i2c0::int_ena::GENERAL_CALL_W
• i2c0::int_ena::MST_TXFIFO_UDF_R
• i2c0::int_ena::MST_TXFIFO_UDF_W
• i2c0::int_ena::NACK_R
• i2c0::int_ena::NACK_W
• i2c0::int_ena::R
• i2c0::int_ena::RXFIFO_OVF_R
• i2c0::int_ena::RXFIFO_OVF_W
• i2c0::int_ena::RXFIFO_UDF_R
• i2c0::int_ena::RXFIFO_UDF_W
• i2c0::int_ena::RXFIFO_WM_R
• i2c0::int_ena::RXFIFO_WM_W
• i2c0::int_ena::SCL_MAIN_ST_TO_R
• i2c0::int_ena::SCL_MAIN_ST_TO_W
• i2c0::int_ena::SCL_ST_TO_R
• i2c0::int_ena::SCL_ST_TO_W
• i2c0::int_ena::SLAVE_ADDR_UNMATCH_R
• i2c0::int_ena::SLAVE_ADDR_UNMATCH_W
• i2c0::int_ena::SLAVE_STRETCH_R
• i2c0::int_ena::SLAVE_STRETCH_W
• i2c0::int_ena::TIME_OUT_R
• i2c0::int_ena::TIME_OUT_W
• i2c0::int_ena::TRANS_COMPLETE_R
• i2c0::int_ena::TRANS_COMPLETE_W
• i2c0::int_ena::TRANS_START_R
• i2c0::int_ena::TRANS_START_W
• i2c0::int_ena::TXFIFO_OVF_R
• i2c0::int_ena::TXFIFO_OVF_W
• i2c0::int_ena::TXFIFO_WM_R
• i2c0::int_ena::TXFIFO_WM_W
• i2c0::int_ena::W
• i2c0::int_raw::ARBITRATION_LOST_R
• i2c0::int_raw::BYTE_TRANS_DONE_R
• i2c0::int_raw::DET_START_R
• i2c0::int_raw::END_DETECT_R
• i2c0::int_raw::GENERAL_CALL_R
• i2c0::int_raw::MST_TXFIFO_UDF_R
• i2c0::int_raw::NACK_R
• i2c0::int_raw::R
• i2c0::int_raw::RXFIFO_OVF_R
• i2c0::int_raw::RXFIFO_UDF_R
• i2c0::int_raw::RXFIFO_WM_R
• i2c0::int_raw::SCL_MAIN_ST_TO_R
• i2c0::int_raw::SCL_ST_TO_R
• i2c0::int_raw::SLAVE_ADDR_UNMATCH_R
• i2c0::int_raw::SLAVE_STRETCH_R
• i2c0::int_raw::TIME_OUT_R
• i2c0::int_raw::TRANS_COMPLETE_R
• i2c0::int_raw::TRANS_START_R
• i2c0::int_raw::TXFIFO_OVF_R
• i2c0::int_raw::TXFIFO_WM_R
• i2c0::int_st::ARBITRATION_LOST_R
• i2c0::int_st::BYTE_TRANS_DONE_R
• i2c0::int_st::DET_START_R
• i2c0::int_st::END_DETECT_R
• i2c0::int_st::GENERAL_CALL_R
• i2c0::int_st::MST_TXFIFO_UDF_R
• i2c0::int_st::NACK_R
• i2c0::int_st::R
• i2c0::int_st::RXFIFO_OVF_R
• i2c0::int_st::RXFIFO_UDF_R
• i2c0::int_st::RXFIFO_WM_R
• i2c0::int_st::SCL_MAIN_ST_TO_R
• i2c0::int_st::SCL_ST_TO_R
• i2c0::int_st::SLAVE_ADDR_UNMATCH_R
• i2c0::int_st::SLAVE_STRETCH_R
• i2c0::int_st::TIME_OUT_R
• i2c0::int_st::TRANS_COMPLETE_R
• i2c0::int_st::TRANS_START_R
• i2c0::int_st::TXFIFO_OVF_R
• i2c0::int_st::TXFIFO_WM_R
• i2c0::rxfifo_start_addr::R
• i2c0::rxfifo_start_addr::RXFIFO_START_ADDR_R
• i2c0::scl_high_period::R
• i2c0::scl_high_period::SCL_HIGH_PERIOD_R
• i2c0::scl_high_period::SCL_HIGH_PERIOD_W
• i2c0::scl_high_period::SCL_WAIT_HIGH_PERIOD_R
• i2c0::scl_high_period::SCL_WAIT_HIGH_PERIOD_W
• i2c0::scl_high_period::W
• i2c0::scl_low_period::R
• i2c0::scl_low_period::SCL_LOW_PERIOD_R
• i2c0::scl_low_period::SCL_LOW_PERIOD_W
• i2c0::scl_low_period::W
• i2c0::scl_main_st_time_out::R
• i2c0::scl_main_st_time_out::SCL_MAIN_ST_TO_R
• i2c0::scl_main_st_time_out::SCL_MAIN_ST_TO_W
• i2c0::scl_main_st_time_out::W
• i2c0::scl_rstart_setup::R
• i2c0::scl_rstart_setup::TIME_R
• i2c0::scl_rstart_setup::TIME_W
• i2c0::scl_rstart_setup::W
• i2c0::scl_sp_conf::R
• i2c0::scl_sp_conf::SCL_PD_EN_R
• i2c0::scl_sp_conf::SCL_PD_EN_W
• i2c0::scl_sp_conf::SCL_RST_SLV_EN_R
• i2c0::scl_sp_conf::SCL_RST_SLV_EN_W
• i2c0::scl_sp_conf::SCL_RST_SLV_NUM_R
• i2c0::scl_sp_conf::SCL_RST_SLV_NUM_W
• i2c0::scl_sp_conf::SDA_PD_EN_R
• i2c0::scl_sp_conf::SDA_PD_EN_W
• i2c0::scl_sp_conf::W
• i2c0::scl_st_time_out::R
• i2c0::scl_st_time_out::SCL_ST_TO_R
• i2c0::scl_st_time_out::SCL_ST_TO_W
• i2c0::scl_st_time_out::W
• i2c0::scl_start_hold::R
• i2c0::scl_start_hold::TIME_R
• i2c0::scl_start_hold::TIME_W
• i2c0::scl_start_hold::W
• i2c0::scl_stop_hold::R
• i2c0::scl_stop_hold::TIME_R
• i2c0::scl_stop_hold::TIME_W
• i2c0::scl_stop_hold::W
• i2c0::scl_stop_setup::R
• i2c0::scl_stop_setup::TIME_R
• i2c0::scl_stop_setup::TIME_W
• i2c0::scl_stop_setup::W
• i2c0::scl_stretch_conf::R
• i2c0::scl_stretch_conf::SLAVE_BYTE_ACK_CTL_EN_R
• i2c0::scl_stretch_conf::SLAVE_BYTE_ACK_CTL_EN_W
• i2c0::scl_stretch_conf::SLAVE_BYTE_ACK_LVL_R
• i2c0::scl_stretch_conf::SLAVE_BYTE_ACK_LVL_W
• i2c0::scl_stretch_conf::SLAVE_SCL_STRETCH_CLR_W
• i2c0::scl_stretch_conf::SLAVE_SCL_STRETCH_EN_R
• i2c0::scl_stretch_conf::SLAVE_SCL_STRETCH_EN_W
• i2c0::scl_stretch_conf::STRETCH_PROTECT_NUM_R
• i2c0::scl_stretch_conf::STRETCH_PROTECT_NUM_W
• i2c0::scl_stretch_conf::W
• i2c0::sda_hold::R
• i2c0::sda_hold::TIME_R
• i2c0::sda_hold::TIME_W
• i2c0::sda_hold::W
• i2c0::sda_sample::R
• i2c0::sda_sample::TIME_R
• i2c0::sda_sample::TIME_W
• i2c0::sda_sample::W
• i2c0::slave_addr::ADDR_10BIT_EN_R
• i2c0::slave_addr::ADDR_10BIT_EN_W
• i2c0::slave_addr::R
• i2c0::slave_addr::SLAVE_ADDR_R
• i2c0::slave_addr::SLAVE_ADDR_W
• i2c0::slave_addr::W
• i2c0::sr::ARB_LOST_R
• i2c0::sr::BUS_BUSY_R
• i2c0::sr::R
• i2c0::sr::RESP_REC_R
• i2c0::sr::RXFIFO_CNT_R
• i2c0::sr::SCL_MAIN_STATE_LAST_R
• i2c0::sr::SCL_STATE_LAST_R
• i2c0::sr::SLAVE_ADDRESSED_R
• i2c0::sr::SLAVE_RW_R
• i2c0::sr::STRETCH_CAUSE_R
• i2c0::sr::TXFIFO_CNT_R
• i2c0::to::R
• i2c0::to::TIME_OUT_EN_R
• i2c0::to::TIME_OUT_EN_W
• i2c0::to::TIME_OUT_VALUE_R
• i2c0::to::TIME_OUT_VALUE_W
• i2c0::to::W
• i2c0::txfifo_start_addr::R
• i2c0::txfifo_start_addr::TXFIFO_START_ADDR_R
• i2c_ana_mst::ANA_CONF0
• i2c_ana_mst::ANA_CONF1
• i2c_ana_mst::ANA_CONF2
• i2c_ana_mst::BURST_CONF
• i2c_ana_mst::BURST_STATUS
• i2c_ana_mst::DATE
• i2c_ana_mst::I2C0_CONF
• i2c_ana_mst::I2C1_CONF
• i2c_ana_mst::I2C_CTRL
• i2c_ana_mst::I2C_CTRL1
• i2c_ana_mst::ana_conf0::BBPLL_STOP_FORCE_HIGH_R
• i2c_ana_mst::ana_conf0::BBPLL_STOP_FORCE_HIGH_W
• i2c_ana_mst::ana_conf0::BBPLL_STOP_FORCE_LOW_R
• i2c_ana_mst::ana_conf0::BBPLL_STOP_FORCE_LOW_W
• i2c_ana_mst::ana_conf0::CAL_DONE_R
• i2c_ana_mst::ana_conf0::R
• i2c_ana_mst::ana_conf0::W
• i2c_ana_mst::ana_conf1::BBPLL_PD_R
• i2c_ana_mst::ana_conf1::BBPLL_PD_W
• i2c_ana_mst::ana_conf1::BBPLL_RD_R
• i2c_ana_mst::ana_conf1::BBPLL_RD_W
• i2c_ana_mst::ana_conf1::BIAS_RD_R
• i2c_ana_mst::ana_conf1::BIAS_RD_W
• i2c_ana_mst::ana_conf1::DIG_REG_RD_R
• i2c_ana_mst::ana_conf1::DIG_REG_RD_W
• i2c_ana_mst::ana_conf1::R
• i2c_ana_mst::ana_conf1::SAR_FORCE_PD_R
• i2c_ana_mst::ana_conf1::SAR_FORCE_PD_W
• i2c_ana_mst::ana_conf1::SAR_FORCE_PU_R
• i2c_ana_mst::ana_conf1::SAR_FORCE_PU_W
• i2c_ana_mst::ana_conf1::SAR_I2C_RD_R
• i2c_ana_mst::ana_conf1::SAR_I2C_RD_W
• i2c_ana_mst::ana_conf1::STATUS_R
• i2c_ana_mst::ana_conf1::ULP_CAL_RD_R
• i2c_ana_mst::ana_conf1::ULP_CAL_RD_W
• i2c_ana_mst::ana_conf1::W
• i2c_ana_mst::ana_conf2::BBPLL_MST_SEL_R
• i2c_ana_mst::ana_conf2::BBPLL_MST_SEL_W
• i2c_ana_mst::ana_conf2::BBPLL_M_R
• i2c_ana_mst::ana_conf2::BBPLL_M_W
• i2c_ana_mst::ana_conf2::BIAS_MST_SEL_R
• i2c_ana_mst::ana_conf2::BIAS_MST_SEL_W
• i2c_ana_mst::ana_conf2::DIG_REG_MST_SEL_R
• i2c_ana_mst::ana_conf2::DIG_REG_MST_SEL_W
• i2c_ana_mst::ana_conf2::R
• i2c_ana_mst::ana_conf2::SAR_FORCE_PD_R
• i2c_ana_mst::ana_conf2::SAR_FORCE_PD_W
• i2c_ana_mst::ana_conf2::SAR_FORCE_PU_R
• i2c_ana_mst::ana_conf2::SAR_FORCE_PU_W
• i2c_ana_mst::ana_conf2::SAR_I2C_MST_SEL_R
• i2c_ana_mst::ana_conf2::SAR_I2C_MST_SEL_W
• i2c_ana_mst::ana_conf2::STATUS_R
• i2c_ana_mst::ana_conf2::ULP_CAL_MST_SEL_R
• i2c_ana_mst::ana_conf2::ULP_CAL_MST_SEL_W
• i2c_ana_mst::ana_conf2::W
• i2c_ana_mst::burst_conf::BURST_CTRL_R
• i2c_ana_mst::burst_conf::BURST_CTRL_W
• i2c_ana_mst::burst_conf::R
• i2c_ana_mst::burst_conf::W
• i2c_ana_mst::burst_status::MST0_BURST_ERR_R
• i2c_ana_mst::burst_status::MST1_BURST_ERR_R
• i2c_ana_mst::burst_status::MST_BURST_DONE_R
• i2c_ana_mst::burst_status::R
• i2c_ana_mst::burst_status::TIMEOUT_CNT_R
• i2c_ana_mst::burst_status::W
• i2c_ana_mst::date::CLK_EN_R
• i2c_ana_mst::date::CLK_EN_W
• i2c_ana_mst::date::DATE_R
• i2c_ana_mst::date::DATE_W
• i2c_ana_mst::date::R
• i2c_ana_mst::date::W
• i2c_ana_mst::i2c0_conf::CONF_R
• i2c_ana_mst::i2c0_conf::CONF_W
• i2c_ana_mst::i2c0_conf::R
• i2c_ana_mst::i2c0_conf::STATUS_R
• i2c_ana_mst::i2c0_conf::W
• i2c_ana_mst::i2c1_conf::CONF_R
• i2c_ana_mst::i2c1_conf::CONF_W
• i2c_ana_mst::i2c1_conf::R
• i2c_ana_mst::i2c1_conf::STATUS_R
• i2c_ana_mst::i2c1_conf::W
• i2c_ana_mst::i2c_ctrl1::R
• i2c_ana_mst::i2c_ctrl1::SCL_PULSE_DUR_R
• i2c_ana_mst::i2c_ctrl1::SCL_PULSE_DUR_W
• i2c_ana_mst::i2c_ctrl1::SDA_SIDE_GUARD_R
• i2c_ana_mst::i2c_ctrl1::SDA_SIDE_GUARD_W
• i2c_ana_mst::i2c_ctrl1::W
• i2c_ana_mst::i2c_ctrl::BUSY_R
• i2c_ana_mst::i2c_ctrl::DATA_R
• i2c_ana_mst::i2c_ctrl::DATA_W
• i2c_ana_mst::i2c_ctrl::R
• i2c_ana_mst::i2c_ctrl::READ_WRITE_R
• i2c_ana_mst::i2c_ctrl::READ_WRITE_W
• i2c_ana_mst::i2c_ctrl::SLAVE_ADDR_R
• i2c_ana_mst::i2c_ctrl::SLAVE_ADDR_W
• i2c_ana_mst::i2c_ctrl::SLAVE_REG_ADDR_R
• i2c_ana_mst::i2c_ctrl::SLAVE_REG_ADDR_W
• i2c_ana_mst::i2c_ctrl::W
• i2s0::CONF_SIGLE_DATA
• i2s0::DATE
• i2s0::ETM_CONF
• i2s0::INT_CLR
• i2s0::INT_ENA
• i2s0::INT_RAW
• i2s0::INT_ST
• i2s0::LC_HUNG_CONF
• i2s0::RXEOF_NUM
• i2s0::RX_CLKM_CONF
• i2s0::RX_CLKM_DIV_CONF
• i2s0::RX_CONF
• i2s0::RX_CONF1
• i2s0::RX_TDM_CTRL
• i2s0::RX_TIMING
• i2s0::STATE
• i2s0::TX_CLKM_CONF
• i2s0::TX_CLKM_DIV_CONF
• i2s0::TX_CONF
• i2s0::TX_CONF1
• i2s0::TX_PCM2PDM_CONF
• i2s0::TX_PCM2PDM_CONF1
• i2s0::TX_TDM_CTRL
• i2s0::TX_TIMING
• i2s0::conf_sigle_data::R
• i2s0::conf_sigle_data::SINGLE_DATA_R
• i2s0::conf_sigle_data::SINGLE_DATA_W
• i2s0::conf_sigle_data::W
• i2s0::date::DATE_R
• i2s0::date::DATE_W
• i2s0::date::R
• i2s0::date::W
• i2s0::etm_conf::ETM_RX_RECEIVE_WORD_NUM_R
• i2s0::etm_conf::ETM_RX_RECEIVE_WORD_NUM_W
• i2s0::etm_conf::ETM_TX_SEND_WORD_NUM_R
• i2s0::etm_conf::ETM_TX_SEND_WORD_NUM_W
• i2s0::etm_conf::R
• i2s0::etm_conf::W
• i2s0::int_clr::RX_DONE_W
• i2s0::int_clr::RX_HUNG_W
• i2s0::int_clr::TX_DONE_W
• i2s0::int_clr::TX_HUNG_W
• i2s0::int_clr::W
• i2s0::int_ena::R
• i2s0::int_ena::RX_DONE_R
• i2s0::int_ena::RX_DONE_W
• i2s0::int_ena::RX_HUNG_R
• i2s0::int_ena::RX_HUNG_W
• i2s0::int_ena::TX_DONE_R
• i2s0::int_ena::TX_DONE_W
• i2s0::int_ena::TX_HUNG_R
• i2s0::int_ena::TX_HUNG_W
• i2s0::int_ena::W
• i2s0::int_raw::R
• i2s0::int_raw::RX_DONE_R
• i2s0::int_raw::RX_HUNG_R
• i2s0::int_raw::TX_DONE_R
• i2s0::int_raw::TX_HUNG_R
• i2s0::int_st::R
• i2s0::int_st::RX_DONE_R
• i2s0::int_st::RX_HUNG_R
• i2s0::int_st::TX_DONE_R
• i2s0::int_st::TX_HUNG_R
• i2s0::lc_hung_conf::LC_FIFO_TIMEOUT_ENA_R
• i2s0::lc_hung_conf::LC_FIFO_TIMEOUT_ENA_W
• i2s0::lc_hung_conf::LC_FIFO_TIMEOUT_R
• i2s0::lc_hung_conf::LC_FIFO_TIMEOUT_SHIFT_R
• i2s0::lc_hung_conf::LC_FIFO_TIMEOUT_SHIFT_W
• i2s0::lc_hung_conf::LC_FIFO_TIMEOUT_W
• i2s0::lc_hung_conf::R
• i2s0::lc_hung_conf::W
• i2s0::rx_clkm_conf::MCLK_SEL_R
• i2s0::rx_clkm_conf::MCLK_SEL_W
• i2s0::rx_clkm_conf::R
• i2s0::rx_clkm_conf::RX_CLKM_DIV_NUM_R
• i2s0::rx_clkm_conf::RX_CLKM_DIV_NUM_W
• i2s0::rx_clkm_conf::RX_CLK_ACTIVE_R
• i2s0::rx_clkm_conf::RX_CLK_ACTIVE_W
• i2s0::rx_clkm_conf::RX_CLK_SEL_R
• i2s0::rx_clkm_conf::RX_CLK_SEL_W
• i2s0::rx_clkm_conf::W
• i2s0::rx_clkm_div_conf::R
• i2s0::rx_clkm_div_conf::RX_CLKM_DIV_X_R
• i2s0::rx_clkm_div_conf::RX_CLKM_DIV_X_W
• i2s0::rx_clkm_div_conf::RX_CLKM_DIV_YN1_R
• i2s0::rx_clkm_div_conf::RX_CLKM_DIV_YN1_W
• i2s0::rx_clkm_div_conf::RX_CLKM_DIV_Y_R
• i2s0::rx_clkm_div_conf::RX_CLKM_DIV_Y_W
• i2s0::rx_clkm_div_conf::RX_CLKM_DIV_Z_R
• i2s0::rx_clkm_div_conf::RX_CLKM_DIV_Z_W
• i2s0::rx_clkm_div_conf::W
• i2s0::rx_conf1::R
• i2s0::rx_conf1::RX_BCK_DIV_NUM_R
• i2s0::rx_conf1::RX_BCK_DIV_NUM_W
• i2s0::rx_conf1::RX_BITS_MOD_R
• i2s0::rx_conf1::RX_BITS_MOD_W
• i2s0::rx_conf1::RX_HALF_SAMPLE_BITS_R
• i2s0::rx_conf1::RX_HALF_SAMPLE_BITS_W
• i2s0::rx_conf1::RX_MSB_SHIFT_R
• i2s0::rx_conf1::RX_MSB_SHIFT_W
• i2s0::rx_conf1::RX_TDM_CHAN_BITS_R
• i2s0::rx_conf1::RX_TDM_CHAN_BITS_W
• i2s0::rx_conf1::RX_TDM_WS_WIDTH_R
• i2s0::rx_conf1::RX_TDM_WS_WIDTH_W
• i2s0::rx_conf1::W
• i2s0::rx_conf::R
• i2s0::rx_conf::RX_24_FILL_EN_R
• i2s0::rx_conf::RX_24_FILL_EN_W
• i2s0::rx_conf::RX_BIG_ENDIAN_R
• i2s0::rx_conf::RX_BIG_ENDIAN_W
• i2s0::rx_conf::RX_BIT_ORDER_R
• i2s0::rx_conf::RX_BIT_ORDER_W
• i2s0::rx_conf::RX_FIFO_RESET_W
• i2s0::rx_conf::RX_LEFT_ALIGN_R
• i2s0::rx_conf::RX_LEFT_ALIGN_W
• i2s0::rx_conf::RX_MONO_FST_VLD_R
• i2s0::rx_conf::RX_MONO_FST_VLD_W
• i2s0::rx_conf::RX_MONO_R
• i2s0::rx_conf::RX_MONO_W
• i2s0::rx_conf::RX_PCM_BYPASS_R
• i2s0::rx_conf::RX_PCM_BYPASS_W
• i2s0::rx_conf::RX_PCM_CONF_R
• i2s0::rx_conf::RX_PCM_CONF_W
• i2s0::rx_conf::RX_PDM_EN_R
• i2s0::rx_conf::RX_PDM_EN_W
• i2s0::rx_conf::RX_RESET_W
• i2s0::rx_conf::RX_SLAVE_MOD_R
• i2s0::rx_conf::RX_SLAVE_MOD_W
• i2s0::rx_conf::RX_START_R
• i2s0::rx_conf::RX_START_W
• i2s0::rx_conf::RX_STOP_MODE_R
• i2s0::rx_conf::RX_STOP_MODE_W
• i2s0::rx_conf::RX_TDM_EN_R
• i2s0::rx_conf::RX_TDM_EN_W
• i2s0::rx_conf::RX_UPDATE_R
• i2s0::rx_conf::RX_UPDATE_W
• i2s0::rx_conf::RX_WS_IDLE_POL_R
• i2s0::rx_conf::RX_WS_IDLE_POL_W
• i2s0::rx_conf::W
• i2s0::rx_tdm_ctrl::R
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN10_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN10_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN11_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN11_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN12_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN12_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN13_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN13_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN14_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN14_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN15_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN15_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN8_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN8_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN9_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_CHAN9_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN0_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN0_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN1_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN1_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN2_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN2_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN3_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN3_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN4_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN4_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN5_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN5_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN6_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN6_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN7_EN_R
• i2s0::rx_tdm_ctrl::RX_TDM_PDM_CHAN7_EN_W
• i2s0::rx_tdm_ctrl::RX_TDM_TOT_CHAN_NUM_R
• i2s0::rx_tdm_ctrl::RX_TDM_TOT_CHAN_NUM_W
• i2s0::rx_tdm_ctrl::W
• i2s0::rx_timing::R
• i2s0::rx_timing::RX_BCK_IN_DM_R
• i2s0::rx_timing::RX_BCK_IN_DM_W
• i2s0::rx_timing::RX_BCK_OUT_DM_R
• i2s0::rx_timing::RX_BCK_OUT_DM_W
• i2s0::rx_timing::RX_SD_IN_DM_R
• i2s0::rx_timing::RX_SD_IN_DM_W
• i2s0::rx_timing::RX_WS_IN_DM_R
• i2s0::rx_timing::RX_WS_IN_DM_W
• i2s0::rx_timing::RX_WS_OUT_DM_R
• i2s0::rx_timing::RX_WS_OUT_DM_W
• i2s0::rx_timing::W
• i2s0::rxeof_num::R
• i2s0::rxeof_num::RX_EOF_NUM_R
• i2s0::rxeof_num::RX_EOF_NUM_W
• i2s0::rxeof_num::W
• i2s0::state::R
• i2s0::state::TX_IDLE_R
• i2s0::tx_clkm_conf::CLK_EN_R
• i2s0::tx_clkm_conf::CLK_EN_W
• i2s0::tx_clkm_conf::R
• i2s0::tx_clkm_conf::TX_CLKM_DIV_NUM_R
• i2s0::tx_clkm_conf::TX_CLKM_DIV_NUM_W
• i2s0::tx_clkm_conf::TX_CLK_ACTIVE_R
• i2s0::tx_clkm_conf::TX_CLK_ACTIVE_W
• i2s0::tx_clkm_conf::TX_CLK_SEL_R
• i2s0::tx_clkm_conf::TX_CLK_SEL_W
• i2s0::tx_clkm_conf::W
• i2s0::tx_clkm_div_conf::R
• i2s0::tx_clkm_div_conf::TX_CLKM_DIV_X_R
• i2s0::tx_clkm_div_conf::TX_CLKM_DIV_X_W
• i2s0::tx_clkm_div_conf::TX_CLKM_DIV_YN1_R
• i2s0::tx_clkm_div_conf::TX_CLKM_DIV_YN1_W
• i2s0::tx_clkm_div_conf::TX_CLKM_DIV_Y_R
• i2s0::tx_clkm_div_conf::TX_CLKM_DIV_Y_W
• i2s0::tx_clkm_div_conf::TX_CLKM_DIV_Z_R
• i2s0::tx_clkm_div_conf::TX_CLKM_DIV_Z_W
• i2s0::tx_clkm_div_conf::W
• i2s0::tx_conf1::R
• i2s0::tx_conf1::TX_BCK_DIV_NUM_R
• i2s0::tx_conf1::TX_BCK_DIV_NUM_W
• i2s0::tx_conf1::TX_BCK_NO_DLY_R
• i2s0::tx_conf1::TX_BCK_NO_DLY_W
• i2s0::tx_conf1::TX_BITS_MOD_R
• i2s0::tx_conf1::TX_BITS_MOD_W
• i2s0::tx_conf1::TX_HALF_SAMPLE_BITS_R
• i2s0::tx_conf1::TX_HALF_SAMPLE_BITS_W
• i2s0::tx_conf1::TX_MSB_SHIFT_R
• i2s0::tx_conf1::TX_MSB_SHIFT_W
• i2s0::tx_conf1::TX_TDM_CHAN_BITS_R
• i2s0::tx_conf1::TX_TDM_CHAN_BITS_W
• i2s0::tx_conf1::TX_TDM_WS_WIDTH_R
• i2s0::tx_conf1::TX_TDM_WS_WIDTH_W
• i2s0::tx_conf1::W
• i2s0::tx_conf::R
• i2s0::tx_conf::SIG_LOOPBACK_R
• i2s0::tx_conf::SIG_LOOPBACK_W
• i2s0::tx_conf::TX_24_FILL_EN_R
• i2s0::tx_conf::TX_24_FILL_EN_W
• i2s0::tx_conf::TX_BIG_ENDIAN_R
• i2s0::tx_conf::TX_BIG_ENDIAN_W
• i2s0::tx_conf::TX_BIT_ORDER_R
• i2s0::tx_conf::TX_BIT_ORDER_W
• i2s0::tx_conf::TX_CHAN_EQUAL_R
• i2s0::tx_conf::TX_CHAN_EQUAL_W
• i2s0::tx_conf::TX_CHAN_MOD_R
• i2s0::tx_conf::TX_CHAN_MOD_W
• i2s0::tx_conf::TX_FIFO_RESET_W
• i2s0::tx_conf::TX_LEFT_ALIGN_R
• i2s0::tx_conf::TX_LEFT_ALIGN_W
• i2s0::tx_conf::TX_MONO_FST_VLD_R
• i2s0::tx_conf::TX_MONO_FST_VLD_W
• i2s0::tx_conf::TX_MONO_R
• i2s0::tx_conf::TX_MONO_W
• i2s0::tx_conf::TX_PCM_BYPASS_R
• i2s0::tx_conf::TX_PCM_BYPASS_W
• i2s0::tx_conf::TX_PCM_CONF_R
• i2s0::tx_conf::TX_PCM_CONF_W
• i2s0::tx_conf::TX_PDM_EN_R
• i2s0::tx_conf::TX_PDM_EN_W
• i2s0::tx_conf::TX_RESET_W
• i2s0::tx_conf::TX_SLAVE_MOD_R
• i2s0::tx_conf::TX_SLAVE_MOD_W
• i2s0::tx_conf::TX_START_R
• i2s0::tx_conf::TX_START_W
• i2s0::tx_conf::TX_STOP_EN_R
• i2s0::tx_conf::TX_STOP_EN_W
• i2s0::tx_conf::TX_TDM_EN_R
• i2s0::tx_conf::TX_TDM_EN_W
• i2s0::tx_conf::TX_UPDATE_R
• i2s0::tx_conf::TX_UPDATE_W
• i2s0::tx_conf::TX_WS_IDLE_POL_R
• i2s0::tx_conf::TX_WS_IDLE_POL_W
• i2s0::tx_conf::W
• i2s0::tx_pcm2pdm_conf1::R
• i2s0::tx_pcm2pdm_conf1::TX_IIR_HP_MULT12_0_R
• i2s0::tx_pcm2pdm_conf1::TX_IIR_HP_MULT12_0_W
• i2s0::tx_pcm2pdm_conf1::TX_IIR_HP_MULT12_5_R
• i2s0::tx_pcm2pdm_conf1::TX_IIR_HP_MULT12_5_W
• i2s0::tx_pcm2pdm_conf1::TX_PDM_FP_R
• i2s0::tx_pcm2pdm_conf1::TX_PDM_FP_W
• i2s0::tx_pcm2pdm_conf1::TX_PDM_FS_R
• i2s0::tx_pcm2pdm_conf1::TX_PDM_FS_W
• i2s0::tx_pcm2pdm_conf1::W
• i2s0::tx_pcm2pdm_conf::PCM2PDM_CONV_EN_R
• i2s0::tx_pcm2pdm_conf::PCM2PDM_CONV_EN_W
• i2s0::tx_pcm2pdm_conf::R
• i2s0::tx_pcm2pdm_conf::TX_PDM_DAC_2OUT_EN_R
• i2s0::tx_pcm2pdm_conf::TX_PDM_DAC_2OUT_EN_W
• i2s0::tx_pcm2pdm_conf::TX_PDM_DAC_MODE_EN_R
• i2s0::tx_pcm2pdm_conf::TX_PDM_DAC_MODE_EN_W
• i2s0::tx_pcm2pdm_conf::TX_PDM_HP_BYPASS_R
• i2s0::tx_pcm2pdm_conf::TX_PDM_HP_BYPASS_W
• i2s0::tx_pcm2pdm_conf::TX_PDM_HP_IN_SHIFT_R
• i2s0::tx_pcm2pdm_conf::TX_PDM_HP_IN_SHIFT_W
• i2s0::tx_pcm2pdm_conf::TX_PDM_LP_IN_SHIFT_R
• i2s0::tx_pcm2pdm_conf::TX_PDM_LP_IN_SHIFT_W
• i2s0::tx_pcm2pdm_conf::TX_PDM_PRESCALE_R
• i2s0::tx_pcm2pdm_conf::TX_PDM_PRESCALE_W
• i2s0::tx_pcm2pdm_conf::TX_PDM_SIGMADELTA_DITHER2_R
• i2s0::tx_pcm2pdm_conf::TX_PDM_SIGMADELTA_DITHER2_W
• i2s0::tx_pcm2pdm_conf::TX_PDM_SIGMADELTA_DITHER_R
• i2s0::tx_pcm2pdm_conf::TX_PDM_SIGMADELTA_DITHER_W
• i2s0::tx_pcm2pdm_conf::TX_PDM_SIGMADELTA_IN_SHIFT_R
• i2s0::tx_pcm2pdm_conf::TX_PDM_SIGMADELTA_IN_SHIFT_W
• i2s0::tx_pcm2pdm_conf::TX_PDM_SINC_IN_SHIFT_R
• i2s0::tx_pcm2pdm_conf::TX_PDM_SINC_IN_SHIFT_W
• i2s0::tx_pcm2pdm_conf::TX_PDM_SINC_OSR2_R
• i2s0::tx_pcm2pdm_conf::TX_PDM_SINC_OSR2_W
• i2s0::tx_pcm2pdm_conf::W
• i2s0::tx_tdm_ctrl::R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN0_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN0_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN10_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN10_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN11_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN11_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN12_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN12_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN13_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN13_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN14_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN14_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN15_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN15_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN1_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN1_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN2_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN2_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN3_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN3_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN4_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN4_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN5_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN5_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN6_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN6_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN7_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN7_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN8_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN8_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN9_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_CHAN9_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_SKIP_MSK_EN_R
• i2s0::tx_tdm_ctrl::TX_TDM_SKIP_MSK_EN_W
• i2s0::tx_tdm_ctrl::TX_TDM_TOT_CHAN_NUM_R
• i2s0::tx_tdm_ctrl::TX_TDM_TOT_CHAN_NUM_W
• i2s0::tx_tdm_ctrl::W
• i2s0::tx_timing::R
• i2s0::tx_timing::TX_BCK_IN_DM_R
• i2s0::tx_timing::TX_BCK_IN_DM_W
• i2s0::tx_timing::TX_BCK_OUT_DM_R
• i2s0::tx_timing::TX_BCK_OUT_DM_W
• i2s0::tx_timing::TX_SD1_OUT_DM_R
• i2s0::tx_timing::TX_SD1_OUT_DM_W
• i2s0::tx_timing::TX_SD_OUT_DM_R
• i2s0::tx_timing::TX_SD_OUT_DM_W
• i2s0::tx_timing::TX_WS_IN_DM_R
• i2s0::tx_timing::TX_WS_IN_DM_W
• i2s0::tx_timing::TX_WS_OUT_DM_R
• i2s0::tx_timing::TX_WS_OUT_DM_W
• i2s0::tx_timing::W
• ieee802154::ACK_FRAME_PENDING_EN
• ieee802154::ACK_TIMEOUT
• ieee802154::BB_CLK
• ieee802154::CCA_BUSY_CNT
• ieee802154::CCA_FAIL_CNT
• ieee802154::CHANNEL
• ieee802154::CLK_COUNTER
• ieee802154::CLK_COUNTER_MATCH_VAL
• ieee802154::COEX_PTI
• ieee802154::COMMAND
• ieee802154::CONT_RX_DELAY
• ieee802154::CORE_DUMMY_DATA
• ieee802154::CORE_GCK_CFG
• ieee802154::CRC_ERROR_CNT
• ieee802154::CTRL_CFG
• ieee802154::DCDC_CTRL
• ieee802154::DEBUG_CTRL
• ieee802154::DMA_DUMMY
• ieee802154::DMA_GCK_CFG
• ieee802154::DTM_CONFIG
• ieee802154::DTM_PKT_COUNTER
• ieee802154::DTM_TX_PKT_CONFIG
• ieee802154::ED_ABORT_CNT
• ieee802154::ED_SCAN_CFG
• ieee802154::ED_SCAN_COEX_CNT
• ieee802154::ED_SCAN_DURATION
• ieee802154::ENHANCE_ACK_CFG
• ieee802154::ERROR_CNT_CLEAR
• ieee802154::EVENT_EN
• ieee802154::EVENT_STATUS
• ieee802154::IFS
• ieee802154::IFS_COUNTER
• ieee802154::INF0_EXTEND_ADDR0
• ieee802154::INF0_EXTEND_ADDR1
• ieee802154::INF0_PAN_ID
• ieee802154::INF0_SHORT_ADDR
• ieee802154::INF1_EXTEND_ADDR0
• ieee802154::INF1_EXTEND_ADDR1
• ieee802154::INF1_PAN_ID
• ieee802154::INF1_SHORT_ADDR
• ieee802154::INF2_EXTEND_ADDR0
• ieee802154::INF2_EXTEND_ADDR1
• ieee802154::INF2_PAN_ID
• ieee802154::INF2_SHORT_ADDR
• ieee802154::INF3_EXTEND_ADDR0
• ieee802154::INF3_EXTEND_ADDR1
• ieee802154::INF3_PAN_ID
• ieee802154::INF3_SHORT_ADDR
• ieee802154::MAC_DATE
• ieee802154::NO_RSS_DETECT_CNT
• ieee802154::PAON_DELAY
• ieee802154::RXDMA_ADDR
• ieee802154::RXDMA_CTRL_STATE
• ieee802154::RXDMA_ERR
• ieee802154::RXON_DELAY
• ieee802154::RX_ABORT_COEX_CNT
• ieee802154::RX_ABORT_INTR_CTRL
• ieee802154::RX_ACK_ABORT_COEX_CNT
• ieee802154::RX_ACK_TIMEOUT_CNT
• ieee802154::RX_FILTER_FAIL_CNT
• ieee802154::RX_LENGTH
• ieee802154::RX_RESTART_CNT
• ieee802154::RX_STATUS
• ieee802154::SEC_CTRL
• ieee802154::SEC_EXTEND_ADDRESS0
• ieee802154::SEC_EXTEND_ADDRESS1
• ieee802154::SEC_KEY0
• ieee802154::SEC_KEY1
• ieee802154::SEC_KEY2
• ieee802154::SEC_KEY3
• ieee802154::SFD_TIMEOUT_CNT
• ieee802154::SFD_WAIT_SYMBOL
• ieee802154::TEST_CONTROL
• ieee802154::TIME0_THRESHOLD
• ieee802154::TIME0_VALUE
• ieee802154::TIME1_THRESHOLD
• ieee802154::TIME1_VALUE
• ieee802154::TXDMA_ADDR
• ieee802154::TXDMA_CTRL_STATE
• ieee802154::TXDMA_ERR
• ieee802154::TXEN_STOP_DELAY
• ieee802154::TXOFF_DELAY
• ieee802154::TXON_DELAY
• ieee802154::TXRX_PATH_DELAY
• ieee802154::TXRX_STATUS
• ieee802154::TXRX_SWITCH_DELAY
• ieee802154::TX_ABORT_INTERRUPT_CONTROL
• ieee802154::TX_ACK_ABORT_COEX_CNT
• ieee802154::TX_BREAK_COEX_CNT
• ieee802154::TX_CCM_SCHEDULE_STATUS
• ieee802154::TX_POWER
• ieee802154::TX_SECURITY_ERROR_CNT
• ieee802154::TX_STATUS
• ieee802154::ack_frame_pending_en::ACK_FRAME_PENDING_EN_R
• ieee802154::ack_frame_pending_en::ACK_FRAME_PENDING_EN_W
• ieee802154::ack_frame_pending_en::ACK_TX_ACK_TIMEOUT_R
• ieee802154::ack_frame_pending_en::ACK_TX_ACK_TIMEOUT_W
• ieee802154::ack_frame_pending_en::R
• ieee802154::ack_frame_pending_en::W
• ieee802154::ack_timeout::ACK_TIMEOUT_R
• ieee802154::ack_timeout::ACK_TIMEOUT_W
• ieee802154::ack_timeout::R
• ieee802154::ack_timeout::W
• ieee802154::bb_clk::FREQ_MINUS_1_R
• ieee802154::bb_clk::FREQ_MINUS_1_W
• ieee802154::bb_clk::R
• ieee802154::bb_clk::W
• ieee802154::cca_busy_cnt::CCA_BUSY_CNT_R
• ieee802154::cca_busy_cnt::CCA_BUSY_CNT_W
• ieee802154::cca_busy_cnt::R
• ieee802154::cca_busy_cnt::W
• ieee802154::cca_fail_cnt::CCA_FAIL_CNT_R
• ieee802154::cca_fail_cnt::CCA_FAIL_CNT_W
• ieee802154::cca_fail_cnt::R
• ieee802154::cca_fail_cnt::W
• ieee802154::channel::HOP_R
• ieee802154::channel::HOP_W
• ieee802154::channel::R
• ieee802154::channel::W
• ieee802154::clk_counter::CLK_625US_CNT_R
• ieee802154::clk_counter::CLK_625US_CNT_W
• ieee802154::clk_counter::R
• ieee802154::clk_counter::W
• ieee802154::clk_counter_match_val::CLK_COUNT_MATCH_VAL_R
• ieee802154::clk_counter_match_val::CLK_COUNT_MATCH_VAL_W
• ieee802154::clk_counter_match_val::R
• ieee802154::clk_counter_match_val::W
• ieee802154::coex_pti::CLOSE_RF_SEL_R
• ieee802154::coex_pti::CLOSE_RF_SEL_W
• ieee802154::coex_pti::COEX_ACK_PTI_R
• ieee802154::coex_pti::COEX_ACK_PTI_W
• ieee802154::coex_pti::COEX_PTI_R
• ieee802154::coex_pti::COEX_PTI_W
• ieee802154::coex_pti::R
• ieee802154::coex_pti::W
• ieee802154::command::OPCODE_R
• ieee802154::command::OPCODE_W
• ieee802154::command::R
• ieee802154::command::W
• ieee802154::cont_rx_delay::CONT_RX_DELAY_R
• ieee802154::cont_rx_delay::CONT_RX_DELAY_W
• ieee802154::cont_rx_delay::R
• ieee802154::cont_rx_delay::W
• ieee802154::core_dummy_data::CORE_DUMMY_DATA_R
• ieee802154::core_dummy_data::CORE_DUMMY_DATA_W
• ieee802154::core_dummy_data::R
• ieee802154::core_dummy_data::W
• ieee802154::core_gck_cfg::DIS_CTRL_GCK_R
• ieee802154::core_gck_cfg::DIS_CTRL_GCK_W
• ieee802154::core_gck_cfg::DIS_PKT_GCK_R
• ieee802154::core_gck_cfg::DIS_PKT_GCK_W
• ieee802154::core_gck_cfg::R
• ieee802154::core_gck_cfg::W
• ieee802154::crc_error_cnt::CRC_ERROR_CNT_R
• ieee802154::crc_error_cnt::CRC_ERROR_CNT_W
• ieee802154::crc_error_cnt::R
• ieee802154::crc_error_cnt::W
• ieee802154::ctrl_cfg::AUTOPEND_ENHANCE_R
• ieee802154::ctrl_cfg::AUTOPEND_ENHANCE_W
• ieee802154::ctrl_cfg::BIT_ORDER_R
• ieee802154::ctrl_cfg::BIT_ORDER_W
• ieee802154::ctrl_cfg::COEX_ARB_DELAY_R
• ieee802154::ctrl_cfg::COEX_ARB_DELAY_W
• ieee802154::ctrl_cfg::DIS_FRAME_VERSION_RSV_FILTER_R
• ieee802154::ctrl_cfg::DIS_FRAME_VERSION_RSV_FILTER_W
• ieee802154::ctrl_cfg::DIS_IFS_CONTROL_R
• ieee802154::ctrl_cfg::DIS_IFS_CONTROL_W
• ieee802154::ctrl_cfg::FILTER_ENHANCE_R
• ieee802154::ctrl_cfg::FILTER_ENHANCE_W
• ieee802154::ctrl_cfg::FORCE_RX_ENB_R
• ieee802154::ctrl_cfg::FORCE_RX_ENB_W
• ieee802154::ctrl_cfg::HW_AUTO_ACK_RX_EN_R
• ieee802154::ctrl_cfg::HW_AUTO_ACK_RX_EN_W
• ieee802154::ctrl_cfg::HW_AUTO_ACK_TX_EN_R
• ieee802154::ctrl_cfg::HW_AUTO_ACK_TX_EN_W
• ieee802154::ctrl_cfg::HW_ENHANCE_ACK_TX_EN_R
• ieee802154::ctrl_cfg::HW_ENHANCE_ACK_TX_EN_W
• ieee802154::ctrl_cfg::MAC_INF0_ENABLE_R
• ieee802154::ctrl_cfg::MAC_INF0_ENABLE_W
• ieee802154::ctrl_cfg::MAC_INF1_ENABLE_R
• ieee802154::ctrl_cfg::MAC_INF1_ENABLE_W
• ieee802154::ctrl_cfg::MAC_INF2_ENABLE_R
• ieee802154::ctrl_cfg::MAC_INF2_ENABLE_W
• ieee802154::ctrl_cfg::MAC_INF3_ENABLE_R
• ieee802154::ctrl_cfg::MAC_INF3_ENABLE_W
• ieee802154::ctrl_cfg::NO_RSS_TRK_ENB_R
• ieee802154::ctrl_cfg::NO_RSS_TRK_ENB_W
• ieee802154::ctrl_cfg::PAN_COORDINATOR_R
• ieee802154::ctrl_cfg::PAN_COORDINATOR_W
• ieee802154::ctrl_cfg::PROMISCUOUS_MODE_R
• ieee802154::ctrl_cfg::PROMISCUOUS_MODE_W
• ieee802154::ctrl_cfg::R
• ieee802154::ctrl_cfg::RX_DONE_TRIGGER_IDLE_R
• ieee802154::ctrl_cfg::RX_DONE_TRIGGER_IDLE_W
• ieee802154::ctrl_cfg::W
• ieee802154::dcdc_ctrl::DCDC_DOWN_DELAY_R
• ieee802154::dcdc_ctrl::DCDC_DOWN_DELAY_W
• ieee802154::dcdc_ctrl::DCDC_PRE_UP_DELAY_R
• ieee802154::dcdc_ctrl::DCDC_PRE_UP_DELAY_W
• ieee802154::dcdc_ctrl::EN_R
• ieee802154::dcdc_ctrl::EN_W
• ieee802154::dcdc_ctrl::R
• ieee802154::dcdc_ctrl::TX_DCDC_UP_R
• ieee802154::dcdc_ctrl::TX_DCDC_UP_W
• ieee802154::dcdc_ctrl::W
• ieee802154::debug_ctrl::DEBUG_SER_DEBUG_SEL_R
• ieee802154::debug_ctrl::DEBUG_SER_DEBUG_SEL_W
• ieee802154::debug_ctrl::DEBUG_SIGNAL_SEL_R
• ieee802154::debug_ctrl::DEBUG_SIGNAL_SEL_W
• ieee802154::debug_ctrl::DEBUG_STATE_MATCH_DUMP_EN_R
• ieee802154::debug_ctrl::DEBUG_STATE_MATCH_DUMP_EN_W
• ieee802154::debug_ctrl::DEBUG_TRIGGER_DUMP_EN_R
• ieee802154::debug_ctrl::DEBUG_TRIGGER_DUMP_EN_W
• ieee802154::debug_ctrl::DEBUG_TRIGGER_PULSE_SELECT_R
• ieee802154::debug_ctrl::DEBUG_TRIGGER_PULSE_SELECT_W
• ieee802154::debug_ctrl::DEBUG_TRIGGER_STATE_MATCH_VALUE_R
• ieee802154::debug_ctrl::DEBUG_TRIGGER_STATE_MATCH_VALUE_W
• ieee802154::debug_ctrl::DEBUG_TRIGGER_STATE_SELECT_R
• ieee802154::debug_ctrl::DEBUG_TRIGGER_STATE_SELECT_W
• ieee802154::debug_ctrl::R
• ieee802154::debug_ctrl::W
• ieee802154::dma_dummy::DATA_R
• ieee802154::dma_dummy::DATA_W
• ieee802154::dma_dummy::R
• ieee802154::dma_dummy::W
• ieee802154::dma_gck_cfg::DMA_GCK_CFG_R
• ieee802154::dma_gck_cfg::DMA_GCK_CFG_W
• ieee802154::dma_gck_cfg::R
• ieee802154::dma_gck_cfg::W
• ieee802154::dtm_config::DTMCH_TX_LENGTH_R
• ieee802154::dtm_config::DTMCH_TX_LENGTH_W
• ieee802154::dtm_config::DTM_CONTRX_EN_R
• ieee802154::dtm_config::DTM_CONTRX_EN_W
• ieee802154::dtm_config::DTM_HOP_FREQ_R
• ieee802154::dtm_config::DTM_HOP_FREQ_W
• ieee802154::dtm_config::DTM_ON_R
• ieee802154::dtm_config::DTM_ON_W
• ieee802154::dtm_config::DTM_TX_PLD_TYPE_R
• ieee802154::dtm_config::DTM_TX_PLD_TYPE_W
• ieee802154::dtm_config::R
• ieee802154::dtm_config::W
• ieee802154::dtm_pkt_counter::DTM_CRC_ERR_PKT_COUNT_R
• ieee802154::dtm_pkt_counter::DTM_CRC_ERR_PKT_COUNT_W
• ieee802154::dtm_pkt_counter::DTM_TXRX_PKT_COUNT_R
• ieee802154::dtm_pkt_counter::DTM_TXRX_PKT_COUNT_W
• ieee802154::dtm_pkt_counter::R
• ieee802154::dtm_pkt_counter::W
• ieee802154::dtm_tx_pkt_config::DTM_TX_PKT_THRESHOLD_R
• ieee802154::dtm_tx_pkt_config::DTM_TX_PKT_THRESHOLD_W
• ieee802154::dtm_tx_pkt_config::R
• ieee802154::dtm_tx_pkt_config::W
• ieee802154::ed_abort_cnt::ED_ABORT_CNT_R
• ieee802154::ed_abort_cnt::ED_ABORT_CNT_W
• ieee802154::ed_abort_cnt::R
• ieee802154::ed_abort_cnt::W
• ieee802154::ed_scan_cfg::CCA_BUSY_R
• ieee802154::ed_scan_cfg::CCA_BUSY_W
• ieee802154::ed_scan_cfg::CCA_ED_THRESHOLD_R
• ieee802154::ed_scan_cfg::CCA_ED_THRESHOLD_W
• ieee802154::ed_scan_cfg::CCA_MODE_R
• ieee802154::ed_scan_cfg::CCA_MODE_W
• ieee802154::ed_scan_cfg::DIS_ED_POWER_SEL_R
• ieee802154::ed_scan_cfg::DIS_ED_POWER_SEL_W
• ieee802154::ed_scan_cfg::ED_RSS_R
• ieee802154::ed_scan_cfg::ED_RSS_W
• ieee802154::ed_scan_cfg::ED_SAMPLE_MODE_R
• ieee802154::ed_scan_cfg::ED_SAMPLE_MODE_W
• ieee802154::ed_scan_cfg::R
• ieee802154::ed_scan_cfg::W
• ieee802154::ed_scan_coex_cnt::ED_SCAN_COEX_CNT_R
• ieee802154::ed_scan_coex_cnt::ED_SCAN_COEX_CNT_W
• ieee802154::ed_scan_coex_cnt::R
• ieee802154::ed_scan_coex_cnt::W
• ieee802154::ed_scan_duration::ED_SCAN_DURATION_R
• ieee802154::ed_scan_duration::ED_SCAN_DURATION_W
• ieee802154::ed_scan_duration::ED_SCAN_WAIT_DLY_R
• ieee802154::ed_scan_duration::ED_SCAN_WAIT_DLY_W
• ieee802154::ed_scan_duration::R
• ieee802154::ed_scan_duration::W
• ieee802154::enhance_ack_cfg::R
• ieee802154::enhance_ack_cfg::TX_ENH_ACK_GENERATE_DONE_NOTIFY_R
• ieee802154::enhance_ack_cfg::TX_ENH_ACK_GENERATE_DONE_NOTIFY_W
• ieee802154::enhance_ack_cfg::W
• ieee802154::error_cnt_clear::CCA_BUSY_CNT_CLEAR_R
• ieee802154::error_cnt_clear::CCA_BUSY_CNT_CLEAR_W
• ieee802154::error_cnt_clear::CCA_FAIL_CNT_CLEAR_R
• ieee802154::error_cnt_clear::CCA_FAIL_CNT_CLEAR_W
• ieee802154::error_cnt_clear::CRC_ERROR_CNT_CLEAR_R
• ieee802154::error_cnt_clear::CRC_ERROR_CNT_CLEAR_W
• ieee802154::error_cnt_clear::ED_ABORT_CNT_CLEAR_R
• ieee802154::error_cnt_clear::ED_ABORT_CNT_CLEAR_W
• ieee802154::error_cnt_clear::ED_SCAN_COEX_CNT_CLEAR_R
• ieee802154::error_cnt_clear::ED_SCAN_COEX_CNT_CLEAR_W
• ieee802154::error_cnt_clear::NO_RSS_DETECT_CNT_CLEAR_R
• ieee802154::error_cnt_clear::NO_RSS_DETECT_CNT_CLEAR_W
• ieee802154::error_cnt_clear::R
• ieee802154::error_cnt_clear::RX_ABORT_COEX_CNT_CLEAR_R
• ieee802154::error_cnt_clear::RX_ABORT_COEX_CNT_CLEAR_W
• ieee802154::error_cnt_clear::RX_ACK_ABORT_COEX_CNT_CLEAR_R
• ieee802154::error_cnt_clear::RX_ACK_ABORT_COEX_CNT_CLEAR_W
• ieee802154::error_cnt_clear::RX_ACK_TIMEOUT_CNT_CLEAR_R
• ieee802154::error_cnt_clear::RX_ACK_TIMEOUT_CNT_CLEAR_W
• ieee802154::error_cnt_clear::RX_FILTER_FAIL_CNT_CLEAR_R
• ieee802154::error_cnt_clear::RX_FILTER_FAIL_CNT_CLEAR_W
• ieee802154::error_cnt_clear::RX_RESTART_CNT_CLEAR_R
• ieee802154::error_cnt_clear::RX_RESTART_CNT_CLEAR_W
• ieee802154::error_cnt_clear::SFD_TIMEOUT_CNT_CLEAR_R
• ieee802154::error_cnt_clear::SFD_TIMEOUT_CNT_CLEAR_W
• ieee802154::error_cnt_clear::TX_ACK_ABORT_COEX_CNT_CLEAR_R
• ieee802154::error_cnt_clear::TX_ACK_ABORT_COEX_CNT_CLEAR_W
• ieee802154::error_cnt_clear::TX_BREAK_COEX_CNT_CLEAR_R
• ieee802154::error_cnt_clear::TX_BREAK_COEX_CNT_CLEAR_W
• ieee802154::error_cnt_clear::TX_SECURITY_ERROR_CNT_CLEAR_R
• ieee802154::error_cnt_clear::TX_SECURITY_ERROR_CNT_CLEAR_W
• ieee802154::error_cnt_clear::W
• ieee802154::event_en::EVENT_EN_R
• ieee802154::event_en::EVENT_EN_W
• ieee802154::event_en::R
• ieee802154::event_en::W
• ieee802154::event_status::EVENT_STATUS_R
• ieee802154::event_status::EVENT_STATUS_W
• ieee802154::event_status::R
• ieee802154::event_status::W
• ieee802154::ifs::LIFS_R
• ieee802154::ifs::LIFS_W
• ieee802154::ifs::R
• ieee802154::ifs::SIFS_R
• ieee802154::ifs::SIFS_W
• ieee802154::ifs::W
• ieee802154::ifs_counter::EN_R
• ieee802154::ifs_counter::EN_W
• ieee802154::ifs_counter::IFS_COUNTER_R
• ieee802154::ifs_counter::IFS_COUNTER_W
• ieee802154::ifs_counter::R
• ieee802154::ifs_counter::W
• ieee802154::inf0_extend_addr0::MAC_INF0_EXTEND_ADDR0_R
• ieee802154::inf0_extend_addr0::MAC_INF0_EXTEND_ADDR0_W
• ieee802154::inf0_extend_addr0::R
• ieee802154::inf0_extend_addr0::W
• ieee802154::inf0_extend_addr1::MAC_INF0_EXTEND_ADDR1_R
• ieee802154::inf0_extend_addr1::MAC_INF0_EXTEND_ADDR1_W
• ieee802154::inf0_extend_addr1::R
• ieee802154::inf0_extend_addr1::W
• ieee802154::inf0_pan_id::MAC_INF0_PAN_ID_R
• ieee802154::inf0_pan_id::MAC_INF0_PAN_ID_W
• ieee802154::inf0_pan_id::R
• ieee802154::inf0_pan_id::W
• ieee802154::inf0_short_addr::MAC_INF0_SHORT_ADDR_R
• ieee802154::inf0_short_addr::MAC_INF0_SHORT_ADDR_W
• ieee802154::inf0_short_addr::R
• ieee802154::inf0_short_addr::W
• ieee802154::inf1_extend_addr0::MAC_INF1_EXTEND_ADDR0_R
• ieee802154::inf1_extend_addr0::MAC_INF1_EXTEND_ADDR0_W
• ieee802154::inf1_extend_addr0::R
• ieee802154::inf1_extend_addr0::W
• ieee802154::inf1_extend_addr1::MAC_INF1_EXTEND_ADDR1_R
• ieee802154::inf1_extend_addr1::MAC_INF1_EXTEND_ADDR1_W
• ieee802154::inf1_extend_addr1::R
• ieee802154::inf1_extend_addr1::W
• ieee802154::inf1_pan_id::MAC_INF1_PAN_ID_R
• ieee802154::inf1_pan_id::MAC_INF1_PAN_ID_W
• ieee802154::inf1_pan_id::R
• ieee802154::inf1_pan_id::W
• ieee802154::inf1_short_addr::MAC_INF1_SHORT_ADDR_R
• ieee802154::inf1_short_addr::MAC_INF1_SHORT_ADDR_W
• ieee802154::inf1_short_addr::R
• ieee802154::inf1_short_addr::W
• ieee802154::inf2_extend_addr0::MAC_INF2_EXTEND_ADDR0_R
• ieee802154::inf2_extend_addr0::MAC_INF2_EXTEND_ADDR0_W
• ieee802154::inf2_extend_addr0::R
• ieee802154::inf2_extend_addr0::W
• ieee802154::inf2_extend_addr1::MAC_INF2_EXTEND_ADDR1_R
• ieee802154::inf2_extend_addr1::MAC_INF2_EXTEND_ADDR1_W
• ieee802154::inf2_extend_addr1::R
• ieee802154::inf2_extend_addr1::W
• ieee802154::inf2_pan_id::MAC_INF2_PAN_ID_R
• ieee802154::inf2_pan_id::MAC_INF2_PAN_ID_W
• ieee802154::inf2_pan_id::R
• ieee802154::inf2_pan_id::W
• ieee802154::inf2_short_addr::MAC_INF2_SHORT_ADDR_R
• ieee802154::inf2_short_addr::MAC_INF2_SHORT_ADDR_W
• ieee802154::inf2_short_addr::R
• ieee802154::inf2_short_addr::W
• ieee802154::inf3_extend_addr0::MAC_INF3_EXTEND_ADDR0_R
• ieee802154::inf3_extend_addr0::MAC_INF3_EXTEND_ADDR0_W
• ieee802154::inf3_extend_addr0::R
• ieee802154::inf3_extend_addr0::W
• ieee802154::inf3_extend_addr1::MAC_INF3_EXTEND_ADDR1_R
• ieee802154::inf3_extend_addr1::MAC_INF3_EXTEND_ADDR1_W
• ieee802154::inf3_extend_addr1::R
• ieee802154::inf3_extend_addr1::W
• ieee802154::inf3_pan_id::MAC_INF3_PAN_ID_R
• ieee802154::inf3_pan_id::MAC_INF3_PAN_ID_W
• ieee802154::inf3_pan_id::R
• ieee802154::inf3_pan_id::W
• ieee802154::inf3_short_addr::MAC_INF3_SHORT_ADDR_R
• ieee802154::inf3_short_addr::MAC_INF3_SHORT_ADDR_W
• ieee802154::inf3_short_addr::R
• ieee802154::inf3_short_addr::W
• ieee802154::mac_date::MAC_DATE_R
• ieee802154::mac_date::MAC_DATE_W
• ieee802154::mac_date::R
• ieee802154::mac_date::W
• ieee802154::no_rss_detect_cnt::NO_RSS_DETECT_CNT_R
• ieee802154::no_rss_detect_cnt::NO_RSS_DETECT_CNT_W
• ieee802154::no_rss_detect_cnt::R
• ieee802154::no_rss_detect_cnt::W
• ieee802154::paon_delay::PAON_DELAY_R
• ieee802154::paon_delay::PAON_DELAY_W
• ieee802154::paon_delay::R
• ieee802154::paon_delay::W
• ieee802154::rx_abort_coex_cnt::R
• ieee802154::rx_abort_coex_cnt::RX_ABORT_COEX_CNT_R
• ieee802154::rx_abort_coex_cnt::RX_ABORT_COEX_CNT_W
• ieee802154::rx_abort_coex_cnt::W
• ieee802154::rx_abort_intr_ctrl::R
• ieee802154::rx_abort_intr_ctrl::RX_ABORT_INTR_CTRL_R
• ieee802154::rx_abort_intr_ctrl::RX_ABORT_INTR_CTRL_W
• ieee802154::rx_abort_intr_ctrl::W
• ieee802154::rx_ack_abort_coex_cnt::R
• ieee802154::rx_ack_abort_coex_cnt::RX_ACK_ABORT_COEX_CNT_R
• ieee802154::rx_ack_abort_coex_cnt::RX_ACK_ABORT_COEX_CNT_W
• ieee802154::rx_ack_abort_coex_cnt::W
• ieee802154::rx_ack_timeout_cnt::R
• ieee802154::rx_ack_timeout_cnt::RX_ACK_TIMEOUT_CNT_R
• ieee802154::rx_ack_timeout_cnt::RX_ACK_TIMEOUT_CNT_W
• ieee802154::rx_ack_timeout_cnt::W
• ieee802154::rx_filter_fail_cnt::R
• ieee802154::rx_filter_fail_cnt::RX_FILTER_FAIL_CNT_R
• ieee802154::rx_filter_fail_cnt::RX_FILTER_FAIL_CNT_W
• ieee802154::rx_filter_fail_cnt::W
• ieee802154::rx_length::R
• ieee802154::rx_length::RX_LENGTH_R
• ieee802154::rx_length::RX_LENGTH_W
• ieee802154::rx_length::W
• ieee802154::rx_restart_cnt::R
• ieee802154::rx_restart_cnt::RX_RESTART_CNT_R
• ieee802154::rx_restart_cnt::RX_RESTART_CNT_W
• ieee802154::rx_restart_cnt::W
• ieee802154::rx_status::FILTER_FAIL_STATUS_R
• ieee802154::rx_status::FILTER_FAIL_STATUS_W
• ieee802154::rx_status::PREAMBLE_MATCH_R
• ieee802154::rx_status::PREAMBLE_MATCH_W
• ieee802154::rx_status::R
• ieee802154::rx_status::RX_ABORT_STATUS_R
• ieee802154::rx_status::RX_ABORT_STATUS_W
• ieee802154::rx_status::RX_STATE_R
• ieee802154::rx_status::RX_STATE_W
• ieee802154::rx_status::SFD_MATCH_R
• ieee802154::rx_status::SFD_MATCH_W
• ieee802154::rx_status::W
• ieee802154::rxdma_addr::R
• ieee802154::rxdma_addr::RXDMA_ADDR_R
• ieee802154::rxdma_addr::RXDMA_ADDR_W
• ieee802154::rxdma_addr::W
• ieee802154::rxdma_ctrl_state::R
• ieee802154::rxdma_ctrl_state::RXDMA_APPEND_FREQ_OFFSET_R
• ieee802154::rxdma_ctrl_state::RXDMA_APPEND_FREQ_OFFSET_W
• ieee802154::rxdma_ctrl_state::RXDMA_APPEND_LQI_OFFSET_R
• ieee802154::rxdma_ctrl_state::RXDMA_APPEND_LQI_OFFSET_W
• ieee802154::rxdma_ctrl_state::RXDMA_STATE_R
• ieee802154::rxdma_ctrl_state::RXDMA_STATE_W
• ieee802154::rxdma_ctrl_state::RXDMA_WATER_LEVEL_R
• ieee802154::rxdma_ctrl_state::RXDMA_WATER_LEVEL_W
• ieee802154::rxdma_ctrl_state::W
• ieee802154::rxdma_err::R
• ieee802154::rxdma_err::RXDMA_ERR_R
• ieee802154::rxdma_err::RXDMA_ERR_W
• ieee802154::rxdma_err::W
• ieee802154::rxon_delay::R
• ieee802154::rxon_delay::RXON_DELAY_R
• ieee802154::rxon_delay::RXON_DELAY_W
• ieee802154::rxon_delay::W
• ieee802154::sec_ctrl::R
• ieee802154::sec_ctrl::SEC_EN_R
• ieee802154::sec_ctrl::SEC_EN_W
• ieee802154::sec_ctrl::SEC_PAYLOAD_OFFSET_R
• ieee802154::sec_ctrl::SEC_PAYLOAD_OFFSET_W
• ieee802154::sec_ctrl::W
• ieee802154::sec_extend_address0::R
• ieee802154::sec_extend_address0::SEC_EXTEND_ADDRESS0_R
• ieee802154::sec_extend_address0::SEC_EXTEND_ADDRESS0_W
• ieee802154::sec_extend_address0::W
• ieee802154::sec_extend_address1::R
• ieee802154::sec_extend_address1::SEC_EXTEND_ADDRESS1_R
• ieee802154::sec_extend_address1::SEC_EXTEND_ADDRESS1_W
• ieee802154::sec_extend_address1::W
• ieee802154::sec_key0::R
• ieee802154::sec_key0::SEC_KEY0_R
• ieee802154::sec_key0::SEC_KEY0_W
• ieee802154::sec_key0::W
• ieee802154::sec_key1::R
• ieee802154::sec_key1::SEC_KEY1_R
• ieee802154::sec_key1::SEC_KEY1_W
• ieee802154::sec_key1::W
• ieee802154::sec_key2::R
• ieee802154::sec_key2::SEC_KEY2_R
• ieee802154::sec_key2::SEC_KEY2_W
• ieee802154::sec_key2::W
• ieee802154::sec_key3::R
• ieee802154::sec_key3::SEC_KEY3_R
• ieee802154::sec_key3::SEC_KEY3_W
• ieee802154::sec_key3::W
• ieee802154::sfd_timeout_cnt::R
• ieee802154::sfd_timeout_cnt::SFD_TIMEOUT_CNT_R
• ieee802154::sfd_timeout_cnt::SFD_TIMEOUT_CNT_W
• ieee802154::sfd_timeout_cnt::W
• ieee802154::sfd_wait_symbol::NUM_R
• ieee802154::sfd_wait_symbol::NUM_W
• ieee802154::sfd_wait_symbol::R
• ieee802154::sfd_wait_symbol::W
• ieee802154::test_control::R
• ieee802154::test_control::W
• ieee802154::test_control::WRONG_CRC_R
• ieee802154::test_control::WRONG_CRC_W
• ieee802154::time0_threshold::R
• ieee802154::time0_threshold::TIMER0_THRESHOLD_R
• ieee802154::time0_threshold::TIMER0_THRESHOLD_W
• ieee802154::time0_threshold::W
• ieee802154::time0_value::R
• ieee802154::time0_value::TIMER0_VALUE_R
• ieee802154::time0_value::TIMER0_VALUE_W
• ieee802154::time0_value::W
• ieee802154::time1_threshold::R
• ieee802154::time1_threshold::TIMER1_THRESHOLD_R
• ieee802154::time1_threshold::TIMER1_THRESHOLD_W
• ieee802154::time1_threshold::W
• ieee802154::time1_value::R
• ieee802154::time1_value::TIMER1_VALUE_R
• ieee802154::time1_value::TIMER1_VALUE_W
• ieee802154::time1_value::W
• ieee802154::tx_abort_interrupt_control::R
• ieee802154::tx_abort_interrupt_control::TX_ABORT_INTERRUPT_CONTROL_R
• ieee802154::tx_abort_interrupt_control::TX_ABORT_INTERRUPT_CONTROL_W
• ieee802154::tx_abort_interrupt_control::W
• ieee802154::tx_ack_abort_coex_cnt::R
• ieee802154::tx_ack_abort_coex_cnt::TX_ACK_ABORT_COEX_CNT_R
• ieee802154::tx_ack_abort_coex_cnt::TX_ACK_ABORT_COEX_CNT_W
• ieee802154::tx_ack_abort_coex_cnt::W
• ieee802154::tx_break_coex_cnt::R
• ieee802154::tx_break_coex_cnt::TX_BREAK_COEX_CNT_R
• ieee802154::tx_break_coex_cnt::TX_BREAK_COEX_CNT_W
• ieee802154::tx_break_coex_cnt::W
• ieee802154::tx_ccm_schedule_status::R
• ieee802154::tx_ccm_schedule_status::TX_CCM_SCHEDULE_STATUS_R
• ieee802154::tx_ccm_schedule_status::TX_CCM_SCHEDULE_STATUS_W
• ieee802154::tx_ccm_schedule_status::W
• ieee802154::tx_power::R
• ieee802154::tx_power::TX_POWER_R
• ieee802154::tx_power::TX_POWER_W
• ieee802154::tx_power::W
• ieee802154::tx_security_error_cnt::R
• ieee802154::tx_security_error_cnt::TX_SECURITY_ERROR_CNT_R
• ieee802154::tx_security_error_cnt::TX_SECURITY_ERROR_CNT_W
• ieee802154::tx_security_error_cnt::W
• ieee802154::tx_status::R
• ieee802154::tx_status::TX_ABORT_STATUS_R
• ieee802154::tx_status::TX_ABORT_STATUS_W
• ieee802154::tx_status::TX_SEC_ERROR_CODE_R
• ieee802154::tx_status::TX_SEC_ERROR_CODE_W
• ieee802154::tx_status::TX_STATE_R
• ieee802154::tx_status::TX_STATE_W
• ieee802154::tx_status::W
• ieee802154::txdma_addr::R
• ieee802154::txdma_addr::TXDMA_ADDR_R
• ieee802154::txdma_addr::TXDMA_ADDR_W
• ieee802154::txdma_addr::W
• ieee802154::txdma_ctrl_state::R
• ieee802154::txdma_ctrl_state::TXDMA_FETCH_BYTE_CNT_R
• ieee802154::txdma_ctrl_state::TXDMA_FETCH_BYTE_CNT_W
• ieee802154::txdma_ctrl_state::TXDMA_FILL_ENTRY_R
• ieee802154::txdma_ctrl_state::TXDMA_FILL_ENTRY_W
• ieee802154::txdma_ctrl_state::TXDMA_STATE_R
• ieee802154::txdma_ctrl_state::TXDMA_STATE_W
• ieee802154::txdma_ctrl_state::TXDMA_WATER_LEVEL_R
• ieee802154::txdma_ctrl_state::TXDMA_WATER_LEVEL_W
• ieee802154::txdma_ctrl_state::W
• ieee802154::txdma_err::R
• ieee802154::txdma_err::TXDMA_ERR_R
• ieee802154::txdma_err::TXDMA_ERR_W
• ieee802154::txdma_err::W
• ieee802154::txen_stop_delay::R
• ieee802154::txen_stop_delay::TXEN_STOP_DLY_R
• ieee802154::txen_stop_delay::TXEN_STOP_DLY_W
• ieee802154::txen_stop_delay::W
• ieee802154::txoff_delay::R
• ieee802154::txoff_delay::TXOFF_DELAY_R
• ieee802154::txoff_delay::TXOFF_DELAY_W
• ieee802154::txoff_delay::W
• ieee802154::txon_delay::R
• ieee802154::txon_delay::TXON_DELAY_R
• ieee802154::txon_delay::TXON_DELAY_W
• ieee802154::txon_delay::W
• ieee802154::txrx_path_delay::R
• ieee802154::txrx_path_delay::RX_PATH_DELAY_R
• ieee802154::txrx_path_delay::RX_PATH_DELAY_W
• ieee802154::txrx_path_delay::TX_PATH_DELAY_R
• ieee802154::txrx_path_delay::TX_PATH_DELAY_W
• ieee802154::txrx_path_delay::W
• ieee802154::txrx_status::ED_PROC_R
• ieee802154::txrx_status::ED_PROC_W
• ieee802154::txrx_status::ED_TRIGGER_TX_PROC_R
• ieee802154::txrx_status::ED_TRIGGER_TX_PROC_W
• ieee802154::txrx_status::R
• ieee802154::txrx_status::RF_CTRL_STATE_R
• ieee802154::txrx_status::RF_CTRL_STATE_W
• ieee802154::txrx_status::RX_PROC_R
• ieee802154::txrx_status::RX_PROC_W
• ieee802154::txrx_status::TXRX_STATE_R
• ieee802154::txrx_status::TXRX_STATE_W
• ieee802154::txrx_status::TX_PROC_R
• ieee802154::txrx_status::TX_PROC_W
• ieee802154::txrx_status::W
• ieee802154::txrx_switch_delay::R
• ieee802154::txrx_switch_delay::TXRX_SWITCH_DELAY_R
• ieee802154::txrx_switch_delay::TXRX_SWITCH_DELAY_W
• ieee802154::txrx_switch_delay::W
• interrupt_core0::AES_INTR_MAP
• interrupt_core0::APB_ADC_INTR_MAP
• interrupt_core0::ASSIST_DEBUG_INTR_MAP
• interrupt_core0::BLE_SEC_INTR_MAP
• interrupt_core0::BLE_TIMER_INTR_MAP
• interrupt_core0::BT_BB_INTR_MAP
• interrupt_core0::BT_BB_NMI_MAP
• interrupt_core0::BT_MAC_INTR_MAP
• interrupt_core0::CACHE_INTR_MAP
• interrupt_core0::CAN0_INTR_MAP
• interrupt_core0::CAN1_INTR_MAP
• interrupt_core0::CLOCK_GATE
• interrupt_core0::COEX_INTR_MAP
• interrupt_core0::CPU_INTR_FROM_CPU_0_MAP
• interrupt_core0::CPU_INTR_FROM_CPU_1_MAP
• interrupt_core0::CPU_INTR_FROM_CPU_2_MAP
• interrupt_core0::CPU_INTR_FROM_CPU_3_MAP
• interrupt_core0::CPU_PERI_TIMEOUT_INTR_MAP
• interrupt_core0::DMA_IN_CH0_INTR_MAP
• interrupt_core0::DMA_IN_CH1_INTR_MAP
• interrupt_core0::DMA_IN_CH2_INTR_MAP
• interrupt_core0::DMA_OUT_CH0_INTR_MAP
• interrupt_core0::DMA_OUT_CH1_INTR_MAP
• interrupt_core0::DMA_OUT_CH2_INTR_MAP
• interrupt_core0::ECC_INTR_MAP
• interrupt_core0::EFUSE_INTR_MAP
• interrupt_core0::GPIO_INTERRUPT_PRO_MAP
• interrupt_core0::GPIO_INTERRUPT_PRO_NMI_MAP
• interrupt_core0::GPSPI2_INTR_MAP
• interrupt_core0::HP_APM_M0_INTR_MAP
• interrupt_core0::HP_APM_M1_INTR_MAP
• interrupt_core0::HP_APM_M2_INTR_MAP
• interrupt_core0::HP_APM_M3_INTR_MAP
• interrupt_core0::HP_PERI_TIMEOUT_INTR_MAP
• interrupt_core0::I2C_EXT0_INTR_MAP
• interrupt_core0::I2C_MST_INTR_MAP
• interrupt_core0::I2S1_INTR_MAP
• interrupt_core0::INTERRUPT_REG_DATE
• interrupt_core0::INTR_STATUS_REG_0
• interrupt_core0::INTR_STATUS_REG_1
• interrupt_core0::INT_STATUS_REG_2
• interrupt_core0::LEDC_INTR_MAP
• interrupt_core0::LP_APM0_INTR_MAP
• interrupt_core0::LP_APM_M0_INTR_MAP
• interrupt_core0::LP_APM_M1_INTR_MAP
• interrupt_core0::LP_I2C_INTR_MAP
• interrupt_core0::LP_PERI_TIMEOUT_INTR_MAP
• interrupt_core0::LP_RTC_TIMER_INTR_MAP
• interrupt_core0::LP_TIMER_INTR_MAP
• interrupt_core0::LP_UART_INTR_MAP
• interrupt_core0::LP_WDT_INTR_MAP
• interrupt_core0::MODEM_PERI_TIMEOUT_INTR_MAP
• interrupt_core0::MSPI_INTR_MAP
• interrupt_core0::PARL_IO_INTR_MAP
• interrupt_core0::PAU_INTR_MAP
• interrupt_core0::PCNT_INTR_MAP
• interrupt_core0::PMU_INTR_MAP
• interrupt_core0::PWM_INTR_MAP
• interrupt_core0::RMT_INTR_MAP
• interrupt_core0::RSA_INTR_MAP
• interrupt_core0::SHA_INTR_MAP
• interrupt_core0::SLC0_INTR_MAP
• interrupt_core0::SLC1_INTR_MAP
• interrupt_core0::SYSTIMER_TARGET0_INTR_MAP
• interrupt_core0::SYSTIMER_TARGET1_INTR_MAP
• interrupt_core0::SYSTIMER_TARGET2_INTR_MAP
• interrupt_core0::TG0_T0_INTR_MAP
• interrupt_core0::TG0_T1_INTR_MAP
• interrupt_core0::TG0_WDT_INTR_MAP
• interrupt_core0::TG1_T0_INTR_MAP
• interrupt_core0::TG1_T1_INTR_MAP
• interrupt_core0::TG1_WDT_INTR_MAP
• interrupt_core0::TRACE_INTR_MAP
• interrupt_core0::UART0_INTR_MAP
• interrupt_core0::UART1_INTR_MAP
• interrupt_core0::UHCI0_INTR_MAP
• interrupt_core0::USB_INTR_MAP
• interrupt_core0::WIFI_BB_INTR_MAP
• interrupt_core0::WIFI_MAC_INTR_MAP
• interrupt_core0::WIFI_MAC_NMI_MAP
• interrupt_core0::WIFI_PWR_INTR_MAP
• interrupt_core0::ZB_MAC_INTR_MAP
• interrupt_core0::aes_intr_map::AES_INTR_MAP_R
• interrupt_core0::aes_intr_map::AES_INTR_MAP_W
• interrupt_core0::aes_intr_map::R
• interrupt_core0::aes_intr_map::W
• interrupt_core0::apb_adc_intr_map::APB_ADC_INTR_MAP_R
• interrupt_core0::apb_adc_intr_map::APB_ADC_INTR_MAP_W
• interrupt_core0::apb_adc_intr_map::R
• interrupt_core0::apb_adc_intr_map::W
• interrupt_core0::assist_debug_intr_map::ASSIST_DEBUG_INTR_MAP_R
• interrupt_core0::assist_debug_intr_map::ASSIST_DEBUG_INTR_MAP_W
• interrupt_core0::assist_debug_intr_map::R
• interrupt_core0::assist_debug_intr_map::W
• interrupt_core0::ble_sec_intr_map::BLE_SEC_INTR_MAP_R
• interrupt_core0::ble_sec_intr_map::BLE_SEC_INTR_MAP_W
• interrupt_core0::ble_sec_intr_map::R
• interrupt_core0::ble_sec_intr_map::W
• interrupt_core0::ble_timer_intr_map::BLE_TIMER_INTR_MAP_R
• interrupt_core0::ble_timer_intr_map::BLE_TIMER_INTR_MAP_W
• interrupt_core0::ble_timer_intr_map::R
• interrupt_core0::ble_timer_intr_map::W
• interrupt_core0::bt_bb_intr_map::BT_BB_INTR_MAP_R
• interrupt_core0::bt_bb_intr_map::BT_BB_INTR_MAP_W
• interrupt_core0::bt_bb_intr_map::R
• interrupt_core0::bt_bb_intr_map::W
• interrupt_core0::bt_bb_nmi_map::BT_BB_NMI_MAP_R
• interrupt_core0::bt_bb_nmi_map::BT_BB_NMI_MAP_W
• interrupt_core0::bt_bb_nmi_map::R
• interrupt_core0::bt_bb_nmi_map::W
• interrupt_core0::bt_mac_intr_map::BT_MAC_INTR_MAP_R
• interrupt_core0::bt_mac_intr_map::BT_MAC_INTR_MAP_W
• interrupt_core0::bt_mac_intr_map::R
• interrupt_core0::bt_mac_intr_map::W
• interrupt_core0::cache_intr_map::CACHE_INTR_MAP_R
• interrupt_core0::cache_intr_map::CACHE_INTR_MAP_W
• interrupt_core0::cache_intr_map::R
• interrupt_core0::cache_intr_map::W
• interrupt_core0::can0_intr_map::CAN0_INTR_MAP_R
• interrupt_core0::can0_intr_map::CAN0_INTR_MAP_W
• interrupt_core0::can0_intr_map::R
• interrupt_core0::can0_intr_map::W
• interrupt_core0::can1_intr_map::CAN1_INTR_MAP_R
• interrupt_core0::can1_intr_map::CAN1_INTR_MAP_W
• interrupt_core0::can1_intr_map::R
• interrupt_core0::can1_intr_map::W
• interrupt_core0::clock_gate::R
• interrupt_core0::clock_gate::REG_CLK_EN_R
• interrupt_core0::clock_gate::REG_CLK_EN_W
• interrupt_core0::clock_gate::W
• interrupt_core0::coex_intr_map::COEX_INTR_MAP_R
• interrupt_core0::coex_intr_map::COEX_INTR_MAP_W
• interrupt_core0::coex_intr_map::R
• interrupt_core0::coex_intr_map::W
• interrupt_core0::cpu_intr_from_cpu_0_map::CPU_INTR_FROM_CPU_0_MAP_R
• interrupt_core0::cpu_intr_from_cpu_0_map::CPU_INTR_FROM_CPU_0_MAP_W
• interrupt_core0::cpu_intr_from_cpu_0_map::R
• interrupt_core0::cpu_intr_from_cpu_0_map::W
• interrupt_core0::cpu_intr_from_cpu_1_map::CPU_INTR_FROM_CPU_1_MAP_R
• interrupt_core0::cpu_intr_from_cpu_1_map::CPU_INTR_FROM_CPU_1_MAP_W
• interrupt_core0::cpu_intr_from_cpu_1_map::R
• interrupt_core0::cpu_intr_from_cpu_1_map::W
• interrupt_core0::cpu_intr_from_cpu_2_map::CPU_INTR_FROM_CPU_2_MAP_R
• interrupt_core0::cpu_intr_from_cpu_2_map::CPU_INTR_FROM_CPU_2_MAP_W
• interrupt_core0::cpu_intr_from_cpu_2_map::R
• interrupt_core0::cpu_intr_from_cpu_2_map::W
• interrupt_core0::cpu_intr_from_cpu_3_map::CPU_INTR_FROM_CPU_3_MAP_R
• interrupt_core0::cpu_intr_from_cpu_3_map::CPU_INTR_FROM_CPU_3_MAP_W
• interrupt_core0::cpu_intr_from_cpu_3_map::R
• interrupt_core0::cpu_intr_from_cpu_3_map::W
• interrupt_core0::cpu_peri_timeout_intr_map::CPU_PERI_TIMEOUT_INTR_MAP_R
• interrupt_core0::cpu_peri_timeout_intr_map::CPU_PERI_TIMEOUT_INTR_MAP_W
• interrupt_core0::cpu_peri_timeout_intr_map::R
• interrupt_core0::cpu_peri_timeout_intr_map::W
• interrupt_core0::dma_in_ch0_intr_map::DMA_IN_CH0_INTR_MAP_R
• interrupt_core0::dma_in_ch0_intr_map::DMA_IN_CH0_INTR_MAP_W
• interrupt_core0::dma_in_ch0_intr_map::R
• interrupt_core0::dma_in_ch0_intr_map::W
• interrupt_core0::dma_in_ch1_intr_map::DMA_IN_CH1_INTR_MAP_R
• interrupt_core0::dma_in_ch1_intr_map::DMA_IN_CH1_INTR_MAP_W
• interrupt_core0::dma_in_ch1_intr_map::R
• interrupt_core0::dma_in_ch1_intr_map::W
• interrupt_core0::dma_in_ch2_intr_map::DMA_IN_CH2_INTR_MAP_R
• interrupt_core0::dma_in_ch2_intr_map::DMA_IN_CH2_INTR_MAP_W
• interrupt_core0::dma_in_ch2_intr_map::R
• interrupt_core0::dma_in_ch2_intr_map::W
• interrupt_core0::dma_out_ch0_intr_map::DMA_OUT_CH0_INTR_MAP_R
• interrupt_core0::dma_out_ch0_intr_map::DMA_OUT_CH0_INTR_MAP_W
• interrupt_core0::dma_out_ch0_intr_map::R
• interrupt_core0::dma_out_ch0_intr_map::W
• interrupt_core0::dma_out_ch1_intr_map::DMA_OUT_CH1_INTR_MAP_R
• interrupt_core0::dma_out_ch1_intr_map::DMA_OUT_CH1_INTR_MAP_W
• interrupt_core0::dma_out_ch1_intr_map::R
• interrupt_core0::dma_out_ch1_intr_map::W
• interrupt_core0::dma_out_ch2_intr_map::DMA_OUT_CH2_INTR_MAP_R
• interrupt_core0::dma_out_ch2_intr_map::DMA_OUT_CH2_INTR_MAP_W
• interrupt_core0::dma_out_ch2_intr_map::R
• interrupt_core0::dma_out_ch2_intr_map::W
• interrupt_core0::ecc_intr_map::ECC_INTR_MAP_R
• interrupt_core0::ecc_intr_map::ECC_INTR_MAP_W
• interrupt_core0::ecc_intr_map::R
• interrupt_core0::ecc_intr_map::W
• interrupt_core0::efuse_intr_map::EFUSE_INTR_MAP_R
• interrupt_core0::efuse_intr_map::EFUSE_INTR_MAP_W
• interrupt_core0::efuse_intr_map::R
• interrupt_core0::efuse_intr_map::W
• interrupt_core0::gpio_interrupt_pro_map::GPIO_INTERRUPT_PRO_MAP_R
• interrupt_core0::gpio_interrupt_pro_map::GPIO_INTERRUPT_PRO_MAP_W
• interrupt_core0::gpio_interrupt_pro_map::R
• interrupt_core0::gpio_interrupt_pro_map::W
• interrupt_core0::gpio_interrupt_pro_nmi_map::GPIO_INTERRUPT_PRO_NMI_MAP_R
• interrupt_core0::gpio_interrupt_pro_nmi_map::GPIO_INTERRUPT_PRO_NMI_MAP_W
• interrupt_core0::gpio_interrupt_pro_nmi_map::R
• interrupt_core0::gpio_interrupt_pro_nmi_map::W
• interrupt_core0::gpspi2_intr_map::GPSPI2_INTR_MAP_R
• interrupt_core0::gpspi2_intr_map::GPSPI2_INTR_MAP_W
• interrupt_core0::gpspi2_intr_map::R
• interrupt_core0::gpspi2_intr_map::W
• interrupt_core0::hp_apm_m0_intr_map::HP_APM_M0_INTR_MAP_R
• interrupt_core0::hp_apm_m0_intr_map::HP_APM_M0_INTR_MAP_W
• interrupt_core0::hp_apm_m0_intr_map::R
• interrupt_core0::hp_apm_m0_intr_map::W
• interrupt_core0::hp_apm_m1_intr_map::HP_APM_M1_INTR_MAP_R
• interrupt_core0::hp_apm_m1_intr_map::HP_APM_M1_INTR_MAP_W
• interrupt_core0::hp_apm_m1_intr_map::R
• interrupt_core0::hp_apm_m1_intr_map::W
• interrupt_core0::hp_apm_m2_intr_map::HP_APM_M2_INTR_MAP_R
• interrupt_core0::hp_apm_m2_intr_map::HP_APM_M2_INTR_MAP_W
• interrupt_core0::hp_apm_m2_intr_map::R
• interrupt_core0::hp_apm_m2_intr_map::W
• interrupt_core0::hp_apm_m3_intr_map::HP_APM_M3_INTR_MAP_R
• interrupt_core0::hp_apm_m3_intr_map::HP_APM_M3_INTR_MAP_W
• interrupt_core0::hp_apm_m3_intr_map::R
• interrupt_core0::hp_apm_m3_intr_map::W
• interrupt_core0::hp_peri_timeout_intr_map::HP_PERI_TIMEOUT_INTR_MAP_R
• interrupt_core0::hp_peri_timeout_intr_map::HP_PERI_TIMEOUT_INTR_MAP_W
• interrupt_core0::hp_peri_timeout_intr_map::R
• interrupt_core0::hp_peri_timeout_intr_map::W
• interrupt_core0::i2c_ext0_intr_map::I2C_EXT0_INTR_MAP_R
• interrupt_core0::i2c_ext0_intr_map::I2C_EXT0_INTR_MAP_W
• interrupt_core0::i2c_ext0_intr_map::R
• interrupt_core0::i2c_ext0_intr_map::W
• interrupt_core0::i2c_mst_intr_map::I2C_MST_INTR_MAP_R
• interrupt_core0::i2c_mst_intr_map::I2C_MST_INTR_MAP_W
• interrupt_core0::i2c_mst_intr_map::R
• interrupt_core0::i2c_mst_intr_map::W
• interrupt_core0::i2s1_intr_map::I2S1_INTR_MAP_R
• interrupt_core0::i2s1_intr_map::I2S1_INTR_MAP_W
• interrupt_core0::i2s1_intr_map::R
• interrupt_core0::i2s1_intr_map::W
• interrupt_core0::int_status_reg_2::INT_STATUS_2_R
• interrupt_core0::int_status_reg_2::R
• interrupt_core0::interrupt_reg_date::INTERRUPT_REG_DATE_R
• interrupt_core0::interrupt_reg_date::INTERRUPT_REG_DATE_W
• interrupt_core0::interrupt_reg_date::R
• interrupt_core0::interrupt_reg_date::W
• interrupt_core0::intr_status_reg_0::INTR_STATUS_0_R
• interrupt_core0::intr_status_reg_0::R
• interrupt_core0::intr_status_reg_1::INTR_STATUS_1_R
• interrupt_core0::intr_status_reg_1::R
• interrupt_core0::ledc_intr_map::LEDC_INTR_MAP_R
• interrupt_core0::ledc_intr_map::LEDC_INTR_MAP_W
• interrupt_core0::ledc_intr_map::R
• interrupt_core0::ledc_intr_map::W
• interrupt_core0::lp_apm0_intr_map::LP_APM0_INTR_MAP_R
• interrupt_core0::lp_apm0_intr_map::LP_APM0_INTR_MAP_W
• interrupt_core0::lp_apm0_intr_map::R
• interrupt_core0::lp_apm0_intr_map::W
• interrupt_core0::lp_apm_m0_intr_map::LP_APM_M0_INTR_MAP_R
• interrupt_core0::lp_apm_m0_intr_map::LP_APM_M0_INTR_MAP_W
• interrupt_core0::lp_apm_m0_intr_map::R
• interrupt_core0::lp_apm_m0_intr_map::W
• interrupt_core0::lp_apm_m1_intr_map::LP_APM_M1_INTR_MAP_R
• interrupt_core0::lp_apm_m1_intr_map::LP_APM_M1_INTR_MAP_W
• interrupt_core0::lp_apm_m1_intr_map::R
• interrupt_core0::lp_apm_m1_intr_map::W
• interrupt_core0::lp_i2c_intr_map::LP_I2C_INTR_MAP_R
• interrupt_core0::lp_i2c_intr_map::LP_I2C_INTR_MAP_W
• interrupt_core0::lp_i2c_intr_map::R
• interrupt_core0::lp_i2c_intr_map::W
• interrupt_core0::lp_peri_timeout_intr_map::LP_PERI_TIMEOUT_INTR_MAP_R
• interrupt_core0::lp_peri_timeout_intr_map::LP_PERI_TIMEOUT_INTR_MAP_W
• interrupt_core0::lp_peri_timeout_intr_map::R
• interrupt_core0::lp_peri_timeout_intr_map::W
• interrupt_core0::lp_rtc_timer_intr_map::LP_RTC_TIMER_INTR_MAP_R
• interrupt_core0::lp_rtc_timer_intr_map::LP_RTC_TIMER_INTR_MAP_W
• interrupt_core0::lp_rtc_timer_intr_map::R
• interrupt_core0::lp_rtc_timer_intr_map::W
• interrupt_core0::lp_timer_intr_map::LP_TIMER_INTR_MAP_R
• interrupt_core0::lp_timer_intr_map::LP_TIMER_INTR_MAP_W
• interrupt_core0::lp_timer_intr_map::R
• interrupt_core0::lp_timer_intr_map::W
• interrupt_core0::lp_uart_intr_map::LP_UART_INTR_MAP_R
• interrupt_core0::lp_uart_intr_map::LP_UART_INTR_MAP_W
• interrupt_core0::lp_uart_intr_map::R
• interrupt_core0::lp_uart_intr_map::W
• interrupt_core0::lp_wdt_intr_map::LP_WDT_INTR_MAP_R
• interrupt_core0::lp_wdt_intr_map::LP_WDT_INTR_MAP_W
• interrupt_core0::lp_wdt_intr_map::R
• interrupt_core0::lp_wdt_intr_map::W
• interrupt_core0::modem_peri_timeout_intr_map::MODEM_PERI_TIMEOUT_INTR_MAP_R
• interrupt_core0::modem_peri_timeout_intr_map::MODEM_PERI_TIMEOUT_INTR_MAP_W
• interrupt_core0::modem_peri_timeout_intr_map::R
• interrupt_core0::modem_peri_timeout_intr_map::W
• interrupt_core0::mspi_intr_map::MSPI_INTR_MAP_R
• interrupt_core0::mspi_intr_map::MSPI_INTR_MAP_W
• interrupt_core0::mspi_intr_map::R
• interrupt_core0::mspi_intr_map::W
• interrupt_core0::parl_io_intr_map::PARL_IO_INTR_MAP_R
• interrupt_core0::parl_io_intr_map::PARL_IO_INTR_MAP_W
• interrupt_core0::parl_io_intr_map::R
• interrupt_core0::parl_io_intr_map::W
• interrupt_core0::pau_intr_map::PAU_INTR_MAP_R
• interrupt_core0::pau_intr_map::PAU_INTR_MAP_W
• interrupt_core0::pau_intr_map::R
• interrupt_core0::pau_intr_map::W
• interrupt_core0::pcnt_intr_map::PCNT_INTR_MAP_R
• interrupt_core0::pcnt_intr_map::PCNT_INTR_MAP_W
• interrupt_core0::pcnt_intr_map::R
• interrupt_core0::pcnt_intr_map::W
• interrupt_core0::pmu_intr_map::PMU_INTR_MAP_R
• interrupt_core0::pmu_intr_map::PMU_INTR_MAP_W
• interrupt_core0::pmu_intr_map::R
• interrupt_core0::pmu_intr_map::W
• interrupt_core0::pwm_intr_map::PWM_INTR_MAP_R
• interrupt_core0::pwm_intr_map::PWM_INTR_MAP_W
• interrupt_core0::pwm_intr_map::R
• interrupt_core0::pwm_intr_map::W
• interrupt_core0::rmt_intr_map::R
• interrupt_core0::rmt_intr_map::RMT_INTR_MAP_R
• interrupt_core0::rmt_intr_map::RMT_INTR_MAP_W
• interrupt_core0::rmt_intr_map::W
• interrupt_core0::rsa_intr_map::R
• interrupt_core0::rsa_intr_map::RSA_INTR_MAP_R
• interrupt_core0::rsa_intr_map::RSA_INTR_MAP_W
• interrupt_core0::rsa_intr_map::W
• interrupt_core0::sha_intr_map::R
• interrupt_core0::sha_intr_map::SHA_INTR_MAP_R
• interrupt_core0::sha_intr_map::SHA_INTR_MAP_W
• interrupt_core0::sha_intr_map::W
• interrupt_core0::slc0_intr_map::R
• interrupt_core0::slc0_intr_map::SLC0_INTR_MAP_R
• interrupt_core0::slc0_intr_map::SLC0_INTR_MAP_W
• interrupt_core0::slc0_intr_map::W
• interrupt_core0::slc1_intr_map::R
• interrupt_core0::slc1_intr_map::SLC1_INTR_MAP_R
• interrupt_core0::slc1_intr_map::SLC1_INTR_MAP_W
• interrupt_core0::slc1_intr_map::W
• interrupt_core0::systimer_target0_intr_map::R
• interrupt_core0::systimer_target0_intr_map::SYSTIMER_TARGET0_INTR_MAP_R
• interrupt_core0::systimer_target0_intr_map::SYSTIMER_TARGET0_INTR_MAP_W
• interrupt_core0::systimer_target0_intr_map::W
• interrupt_core0::systimer_target1_intr_map::R
• interrupt_core0::systimer_target1_intr_map::SYSTIMER_TARGET1_INTR_MAP_R
• interrupt_core0::systimer_target1_intr_map::SYSTIMER_TARGET1_INTR_MAP_W
• interrupt_core0::systimer_target1_intr_map::W
• interrupt_core0::systimer_target2_intr_map::R
• interrupt_core0::systimer_target2_intr_map::SYSTIMER_TARGET2_INTR_MAP_R
• interrupt_core0::systimer_target2_intr_map::SYSTIMER_TARGET2_INTR_MAP_W
• interrupt_core0::systimer_target2_intr_map::W
• interrupt_core0::tg0_t0_intr_map::R
• interrupt_core0::tg0_t0_intr_map::TG0_T0_INTR_MAP_R
• interrupt_core0::tg0_t0_intr_map::TG0_T0_INTR_MAP_W
• interrupt_core0::tg0_t0_intr_map::W
• interrupt_core0::tg0_t1_intr_map::R
• interrupt_core0::tg0_t1_intr_map::TG0_T1_INTR_MAP_R
• interrupt_core0::tg0_t1_intr_map::TG0_T1_INTR_MAP_W
• interrupt_core0::tg0_t1_intr_map::W
• interrupt_core0::tg0_wdt_intr_map::R
• interrupt_core0::tg0_wdt_intr_map::TG0_WDT_INTR_MAP_R
• interrupt_core0::tg0_wdt_intr_map::TG0_WDT_INTR_MAP_W
• interrupt_core0::tg0_wdt_intr_map::W
• interrupt_core0::tg1_t0_intr_map::R
• interrupt_core0::tg1_t0_intr_map::TG1_T0_INTR_MAP_R
• interrupt_core0::tg1_t0_intr_map::TG1_T0_INTR_MAP_W
• interrupt_core0::tg1_t0_intr_map::W
• interrupt_core0::tg1_t1_intr_map::R
• interrupt_core0::tg1_t1_intr_map::TG1_T1_INTR_MAP_R
• interrupt_core0::tg1_t1_intr_map::TG1_T1_INTR_MAP_W
• interrupt_core0::tg1_t1_intr_map::W
• interrupt_core0::tg1_wdt_intr_map::R
• interrupt_core0::tg1_wdt_intr_map::TG1_WDT_INTR_MAP_R
• interrupt_core0::tg1_wdt_intr_map::TG1_WDT_INTR_MAP_W
• interrupt_core0::tg1_wdt_intr_map::W
• interrupt_core0::trace_intr_map::R
• interrupt_core0::trace_intr_map::TRACE_INTR_MAP_R
• interrupt_core0::trace_intr_map::TRACE_INTR_MAP_W
• interrupt_core0::trace_intr_map::W
• interrupt_core0::uart0_intr_map::R
• interrupt_core0::uart0_intr_map::UART0_INTR_MAP_R
• interrupt_core0::uart0_intr_map::UART0_INTR_MAP_W
• interrupt_core0::uart0_intr_map::W
• interrupt_core0::uart1_intr_map::R
• interrupt_core0::uart1_intr_map::UART1_INTR_MAP_R
• interrupt_core0::uart1_intr_map::UART1_INTR_MAP_W
• interrupt_core0::uart1_intr_map::W
• interrupt_core0::uhci0_intr_map::R
• interrupt_core0::uhci0_intr_map::UHCI0_INTR_MAP_R
• interrupt_core0::uhci0_intr_map::UHCI0_INTR_MAP_W
• interrupt_core0::uhci0_intr_map::W
• interrupt_core0::usb_intr_map::R
• interrupt_core0::usb_intr_map::USB_INTR_MAP_R
• interrupt_core0::usb_intr_map::USB_INTR_MAP_W
• interrupt_core0::usb_intr_map::W
• interrupt_core0::wifi_bb_intr_map::R
• interrupt_core0::wifi_bb_intr_map::W
• interrupt_core0::wifi_bb_intr_map::WIFI_BB_INTR_MAP_R
• interrupt_core0::wifi_bb_intr_map::WIFI_BB_INTR_MAP_W
• interrupt_core0::wifi_mac_intr_map::R
• interrupt_core0::wifi_mac_intr_map::W
• interrupt_core0::wifi_mac_intr_map::WIFI_MAC_INTR_MAP_R
• interrupt_core0::wifi_mac_intr_map::WIFI_MAC_INTR_MAP_W
• interrupt_core0::wifi_mac_nmi_map::R
• interrupt_core0::wifi_mac_nmi_map::W
• interrupt_core0::wifi_mac_nmi_map::WIFI_MAC_NMI_MAP_R
• interrupt_core0::wifi_mac_nmi_map::WIFI_MAC_NMI_MAP_W
• interrupt_core0::wifi_pwr_intr_map::R
• interrupt_core0::wifi_pwr_intr_map::W
• interrupt_core0::wifi_pwr_intr_map::WIFI_PWR_INTR_MAP_R
• interrupt_core0::wifi_pwr_intr_map::WIFI_PWR_INTR_MAP_W
• interrupt_core0::zb_mac_intr_map::R
• interrupt_core0::zb_mac_intr_map::W
• interrupt_core0::zb_mac_intr_map::ZB_MAC_INTR_MAP_R
• interrupt_core0::zb_mac_intr_map::ZB_MAC_INTR_MAP_W
• intpri::CLOCK_GATE
• intpri::CPU_INTR_FROM_CPU_0
• intpri::CPU_INTR_FROM_CPU_1
• intpri::CPU_INTR_FROM_CPU_2
• intpri::CPU_INTR_FROM_CPU_3
• intpri::CPU_INT_CLEAR
• intpri::CPU_INT_EIP_STATUS
• intpri::CPU_INT_ENABLE
• intpri::CPU_INT_PRI
• intpri::CPU_INT_THRESH
• intpri::CPU_INT_TYPE
• intpri::DATE
• intpri::RND_ECO
• intpri::RND_ECO_HIGH
• intpri::RND_ECO_LOW
• intpri::clock_gate::CLK_EN_R
• intpri::clock_gate::CLK_EN_W
• intpri::clock_gate::R
• intpri::clock_gate::W
• intpri::cpu_int_clear::CPU_INT_CLEAR_R
• intpri::cpu_int_clear::CPU_INT_CLEAR_W
• intpri::cpu_int_clear::R
• intpri::cpu_int_clear::W
• intpri::cpu_int_eip_status::CPU_INT_EIP_STATUS_R
• intpri::cpu_int_eip_status::R
• intpri::cpu_int_enable::CPU_INT_ENABLE_R
• intpri::cpu_int_enable::CPU_INT_ENABLE_W
• intpri::cpu_int_enable::R
• intpri::cpu_int_enable::W
• intpri::cpu_int_pri::MAP_R
• intpri::cpu_int_pri::MAP_W
• intpri::cpu_int_pri::R
• intpri::cpu_int_pri::W
• intpri::cpu_int_thresh::CPU_INT_THRESH_R
• intpri::cpu_int_thresh::CPU_INT_THRESH_W
• intpri::cpu_int_thresh::R
• intpri::cpu_int_thresh::W
• intpri::cpu_int_type::CPU_INT_TYPE_R
• intpri::cpu_int_type::CPU_INT_TYPE_W
• intpri::cpu_int_type::R
• intpri::cpu_int_type::W
• intpri::cpu_intr_from_cpu_0::CPU_INTR_FROM_CPU_0_R
• intpri::cpu_intr_from_cpu_0::CPU_INTR_FROM_CPU_0_W
• intpri::cpu_intr_from_cpu_0::R
• intpri::cpu_intr_from_cpu_0::W
• intpri::cpu_intr_from_cpu_1::CPU_INTR_FROM_CPU_1_R
• intpri::cpu_intr_from_cpu_1::CPU_INTR_FROM_CPU_1_W
• intpri::cpu_intr_from_cpu_1::R
• intpri::cpu_intr_from_cpu_1::W
• intpri::cpu_intr_from_cpu_2::CPU_INTR_FROM_CPU_2_R
• intpri::cpu_intr_from_cpu_2::CPU_INTR_FROM_CPU_2_W
• intpri::cpu_intr_from_cpu_2::R
• intpri::cpu_intr_from_cpu_2::W
• intpri::cpu_intr_from_cpu_3::CPU_INTR_FROM_CPU_3_R
• intpri::cpu_intr_from_cpu_3::CPU_INTR_FROM_CPU_3_W
• intpri::cpu_intr_from_cpu_3::R
• intpri::cpu_intr_from_cpu_3::W
• intpri::date::DATE_R
• intpri::date::DATE_W
• intpri::date::R
• intpri::date::W
• intpri::rnd_eco::R
• intpri::rnd_eco::REDCY_ENA_R
• intpri::rnd_eco::REDCY_ENA_W
• intpri::rnd_eco::REDCY_RESULT_R
• intpri::rnd_eco::W
• intpri::rnd_eco_high::R
• intpri::rnd_eco_high::REDCY_HIGH_R
• intpri::rnd_eco_high::REDCY_HIGH_W
• intpri::rnd_eco_high::W
• intpri::rnd_eco_low::R
• intpri::rnd_eco_low::REDCY_LOW_R
• intpri::rnd_eco_low::REDCY_LOW_W
• intpri::rnd_eco_low::W
• io_mux::DATE
• io_mux::GPIO
• io_mux::MODEM_DIAG_EN
• io_mux::PIN_CTRL
• io_mux::date::R
• io_mux::date::REG_DATE_R
• io_mux::date::REG_DATE_W
• io_mux::date::W
• io_mux::gpio::FILTER_EN_R
• io_mux::gpio::FILTER_EN_W
• io_mux::gpio::FUN_DRV_R
• io_mux::gpio::FUN_DRV_W
• io_mux::gpio::FUN_IE_R
• io_mux::gpio::FUN_IE_W
• io_mux::gpio::FUN_WPD_R
• io_mux::gpio::FUN_WPD_W
• io_mux::gpio::FUN_WPU_R
• io_mux::gpio::FUN_WPU_W
• io_mux::gpio::MCU_DRV_R
• io_mux::gpio::MCU_DRV_W
• io_mux::gpio::MCU_IE_R
• io_mux::gpio::MCU_IE_W
• io_mux::gpio::MCU_OE_R
• io_mux::gpio::MCU_OE_W
• io_mux::gpio::MCU_SEL_R
• io_mux::gpio::MCU_SEL_W
• io_mux::gpio::MCU_WPD_R
• io_mux::gpio::MCU_WPD_W
• io_mux::gpio::MCU_WPU_R
• io_mux::gpio::MCU_WPU_W
• io_mux::gpio::R
• io_mux::gpio::SLP_SEL_R
• io_mux::gpio::SLP_SEL_W
• io_mux::gpio::W
• io_mux::modem_diag_en::MODEM_DIAG_EN_R
• io_mux::modem_diag_en::MODEM_DIAG_EN_W
• io_mux::modem_diag_en::R
• io_mux::modem_diag_en::W
• io_mux::pin_ctrl::CLK_OUT1_R
• io_mux::pin_ctrl::CLK_OUT1_W
• io_mux::pin_ctrl::CLK_OUT2_R
• io_mux::pin_ctrl::CLK_OUT2_W
• io_mux::pin_ctrl::CLK_OUT3_R
• io_mux::pin_ctrl::CLK_OUT3_W
• io_mux::pin_ctrl::R
• io_mux::pin_ctrl::W
• ledc::CH_GAMMA_CONF
• ledc::CH_GAMMA_RD_ADDR
• ledc::CH_GAMMA_RD_DATA
• ledc::CH_GAMMA_WR
• ledc::CH_GAMMA_WR_ADDR
• ledc::CONF
• ledc::DATE
• ledc::EVT_TASK_EN0
• ledc::EVT_TASK_EN1
• ledc::EVT_TASK_EN2
• ledc::INT_CLR
• ledc::INT_ENA
• ledc::INT_RAW
• ledc::INT_ST
• ledc::TIMER_CMP
• ledc::TIMER_CNT_CAP
• ledc::ch::CONF0
• ledc::ch::CONF1
• ledc::ch::DUTY
• ledc::ch::DUTY_R
• ledc::ch::HPOINT
• ledc::ch::conf0::IDLE_LV_R
• ledc::ch::conf0::IDLE_LV_W
• ledc::ch::conf0::OVF_CNT_EN_R
• ledc::ch::conf0::OVF_CNT_EN_W
• ledc::ch::conf0::OVF_CNT_RESET_W
• ledc::ch::conf0::OVF_NUM_R
• ledc::ch::conf0::OVF_NUM_W
• ledc::ch::conf0::PARA_UP_W
• ledc::ch::conf0::R
• ledc::ch::conf0::SIG_OUT_EN_R
• ledc::ch::conf0::SIG_OUT_EN_W
• ledc::ch::conf0::TIMER_SEL_R
• ledc::ch::conf0::TIMER_SEL_W
• ledc::ch::conf0::W
• ledc::ch::conf1::DUTY_START_R
• ledc::ch::conf1::DUTY_START_W
• ledc::ch::conf1::R
• ledc::ch::conf1::W
• ledc::ch::duty::DUTY_R
• ledc::ch::duty::DUTY_W
• ledc::ch::duty::R
• ledc::ch::duty::W
• ledc::ch::duty_r::DUTY_R_R
• ledc::ch::duty_r::R
• ledc::ch::hpoint::HPOINT_R
• ledc::ch::hpoint::HPOINT_W
• ledc::ch::hpoint::R
• ledc::ch::hpoint::W
• ledc::ch_gamma_conf::CH_GAMMA_ENTRY_NUM_R
• ledc::ch_gamma_conf::CH_GAMMA_ENTRY_NUM_W
• ledc::ch_gamma_conf::CH_GAMMA_PAUSE_W
• ledc::ch_gamma_conf::CH_GAMMA_RESUME_W
• ledc::ch_gamma_conf::R
• ledc::ch_gamma_conf::W
• ledc::ch_gamma_rd_addr::CH_GAMMA_RD_ADDR_R
• ledc::ch_gamma_rd_addr::CH_GAMMA_RD_ADDR_W
• ledc::ch_gamma_rd_addr::R
• ledc::ch_gamma_rd_addr::W
• ledc::ch_gamma_rd_data::CH_GAMMA_RD_DATA_R
• ledc::ch_gamma_rd_data::R
• ledc::ch_gamma_wr::CH_GAMMA_DUTY_CYCLE_R
• ledc::ch_gamma_wr::CH_GAMMA_DUTY_CYCLE_W
• ledc::ch_gamma_wr::CH_GAMMA_DUTY_INC_R
• ledc::ch_gamma_wr::CH_GAMMA_DUTY_INC_W
• ledc::ch_gamma_wr::CH_GAMMA_DUTY_NUM_R
• ledc::ch_gamma_wr::CH_GAMMA_DUTY_NUM_W
• ledc::ch_gamma_wr::CH_GAMMA_SCALE_R
• ledc::ch_gamma_wr::CH_GAMMA_SCALE_W
• ledc::ch_gamma_wr::R
• ledc::ch_gamma_wr::W
• ledc::ch_gamma_wr_addr::CH_GAMMA_WR_ADDR_R
• ledc::ch_gamma_wr_addr::CH_GAMMA_WR_ADDR_W
• ledc::ch_gamma_wr_addr::R
• ledc::ch_gamma_wr_addr::W
• ledc::conf::APB_CLK_SEL_R
• ledc::conf::APB_CLK_SEL_W
• ledc::conf::CLK_EN_R
• ledc::conf::CLK_EN_W
• ledc::conf::GAMMA_RAM_CLK_EN_CH0_R
• ledc::conf::GAMMA_RAM_CLK_EN_CH0_W
• ledc::conf::GAMMA_RAM_CLK_EN_CH1_R
• ledc::conf::GAMMA_RAM_CLK_EN_CH1_W
• ledc::conf::GAMMA_RAM_CLK_EN_CH2_R
• ledc::conf::GAMMA_RAM_CLK_EN_CH2_W
• ledc::conf::GAMMA_RAM_CLK_EN_CH3_R
• ledc::conf::GAMMA_RAM_CLK_EN_CH3_W
• ledc::conf::GAMMA_RAM_CLK_EN_CH4_R
• ledc::conf::GAMMA_RAM_CLK_EN_CH4_W
• ledc::conf::GAMMA_RAM_CLK_EN_CH5_R
• ledc::conf::GAMMA_RAM_CLK_EN_CH5_W
• ledc::conf::R
• ledc::conf::W
• ledc::date::LEDC_DATE_R
• ledc::date::LEDC_DATE_W
• ledc::date::R
• ledc::date::W
• ledc::evt_task_en0::EVT_DUTY_CHNG_END_CH0_EN_R
• ledc::evt_task_en0::EVT_DUTY_CHNG_END_CH0_EN_W
• ledc::evt_task_en0::EVT_DUTY_CHNG_END_CH1_EN_R
• ledc::evt_task_en0::EVT_DUTY_CHNG_END_CH1_EN_W
• ledc::evt_task_en0::EVT_DUTY_CHNG_END_CH2_EN_R
• ledc::evt_task_en0::EVT_DUTY_CHNG_END_CH2_EN_W
• ledc::evt_task_en0::EVT_DUTY_CHNG_END_CH3_EN_R
• ledc::evt_task_en0::EVT_DUTY_CHNG_END_CH3_EN_W
• ledc::evt_task_en0::EVT_DUTY_CHNG_END_CH4_EN_R
• ledc::evt_task_en0::EVT_DUTY_CHNG_END_CH4_EN_W
• ledc::evt_task_en0::EVT_DUTY_CHNG_END_CH5_EN_R
• ledc::evt_task_en0::EVT_DUTY_CHNG_END_CH5_EN_W
• ledc::evt_task_en0::EVT_OVF_CNT_PLS_CH0_EN_R
• ledc::evt_task_en0::EVT_OVF_CNT_PLS_CH0_EN_W
• ledc::evt_task_en0::EVT_OVF_CNT_PLS_CH1_EN_R
• ledc::evt_task_en0::EVT_OVF_CNT_PLS_CH1_EN_W
• ledc::evt_task_en0::EVT_OVF_CNT_PLS_CH2_EN_R
• ledc::evt_task_en0::EVT_OVF_CNT_PLS_CH2_EN_W
• ledc::evt_task_en0::EVT_OVF_CNT_PLS_CH3_EN_R
• ledc::evt_task_en0::EVT_OVF_CNT_PLS_CH3_EN_W
• ledc::evt_task_en0::EVT_OVF_CNT_PLS_CH4_EN_R
• ledc::evt_task_en0::EVT_OVF_CNT_PLS_CH4_EN_W
• ledc::evt_task_en0::EVT_OVF_CNT_PLS_CH5_EN_R
• ledc::evt_task_en0::EVT_OVF_CNT_PLS_CH5_EN_W
• ledc::evt_task_en0::EVT_TIME0_CMP_EN_R
• ledc::evt_task_en0::EVT_TIME0_CMP_EN_W
• ledc::evt_task_en0::EVT_TIME1_CMP_EN_R
• ledc::evt_task_en0::EVT_TIME1_CMP_EN_W
• ledc::evt_task_en0::EVT_TIME2_CMP_EN_R
• ledc::evt_task_en0::EVT_TIME2_CMP_EN_W
• ledc::evt_task_en0::EVT_TIME3_CMP_EN_R
• ledc::evt_task_en0::EVT_TIME3_CMP_EN_W
• ledc::evt_task_en0::EVT_TIME_OVF_TIMER0_EN_R
• ledc::evt_task_en0::EVT_TIME_OVF_TIMER0_EN_W
• ledc::evt_task_en0::EVT_TIME_OVF_TIMER1_EN_R
• ledc::evt_task_en0::EVT_TIME_OVF_TIMER1_EN_W
• ledc::evt_task_en0::EVT_TIME_OVF_TIMER2_EN_R
• ledc::evt_task_en0::EVT_TIME_OVF_TIMER2_EN_W
• ledc::evt_task_en0::EVT_TIME_OVF_TIMER3_EN_R
• ledc::evt_task_en0::EVT_TIME_OVF_TIMER3_EN_W
• ledc::evt_task_en0::R
• ledc::evt_task_en0::TASK_DUTY_SCALE_UPDATE_CH0_EN_R
• ledc::evt_task_en0::TASK_DUTY_SCALE_UPDATE_CH0_EN_W
• ledc::evt_task_en0::TASK_DUTY_SCALE_UPDATE_CH1_EN_R
• ledc::evt_task_en0::TASK_DUTY_SCALE_UPDATE_CH1_EN_W
• ledc::evt_task_en0::TASK_DUTY_SCALE_UPDATE_CH2_EN_R
• ledc::evt_task_en0::TASK_DUTY_SCALE_UPDATE_CH2_EN_W
• ledc::evt_task_en0::TASK_DUTY_SCALE_UPDATE_CH3_EN_R
• ledc::evt_task_en0::TASK_DUTY_SCALE_UPDATE_CH3_EN_W
• ledc::evt_task_en0::TASK_DUTY_SCALE_UPDATE_CH4_EN_R
• ledc::evt_task_en0::TASK_DUTY_SCALE_UPDATE_CH4_EN_W
• ledc::evt_task_en0::TASK_DUTY_SCALE_UPDATE_CH5_EN_R
• ledc::evt_task_en0::TASK_DUTY_SCALE_UPDATE_CH5_EN_W
• ledc::evt_task_en0::W
• ledc::evt_task_en1::R
• ledc::evt_task_en1::TASK_OVF_CNT_RST_CH0_EN_R
• ledc::evt_task_en1::TASK_OVF_CNT_RST_CH0_EN_W
• ledc::evt_task_en1::TASK_OVF_CNT_RST_CH1_EN_R
• ledc::evt_task_en1::TASK_OVF_CNT_RST_CH1_EN_W
• ledc::evt_task_en1::TASK_OVF_CNT_RST_CH2_EN_R
• ledc::evt_task_en1::TASK_OVF_CNT_RST_CH2_EN_W
• ledc::evt_task_en1::TASK_OVF_CNT_RST_CH3_EN_R
• ledc::evt_task_en1::TASK_OVF_CNT_RST_CH3_EN_W
• ledc::evt_task_en1::TASK_OVF_CNT_RST_CH4_EN_R
• ledc::evt_task_en1::TASK_OVF_CNT_RST_CH4_EN_W
• ledc::evt_task_en1::TASK_OVF_CNT_RST_CH5_EN_R
• ledc::evt_task_en1::TASK_OVF_CNT_RST_CH5_EN_W
• ledc::evt_task_en1::TASK_SIG_OUT_DIS_CH0_EN_R
• ledc::evt_task_en1::TASK_SIG_OUT_DIS_CH0_EN_W
• ledc::evt_task_en1::TASK_SIG_OUT_DIS_CH1_EN_R
• ledc::evt_task_en1::TASK_SIG_OUT_DIS_CH1_EN_W
• ledc::evt_task_en1::TASK_SIG_OUT_DIS_CH2_EN_R
• ledc::evt_task_en1::TASK_SIG_OUT_DIS_CH2_EN_W
• ledc::evt_task_en1::TASK_SIG_OUT_DIS_CH3_EN_R
• ledc::evt_task_en1::TASK_SIG_OUT_DIS_CH3_EN_W
• ledc::evt_task_en1::TASK_SIG_OUT_DIS_CH4_EN_R
• ledc::evt_task_en1::TASK_SIG_OUT_DIS_CH4_EN_W
• ledc::evt_task_en1::TASK_SIG_OUT_DIS_CH5_EN_R
• ledc::evt_task_en1::TASK_SIG_OUT_DIS_CH5_EN_W
• ledc::evt_task_en1::TASK_TIMER0_CAP_EN_R
• ledc::evt_task_en1::TASK_TIMER0_CAP_EN_W
• ledc::evt_task_en1::TASK_TIMER0_PAUSE_RESUME_EN_R
• ledc::evt_task_en1::TASK_TIMER0_PAUSE_RESUME_EN_W
• ledc::evt_task_en1::TASK_TIMER0_RES_UPDATE_EN_R
• ledc::evt_task_en1::TASK_TIMER0_RES_UPDATE_EN_W
• ledc::evt_task_en1::TASK_TIMER0_RST_EN_R
• ledc::evt_task_en1::TASK_TIMER0_RST_EN_W
• ledc::evt_task_en1::TASK_TIMER1_CAP_EN_R
• ledc::evt_task_en1::TASK_TIMER1_CAP_EN_W
• ledc::evt_task_en1::TASK_TIMER1_PAUSE_RESUME_EN_R
• ledc::evt_task_en1::TASK_TIMER1_PAUSE_RESUME_EN_W
• ledc::evt_task_en1::TASK_TIMER1_RES_UPDATE_EN_R
• ledc::evt_task_en1::TASK_TIMER1_RES_UPDATE_EN_W
• ledc::evt_task_en1::TASK_TIMER1_RST_EN_R
• ledc::evt_task_en1::TASK_TIMER1_RST_EN_W
• ledc::evt_task_en1::TASK_TIMER2_CAP_EN_R
• ledc::evt_task_en1::TASK_TIMER2_CAP_EN_W
• ledc::evt_task_en1::TASK_TIMER2_PAUSE_RESUME_EN_R
• ledc::evt_task_en1::TASK_TIMER2_PAUSE_RESUME_EN_W
• ledc::evt_task_en1::TASK_TIMER2_RES_UPDATE_EN_R
• ledc::evt_task_en1::TASK_TIMER2_RES_UPDATE_EN_W
• ledc::evt_task_en1::TASK_TIMER2_RST_EN_R
• ledc::evt_task_en1::TASK_TIMER2_RST_EN_W
• ledc::evt_task_en1::TASK_TIMER3_CAP_EN_R
• ledc::evt_task_en1::TASK_TIMER3_CAP_EN_W
• ledc::evt_task_en1::TASK_TIMER3_PAUSE_RESUME_EN_R
• ledc::evt_task_en1::TASK_TIMER3_PAUSE_RESUME_EN_W
• ledc::evt_task_en1::TASK_TIMER3_RES_UPDATE_EN_R
• ledc::evt_task_en1::TASK_TIMER3_RES_UPDATE_EN_W
• ledc::evt_task_en1::TASK_TIMER3_RST_EN_R
• ledc::evt_task_en1::TASK_TIMER3_RST_EN_W
• ledc::evt_task_en1::W
• ledc::evt_task_en2::R
• ledc::evt_task_en2::TASK_GAMMA_PAUSE_CH0_EN_R
• ledc::evt_task_en2::TASK_GAMMA_PAUSE_CH0_EN_W
• ledc::evt_task_en2::TASK_GAMMA_PAUSE_CH1_EN_R
• ledc::evt_task_en2::TASK_GAMMA_PAUSE_CH1_EN_W
• ledc::evt_task_en2::TASK_GAMMA_PAUSE_CH2_EN_R
• ledc::evt_task_en2::TASK_GAMMA_PAUSE_CH2_EN_W
• ledc::evt_task_en2::TASK_GAMMA_PAUSE_CH3_EN_R
• ledc::evt_task_en2::TASK_GAMMA_PAUSE_CH3_EN_W
• ledc::evt_task_en2::TASK_GAMMA_PAUSE_CH4_EN_R
• ledc::evt_task_en2::TASK_GAMMA_PAUSE_CH4_EN_W
• ledc::evt_task_en2::TASK_GAMMA_PAUSE_CH5_EN_R
• ledc::evt_task_en2::TASK_GAMMA_PAUSE_CH5_EN_W
• ledc::evt_task_en2::TASK_GAMMA_RESTART_CH0_EN_R
• ledc::evt_task_en2::TASK_GAMMA_RESTART_CH0_EN_W
• ledc::evt_task_en2::TASK_GAMMA_RESTART_CH1_EN_R
• ledc::evt_task_en2::TASK_GAMMA_RESTART_CH1_EN_W
• ledc::evt_task_en2::TASK_GAMMA_RESTART_CH2_EN_R
• ledc::evt_task_en2::TASK_GAMMA_RESTART_CH2_EN_W
• ledc::evt_task_en2::TASK_GAMMA_RESTART_CH3_EN_R
• ledc::evt_task_en2::TASK_GAMMA_RESTART_CH3_EN_W
• ledc::evt_task_en2::TASK_GAMMA_RESTART_CH4_EN_R
• ledc::evt_task_en2::TASK_GAMMA_RESTART_CH4_EN_W
• ledc::evt_task_en2::TASK_GAMMA_RESTART_CH5_EN_R
• ledc::evt_task_en2::TASK_GAMMA_RESTART_CH5_EN_W
• ledc::evt_task_en2::TASK_GAMMA_RESUME_CH0_EN_R
• ledc::evt_task_en2::TASK_GAMMA_RESUME_CH0_EN_W
• ledc::evt_task_en2::TASK_GAMMA_RESUME_CH1_EN_R
• ledc::evt_task_en2::TASK_GAMMA_RESUME_CH1_EN_W
• ledc::evt_task_en2::TASK_GAMMA_RESUME_CH2_EN_R
• ledc::evt_task_en2::TASK_GAMMA_RESUME_CH2_EN_W
• ledc::evt_task_en2::TASK_GAMMA_RESUME_CH3_EN_R
• ledc::evt_task_en2::TASK_GAMMA_RESUME_CH3_EN_W
• ledc::evt_task_en2::TASK_GAMMA_RESUME_CH4_EN_R
• ledc::evt_task_en2::TASK_GAMMA_RESUME_CH4_EN_W
• ledc::evt_task_en2::TASK_GAMMA_RESUME_CH5_EN_R
• ledc::evt_task_en2::TASK_GAMMA_RESUME_CH5_EN_W
• ledc::evt_task_en2::W
• ledc::int_clr::DUTY_CHNG_END_CH_W
• ledc::int_clr::OVF_CNT_CH_W
• ledc::int_clr::TIMER_OVF_W
• ledc::int_clr::W
• ledc::int_ena::DUTY_CHNG_END_CH_R
• ledc::int_ena::DUTY_CHNG_END_CH_W
• ledc::int_ena::OVF_CNT_CH_R
• ledc::int_ena::OVF_CNT_CH_W
• ledc::int_ena::R
• ledc::int_ena::TIMER_OVF_R
• ledc::int_ena::TIMER_OVF_W
• ledc::int_ena::W
• ledc::int_raw::DUTY_CHNG_END_CH_R
• ledc::int_raw::DUTY_CHNG_END_CH_W
• ledc::int_raw::OVF_CNT_CH_R
• ledc::int_raw::OVF_CNT_CH_W
• ledc::int_raw::R
• ledc::int_raw::TIMER_OVF_R
• ledc::int_raw::TIMER_OVF_W
• ledc::int_raw::W
• ledc::int_st::DUTY_CHNG_END_CH_R
• ledc::int_st::OVF_CNT_CH_R
• ledc::int_st::R
• ledc::int_st::TIMER_OVF_R
• ledc::timer::CONF
• ledc::timer::VALUE
• ledc::timer::conf::CLK_DIV_R
• ledc::timer::conf::CLK_DIV_W
• ledc::timer::conf::DUTY_RES_R
• ledc::timer::conf::DUTY_RES_W
• ledc::timer::conf::PARA_UP_W
• ledc::timer::conf::PAUSE_R
• ledc::timer::conf::PAUSE_W
• ledc::timer::conf::R
• ledc::timer::conf::RST_R
• ledc::timer::conf::RST_W
• ledc::timer::conf::TICK_SEL_R
• ledc::timer::conf::TICK_SEL_W
• ledc::timer::conf::W
• ledc::timer::value::CNT_R
• ledc::timer::value::R
• ledc::timer_cmp::R
• ledc::timer_cmp::TIMER_CMP_R
• ledc::timer_cmp::TIMER_CMP_W
• ledc::timer_cmp::W
• ledc::timer_cnt_cap::R
• ledc::timer_cnt_cap::TIMER_CNT_CAP_R
• lp_ana::BOD_MODE0_CNTL
• lp_ana::BOD_MODE1_CNTL
• lp_ana::CK_GLITCH_CNTL
• lp_ana::DATE
• lp_ana::FIB_ENABLE
• lp_ana::INT_CLR
• lp_ana::INT_ENA
• lp_ana::INT_RAW
• lp_ana::INT_ST
• lp_ana::LP_INT_CLR
• lp_ana::LP_INT_ENA
• lp_ana::LP_INT_RAW
• lp_ana::LP_INT_ST
• lp_ana::bod_mode0_cntl::BOD_MODE0_CLOSE_FLASH_ENA_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_CLOSE_FLASH_ENA_W
• lp_ana::bod_mode0_cntl::BOD_MODE0_CNT_CLR_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_CNT_CLR_W
• lp_ana::bod_mode0_cntl::BOD_MODE0_INTR_ENA_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_INTR_ENA_W
• lp_ana::bod_mode0_cntl::BOD_MODE0_INTR_WAIT_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_INTR_WAIT_W
• lp_ana::bod_mode0_cntl::BOD_MODE0_PD_RF_ENA_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_PD_RF_ENA_W
• lp_ana::bod_mode0_cntl::BOD_MODE0_RESET_ENA_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_RESET_ENA_W
• lp_ana::bod_mode0_cntl::BOD_MODE0_RESET_SEL_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_RESET_SEL_W
• lp_ana::bod_mode0_cntl::BOD_MODE0_RESET_WAIT_R
• lp_ana::bod_mode0_cntl::BOD_MODE0_RESET_WAIT_W
• lp_ana::bod_mode0_cntl::R
• lp_ana::bod_mode0_cntl::W
• lp_ana::bod_mode1_cntl::BOD_MODE1_RESET_ENA_R
• lp_ana::bod_mode1_cntl::BOD_MODE1_RESET_ENA_W
• lp_ana::bod_mode1_cntl::R
• lp_ana::bod_mode1_cntl::W
• lp_ana::ck_glitch_cntl::CK_GLITCH_RESET_ENA_R
• lp_ana::ck_glitch_cntl::CK_GLITCH_RESET_ENA_W
• lp_ana::ck_glitch_cntl::R
• lp_ana::ck_glitch_cntl::W
• lp_ana::date::CLK_EN_R
• lp_ana::date::CLK_EN_W
• lp_ana::date::LP_ANA_DATE_R
• lp_ana::date::LP_ANA_DATE_W
• lp_ana::date::R
• lp_ana::date::W
• lp_ana::fib_enable::ANA_FIB_ENA_R
• lp_ana::fib_enable::ANA_FIB_ENA_W
• lp_ana::fib_enable::R
• lp_ana::fib_enable::W
• lp_ana::int_clr::BOD_MODE0_W
• lp_ana::int_clr::W
• lp_ana::int_ena::BOD_MODE0_R
• lp_ana::int_ena::BOD_MODE0_W
• lp_ana::int_ena::R
• lp_ana::int_ena::W
• lp_ana::int_raw::BOD_MODE0_R
• lp_ana::int_raw::BOD_MODE0_W
• lp_ana::int_raw::R
• lp_ana::int_raw::W
• lp_ana::int_st::BOD_MODE0_R
• lp_ana::int_st::R
• lp_ana::lp_int_clr::BOD_MODE0_W
• lp_ana::lp_int_clr::W
• lp_ana::lp_int_ena::BOD_MODE0_R
• lp_ana::lp_int_ena::BOD_MODE0_W
• lp_ana::lp_int_ena::R
• lp_ana::lp_int_ena::W
• lp_ana::lp_int_raw::BOD_MODE0_R
• lp_ana::lp_int_raw::BOD_MODE0_W
• lp_ana::lp_int_raw::R
• lp_ana::lp_int_raw::W
• lp_ana::lp_int_st::BOD_MODE0_R
• lp_ana::lp_int_st::R
• lp_aon::CPUCORE0_CFG
• lp_aon::DATE
• lp_aon::EXT_WAKEUP_CNTL
• lp_aon::GPIO_HOLD0
• lp_aon::GPIO_HOLD1
• lp_aon::GPIO_MUX
• lp_aon::IO_MUX
• lp_aon::LPBUS
• lp_aon::LPCORE
• lp_aon::SAR_CCT
• lp_aon::SDIO_ACTIVE
• lp_aon::STORE0
• lp_aon::STORE1
• lp_aon::STORE2
• lp_aon::STORE3
• lp_aon::STORE4
• lp_aon::STORE5
• lp_aon::STORE6
• lp_aon::STORE7
• lp_aon::STORE8
• lp_aon::STORE9
• lp_aon::SYS_CFG
• lp_aon::USB
• lp_aon::cpucore0_cfg::CPU_CORE0_DRESET_MASK_R
• lp_aon::cpucore0_cfg::CPU_CORE0_DRESET_MASK_W
• lp_aon::cpucore0_cfg::CPU_CORE0_OCD_HALT_ON_RESET_R
• lp_aon::cpucore0_cfg::CPU_CORE0_OCD_HALT_ON_RESET_W
• lp_aon::cpucore0_cfg::CPU_CORE0_STAT_VECTOR_SEL_R
• lp_aon::cpucore0_cfg::CPU_CORE0_STAT_VECTOR_SEL_W
• lp_aon::cpucore0_cfg::CPU_CORE0_SW_RESET_W
• lp_aon::cpucore0_cfg::CPU_CORE0_SW_STALL_R
• lp_aon::cpucore0_cfg::CPU_CORE0_SW_STALL_W
• lp_aon::cpucore0_cfg::R
• lp_aon::cpucore0_cfg::W
• lp_aon::date::CLK_EN_R
• lp_aon::date::CLK_EN_W
• lp_aon::date::DATE_R
• lp_aon::date::DATE_W
• lp_aon::date::R
• lp_aon::date::W
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_FILTER_R
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_FILTER_W
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_LV_R
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_LV_W
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_SEL_R
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_SEL_W
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_STATUS_CLR_W
• lp_aon::ext_wakeup_cntl::EXT_WAKEUP_STATUS_R
• lp_aon::ext_wakeup_cntl::R
• lp_aon::ext_wakeup_cntl::W
• lp_aon::gpio_hold0::GPIO_HOLD0_R
• lp_aon::gpio_hold0::GPIO_HOLD0_W
• lp_aon::gpio_hold0::R
• lp_aon::gpio_hold0::W
• lp_aon::gpio_hold1::GPIO_HOLD1_R
• lp_aon::gpio_hold1::GPIO_HOLD1_W
• lp_aon::gpio_hold1::R
• lp_aon::gpio_hold1::W
• lp_aon::gpio_mux::R
• lp_aon::gpio_mux::SEL_R
• lp_aon::gpio_mux::SEL_W
• lp_aon::gpio_mux::W
• lp_aon::io_mux::R
• lp_aon::io_mux::RESET_DISABLE_R
• lp_aon::io_mux::RESET_DISABLE_W
• lp_aon::io_mux::W
• lp_aon::lpbus::FAST_MEM_MUX_FSM_IDLE_R
• lp_aon::lpbus::FAST_MEM_MUX_SEL_R
• lp_aon::lpbus::FAST_MEM_MUX_SEL_STATUS_R
• lp_aon::lpbus::FAST_MEM_MUX_SEL_UPDATE_W
• lp_aon::lpbus::FAST_MEM_MUX_SEL_W
• lp_aon::lpbus::FAST_MEM_RA_R
• lp_aon::lpbus::FAST_MEM_RA_W
• lp_aon::lpbus::FAST_MEM_WA_R
• lp_aon::lpbus::FAST_MEM_WA_W
• lp_aon::lpbus::FAST_MEM_WPULSE_R
• lp_aon::lpbus::FAST_MEM_WPULSE_W
• lp_aon::lpbus::R
• lp_aon::lpbus::W
• lp_aon::lpcore::DISABLE_R
• lp_aon::lpcore::DISABLE_W
• lp_aon::lpcore::ETM_WAKEUP_FLAG_CLR_W
• lp_aon::lpcore::ETM_WAKEUP_FLAG_R
• lp_aon::lpcore::ETM_WAKEUP_FLAG_W
• lp_aon::lpcore::R
• lp_aon::lpcore::W
• lp_aon::sar_cct::R
• lp_aon::sar_cct::SAR2_PWDET_CCT_R
• lp_aon::sar_cct::SAR2_PWDET_CCT_W
• lp_aon::sar_cct::W
• lp_aon::sdio_active::R
• lp_aon::sdio_active::SDIO_ACT_DNUM_R
• lp_aon::sdio_active::SDIO_ACT_DNUM_W
• lp_aon::sdio_active::W
• lp_aon::store0::LP_AON_STORE0_R
• lp_aon::store0::LP_AON_STORE0_W
• lp_aon::store0::R
• lp_aon::store0::W
• lp_aon::store1::LP_AON_STORE1_R
• lp_aon::store1::LP_AON_STORE1_W
• lp_aon::store1::R
• lp_aon::store1::W
• lp_aon::store2::LP_AON_STORE2_R
• lp_aon::store2::LP_AON_STORE2_W
• lp_aon::store2::R
• lp_aon::store2::W
• lp_aon::store3::LP_AON_STORE3_R
• lp_aon::store3::LP_AON_STORE3_W
• lp_aon::store3::R
• lp_aon::store3::W
• lp_aon::store4::LP_AON_STORE4_R
• lp_aon::store4::LP_AON_STORE4_W
• lp_aon::store4::R
• lp_aon::store4::W
• lp_aon::store5::LP_AON_STORE5_R
• lp_aon::store5::LP_AON_STORE5_W
• lp_aon::store5::R
• lp_aon::store5::W
• lp_aon::store6::LP_AON_STORE6_R
• lp_aon::store6::LP_AON_STORE6_W
• lp_aon::store6::R
• lp_aon::store6::W
• lp_aon::store7::LP_AON_STORE7_R
• lp_aon::store7::LP_AON_STORE7_W
• lp_aon::store7::R
• lp_aon::store7::W
• lp_aon::store8::LP_AON_STORE8_R
• lp_aon::store8::LP_AON_STORE8_W
• lp_aon::store8::R
• lp_aon::store8::W
• lp_aon::store9::LP_AON_STORE9_R
• lp_aon::store9::LP_AON_STORE9_W
• lp_aon::store9::R
• lp_aon::store9::W
• lp_aon::sys_cfg::FORCE_DOWNLOAD_BOOT_R
• lp_aon::sys_cfg::FORCE_DOWNLOAD_BOOT_W
• lp_aon::sys_cfg::HPSYS_SW_RESET_W
• lp_aon::sys_cfg::R
• lp_aon::sys_cfg::W
• lp_aon::usb::R
• lp_aon::usb::RESET_DISABLE_R
• lp_aon::usb::RESET_DISABLE_W
• lp_aon::usb::W
• lp_apm0::CLOCK_GATE
• lp_apm0::DATE
• lp_apm0::FUNC_CTRL
• lp_apm0::INT_EN
• lp_apm0::REGION_FILTER_EN
• lp_apm0::clock_gate::CLK_EN_R
• lp_apm0::clock_gate::CLK_EN_W
• lp_apm0::clock_gate::R
• lp_apm0::clock_gate::W
• lp_apm0::date::DATE_R
• lp_apm0::date::DATE_W
• lp_apm0::date::R
• lp_apm0::date::W
• lp_apm0::func_ctrl::M_PMS_FUNC_EN_R
• lp_apm0::func_ctrl::M_PMS_FUNC_EN_W
• lp_apm0::func_ctrl::R
• lp_apm0::func_ctrl::W
• lp_apm0::int_en::M_APM_R
• lp_apm0::int_en::M_APM_W
• lp_apm0::int_en::R
• lp_apm0::int_en::W
• lp_apm0::m::EXCEPTION_INFO0
• lp_apm0::m::EXCEPTION_INFO1
• lp_apm0::m::STATUS
• lp_apm0::m::STATUS_CLR
• lp_apm0::m::exception_info0::EXCEPTION_ID_R
• lp_apm0::m::exception_info0::EXCEPTION_MODE_R
• lp_apm0::m::exception_info0::EXCEPTION_REGION_R
• lp_apm0::m::exception_info0::R
• lp_apm0::m::exception_info1::EXCEPTION_ADDR_R
• lp_apm0::m::exception_info1::R
• lp_apm0::m::status::EXCEPTION_STATUS_R
• lp_apm0::m::status::R
• lp_apm0::m::status_clr::REGION_STATUS_CLR_W
• lp_apm0::m::status_clr::W
• lp_apm0::region::ADDR_END
• lp_apm0::region::ADDR_START
• lp_apm0::region::PMS_ATTR
• lp_apm0::region::addr_end::ADDR_END_R
• lp_apm0::region::addr_end::ADDR_END_W
• lp_apm0::region::addr_end::R
• lp_apm0::region::addr_end::W
• lp_apm0::region::addr_start::ADDR_START_R
• lp_apm0::region::addr_start::ADDR_START_W
• lp_apm0::region::addr_start::R
• lp_apm0::region::addr_start::W
• lp_apm0::region::pms_attr::R
• lp_apm0::region::pms_attr::R_PMS_R_R
• lp_apm0::region::pms_attr::R_PMS_R_W
• lp_apm0::region::pms_attr::R_PMS_W_R
• lp_apm0::region::pms_attr::R_PMS_W_W
• lp_apm0::region::pms_attr::R_PMS_X_R
• lp_apm0::region::pms_attr::R_PMS_X_W
• lp_apm0::region::pms_attr::W
• lp_apm0::region_filter_en::R
• lp_apm0::region_filter_en::REGION_FILTER_EN_R
• lp_apm0::region_filter_en::REGION_FILTER_EN_W
• lp_apm0::region_filter_en::W
• lp_apm::CLOCK_GATE
• lp_apm::DATE
• lp_apm::FUNC_CTRL
• lp_apm::INT_EN
• lp_apm::REGION_FILTER_EN
• lp_apm::clock_gate::CLK_EN_R
• lp_apm::clock_gate::CLK_EN_W
• lp_apm::clock_gate::R
• lp_apm::clock_gate::W
• lp_apm::date::DATE_R
• lp_apm::date::DATE_W
• lp_apm::date::R
• lp_apm::date::W
• lp_apm::func_ctrl::M_PMS_FUNC_EN_R
• lp_apm::func_ctrl::M_PMS_FUNC_EN_W
• lp_apm::func_ctrl::R
• lp_apm::func_ctrl::W
• lp_apm::int_en::M_APM_R
• lp_apm::int_en::M_APM_W
• lp_apm::int_en::R
• lp_apm::int_en::W
• lp_apm::m::EXCEPTION_INFO0
• lp_apm::m::EXCEPTION_INFO1
• lp_apm::m::STATUS
• lp_apm::m::STATUS_CLR
• lp_apm::m::exception_info0::EXCEPTION_ID_R
• lp_apm::m::exception_info0::EXCEPTION_MODE_R
• lp_apm::m::exception_info0::EXCEPTION_REGION_R
• lp_apm::m::exception_info0::R
• lp_apm::m::exception_info1::EXCEPTION_ADDR_R
• lp_apm::m::exception_info1::R
• lp_apm::m::status::EXCEPTION_STATUS_R
• lp_apm::m::status::R
• lp_apm::m::status_clr::REGION_STATUS_CLR_W
• lp_apm::m::status_clr::W
• lp_apm::region::ADDR_END
• lp_apm::region::ADDR_START
• lp_apm::region::PMS_ATTR
• lp_apm::region::addr_end::ADDR_END_R
• lp_apm::region::addr_end::ADDR_END_W
• lp_apm::region::addr_end::R
• lp_apm::region::addr_end::W
• lp_apm::region::addr_start::ADDR_START_R
• lp_apm::region::addr_start::ADDR_START_W
• lp_apm::region::addr_start::R
• lp_apm::region::addr_start::W
• lp_apm::region::pms_attr::R
• lp_apm::region::pms_attr::R_PMS_R_R
• lp_apm::region::pms_attr::R_PMS_R_W
• lp_apm::region::pms_attr::R_PMS_W_R
• lp_apm::region::pms_attr::R_PMS_W_W
• lp_apm::region::pms_attr::R_PMS_X_R
• lp_apm::region::pms_attr::R_PMS_X_W
• lp_apm::region::pms_attr::W
• lp_apm::region_filter_en::R
• lp_apm::region_filter_en::REGION_FILTER_EN_R
• lp_apm::region_filter_en::REGION_FILTER_EN_W
• lp_apm::region_filter_en::W
• lp_clkrst::CLK_TO_HP
• lp_clkrst::CPU_RESET
• lp_clkrst::DATE
• lp_clkrst::FOSC_CNTL
• lp_clkrst::LPMEM_FORCE
• lp_clkrst::LPPERI
• lp_clkrst::LP_CLK_CONF
• lp_clkrst::LP_CLK_EN
• lp_clkrst::LP_CLK_PO_EN
• lp_clkrst::LP_RST_EN
• lp_clkrst::RC32K_CNTL
• lp_clkrst::RESET_CAUSE
• lp_clkrst::XTAL32K
• lp_clkrst::clk_to_hp::ICG_HP_FOSC_R
• lp_clkrst::clk_to_hp::ICG_HP_FOSC_W
• lp_clkrst::clk_to_hp::ICG_HP_OSC32K_R
• lp_clkrst::clk_to_hp::ICG_HP_OSC32K_W
• lp_clkrst::clk_to_hp::ICG_HP_SOSC_R
• lp_clkrst::clk_to_hp::ICG_HP_SOSC_W
• lp_clkrst::clk_to_hp::ICG_HP_XTAL32K_R
• lp_clkrst::clk_to_hp::ICG_HP_XTAL32K_W
• lp_clkrst::clk_to_hp::R
• lp_clkrst::clk_to_hp::W
• lp_clkrst::cpu_reset::CPU_STALL_EN_R
• lp_clkrst::cpu_reset::CPU_STALL_EN_W
• lp_clkrst::cpu_reset::CPU_STALL_WAIT_R
• lp_clkrst::cpu_reset::CPU_STALL_WAIT_W
• lp_clkrst::cpu_reset::R
• lp_clkrst::cpu_reset::RTC_WDT_CPU_RESET_EN_R
• lp_clkrst::cpu_reset::RTC_WDT_CPU_RESET_EN_W
• lp_clkrst::cpu_reset::RTC_WDT_CPU_RESET_LENGTH_R
• lp_clkrst::cpu_reset::RTC_WDT_CPU_RESET_LENGTH_W
• lp_clkrst::cpu_reset::W
• lp_clkrst::date::CLKRST_DATE_R
• lp_clkrst::date::CLKRST_DATE_W
• lp_clkrst::date::CLK_EN_R
• lp_clkrst::date::CLK_EN_W
• lp_clkrst::date::R
• lp_clkrst::date::W
• lp_clkrst::fosc_cntl::FOSC_DFREQ_R
• lp_clkrst::fosc_cntl::FOSC_DFREQ_W
• lp_clkrst::fosc_cntl::R
• lp_clkrst::fosc_cntl::W
• lp_clkrst::lp_clk_conf::FAST_CLK_SEL_R
• lp_clkrst::lp_clk_conf::FAST_CLK_SEL_W
• lp_clkrst::lp_clk_conf::LP_PERI_DIV_NUM_R
• lp_clkrst::lp_clk_conf::LP_PERI_DIV_NUM_W
• lp_clkrst::lp_clk_conf::R
• lp_clkrst::lp_clk_conf::SLOW_CLK_SEL_R
• lp_clkrst::lp_clk_conf::SLOW_CLK_SEL_W
• lp_clkrst::lp_clk_conf::W
• lp_clkrst::lp_clk_en::FAST_ORI_GATE_R
• lp_clkrst::lp_clk_en::FAST_ORI_GATE_W
• lp_clkrst::lp_clk_en::R
• lp_clkrst::lp_clk_en::W
• lp_clkrst::lp_clk_po_en::AON_FAST_OEN_R
• lp_clkrst::lp_clk_po_en::AON_FAST_OEN_W
• lp_clkrst::lp_clk_po_en::AON_SLOW_OEN_R
• lp_clkrst::lp_clk_po_en::AON_SLOW_OEN_W
• lp_clkrst::lp_clk_po_en::CORE_EFUSE_OEN_R
• lp_clkrst::lp_clk_po_en::CORE_EFUSE_OEN_W
• lp_clkrst::lp_clk_po_en::FAST_OEN_R
• lp_clkrst::lp_clk_po_en::FAST_OEN_W
• lp_clkrst::lp_clk_po_en::FOSC_OEN_R
• lp_clkrst::lp_clk_po_en::FOSC_OEN_W
• lp_clkrst::lp_clk_po_en::LPBUS_OEN_R
• lp_clkrst::lp_clk_po_en::LPBUS_OEN_W
• lp_clkrst::lp_clk_po_en::OSC32K_OEN_R
• lp_clkrst::lp_clk_po_en::OSC32K_OEN_W
• lp_clkrst::lp_clk_po_en::R
• lp_clkrst::lp_clk_po_en::RNG_OEN_R
• lp_clkrst::lp_clk_po_en::RNG_OEN_W
• lp_clkrst::lp_clk_po_en::SLOW_OEN_R
• lp_clkrst::lp_clk_po_en::SLOW_OEN_W
• lp_clkrst::lp_clk_po_en::SOSC_OEN_R
• lp_clkrst::lp_clk_po_en::SOSC_OEN_W
• lp_clkrst::lp_clk_po_en::W
• lp_clkrst::lp_clk_po_en::XTAL32K_OEN_R
• lp_clkrst::lp_clk_po_en::XTAL32K_OEN_W
• lp_clkrst::lp_rst_en::ANA_PERI_RESET_EN_R
• lp_clkrst::lp_rst_en::ANA_PERI_RESET_EN_W
• lp_clkrst::lp_rst_en::AON_EFUSE_CORE_RESET_EN_R
• lp_clkrst::lp_rst_en::AON_EFUSE_CORE_RESET_EN_W
• lp_clkrst::lp_rst_en::LP_TIMER_RESET_EN_R
• lp_clkrst::lp_rst_en::LP_TIMER_RESET_EN_W
• lp_clkrst::lp_rst_en::R
• lp_clkrst::lp_rst_en::W
• lp_clkrst::lp_rst_en::WDT_RESET_EN_R
• lp_clkrst::lp_rst_en::WDT_RESET_EN_W
• lp_clkrst::lpmem_force::LPMEM_CLK_FORCE_ON_R
• lp_clkrst::lpmem_force::LPMEM_CLK_FORCE_ON_W
• lp_clkrst::lpmem_force::R
• lp_clkrst::lpmem_force::W
• lp_clkrst::lpperi::LP_I2C_CLK_SEL_R
• lp_clkrst::lpperi::LP_I2C_CLK_SEL_W
• lp_clkrst::lpperi::LP_UART_CLK_SEL_R
• lp_clkrst::lpperi::LP_UART_CLK_SEL_W
• lp_clkrst::lpperi::R
• lp_clkrst::lpperi::W
• lp_clkrst::rc32k_cntl::R
• lp_clkrst::rc32k_cntl::RC32K_DFREQ_R
• lp_clkrst::rc32k_cntl::RC32K_DFREQ_W
• lp_clkrst::rc32k_cntl::W
• lp_clkrst::reset_cause::CORE0_RESET_CAUSE_CLR_W
• lp_clkrst::reset_cause::CORE0_RESET_FLAG_CLR_W
• lp_clkrst::reset_cause::CORE0_RESET_FLAG_R
• lp_clkrst::reset_cause::CORE0_RESET_FLAG_SET_W
• lp_clkrst::reset_cause::R
• lp_clkrst::reset_cause::RESET_CAUSE_R
• lp_clkrst::reset_cause::W
• lp_clkrst::xtal32k::DAC_XTAL32K_R
• lp_clkrst::xtal32k::DAC_XTAL32K_W
• lp_clkrst::xtal32k::DBUF_XTAL32K_R
• lp_clkrst::xtal32k::DBUF_XTAL32K_W
• lp_clkrst::xtal32k::DGM_XTAL32K_R
• lp_clkrst::xtal32k::DGM_XTAL32K_W
• lp_clkrst::xtal32k::DRES_XTAL32K_R
• lp_clkrst::xtal32k::DRES_XTAL32K_W
• lp_clkrst::xtal32k::R
• lp_clkrst::xtal32k::W
• lp_i2c0::CLK_CONF
• lp_i2c0::COMD
• lp_i2c0::CTR
• lp_i2c0::DATA
• lp_i2c0::DATE
• lp_i2c0::FIFO_CONF
• lp_i2c0::FIFO_ST
• lp_i2c0::FILTER_CFG
• lp_i2c0::INT_CLR
• lp_i2c0::INT_ENA
• lp_i2c0::INT_RAW
• lp_i2c0::INT_ST
• lp_i2c0::RXFIFO_START_ADDR
• lp_i2c0::SCL_HIGH_PERIOD
• lp_i2c0::SCL_LOW_PERIOD
• lp_i2c0::SCL_MAIN_ST_TIME_OUT
• lp_i2c0::SCL_RSTART_SETUP
• lp_i2c0::SCL_SP_CONF
• lp_i2c0::SCL_START_HOLD
• lp_i2c0::SCL_STOP_HOLD
• lp_i2c0::SCL_STOP_SETUP
• lp_i2c0::SCL_ST_TIME_OUT
• lp_i2c0::SDA_HOLD
• lp_i2c0::SDA_SAMPLE
• lp_i2c0::SR
• lp_i2c0::TO
• lp_i2c0::TXFIFO_START_ADDR
• lp_i2c0::clk_conf::R
• lp_i2c0::clk_conf::SCLK_ACTIVE_R
• lp_i2c0::clk_conf::SCLK_ACTIVE_W
• lp_i2c0::clk_conf::SCLK_DIV_A_R
• lp_i2c0::clk_conf::SCLK_DIV_A_W
• lp_i2c0::clk_conf::SCLK_DIV_B_R
• lp_i2c0::clk_conf::SCLK_DIV_B_W
• lp_i2c0::clk_conf::SCLK_DIV_NUM_R
• lp_i2c0::clk_conf::SCLK_DIV_NUM_W
• lp_i2c0::clk_conf::SCLK_SEL_R
• lp_i2c0::clk_conf::SCLK_SEL_W
• lp_i2c0::clk_conf::W
• lp_i2c0::comd::COMMAND_DONE_R
• lp_i2c0::comd::COMMAND_DONE_W
• lp_i2c0::comd::COMMAND_R
• lp_i2c0::comd::COMMAND_W
• lp_i2c0::comd::R
• lp_i2c0::comd::W
• lp_i2c0::ctr::ARBITRATION_EN_R
• lp_i2c0::ctr::ARBITRATION_EN_W
• lp_i2c0::ctr::CLK_EN_R
• lp_i2c0::ctr::CLK_EN_W
• lp_i2c0::ctr::CONF_UPGATE_W
• lp_i2c0::ctr::FSM_RST_W
• lp_i2c0::ctr::R
• lp_i2c0::ctr::RX_FULL_ACK_LEVEL_R
• lp_i2c0::ctr::RX_FULL_ACK_LEVEL_W
• lp_i2c0::ctr::RX_LSB_FIRST_R
• lp_i2c0::ctr::RX_LSB_FIRST_W
• lp_i2c0::ctr::SAMPLE_SCL_LEVEL_R
• lp_i2c0::ctr::SAMPLE_SCL_LEVEL_W
• lp_i2c0::ctr::SCL_FORCE_OUT_R
• lp_i2c0::ctr::SCL_FORCE_OUT_W
• lp_i2c0::ctr::SDA_FORCE_OUT_R
• lp_i2c0::ctr::SDA_FORCE_OUT_W
• lp_i2c0::ctr::TRANS_START_W
• lp_i2c0::ctr::TX_LSB_FIRST_R
• lp_i2c0::ctr::TX_LSB_FIRST_W
• lp_i2c0::ctr::W
• lp_i2c0::data::FIFO_RDATA_R
• lp_i2c0::data::FIFO_RDATA_W
• lp_i2c0::data::R
• lp_i2c0::data::W
• lp_i2c0::date::DATE_R
• lp_i2c0::date::DATE_W
• lp_i2c0::date::R
• lp_i2c0::date::W
• lp_i2c0::fifo_conf::FIFO_PRT_EN_R
• lp_i2c0::fifo_conf::FIFO_PRT_EN_W
• lp_i2c0::fifo_conf::NONFIFO_EN_R
• lp_i2c0::fifo_conf::NONFIFO_EN_W
• lp_i2c0::fifo_conf::R
• lp_i2c0::fifo_conf::RXFIFO_WM_THRHD_R
• lp_i2c0::fifo_conf::RXFIFO_WM_THRHD_W
• lp_i2c0::fifo_conf::RX_FIFO_RST_R
• lp_i2c0::fifo_conf::RX_FIFO_RST_W
• lp_i2c0::fifo_conf::TXFIFO_WM_THRHD_R
• lp_i2c0::fifo_conf::TXFIFO_WM_THRHD_W
• lp_i2c0::fifo_conf::TX_FIFO_RST_R
• lp_i2c0::fifo_conf::TX_FIFO_RST_W
• lp_i2c0::fifo_conf::W
• lp_i2c0::fifo_st::R
• lp_i2c0::fifo_st::RXFIFO_RADDR_R
• lp_i2c0::fifo_st::RXFIFO_WADDR_R
• lp_i2c0::fifo_st::TXFIFO_RADDR_R
• lp_i2c0::fifo_st::TXFIFO_WADDR_R
• lp_i2c0::filter_cfg::R
• lp_i2c0::filter_cfg::SCL_FILTER_EN_R
• lp_i2c0::filter_cfg::SCL_FILTER_EN_W
• lp_i2c0::filter_cfg::SCL_FILTER_THRES_R
• lp_i2c0::filter_cfg::SCL_FILTER_THRES_W
• lp_i2c0::filter_cfg::SDA_FILTER_EN_R
• lp_i2c0::filter_cfg::SDA_FILTER_EN_W
• lp_i2c0::filter_cfg::SDA_FILTER_THRES_R
• lp_i2c0::filter_cfg::SDA_FILTER_THRES_W
• lp_i2c0::filter_cfg::W
• lp_i2c0::int_clr::ARBITRATION_LOST_W
• lp_i2c0::int_clr::BYTE_TRANS_DONE_W
• lp_i2c0::int_clr::DET_START_W
• lp_i2c0::int_clr::END_DETECT_W
• lp_i2c0::int_clr::MST_TXFIFO_UDF_W
• lp_i2c0::int_clr::NACK_W
• lp_i2c0::int_clr::RXFIFO_OVF_W
• lp_i2c0::int_clr::RXFIFO_UDF_W
• lp_i2c0::int_clr::RXFIFO_WM_W
• lp_i2c0::int_clr::SCL_MAIN_ST_TO_W
• lp_i2c0::int_clr::SCL_ST_TO_W
• lp_i2c0::int_clr::TIME_OUT_W
• lp_i2c0::int_clr::TRANS_COMPLETE_W
• lp_i2c0::int_clr::TRANS_START_W
• lp_i2c0::int_clr::TXFIFO_OVF_W
• lp_i2c0::int_clr::TXFIFO_WM_W
• lp_i2c0::int_clr::W
• lp_i2c0::int_ena::ARBITRATION_LOST_R
• lp_i2c0::int_ena::ARBITRATION_LOST_W
• lp_i2c0::int_ena::BYTE_TRANS_DONE_R
• lp_i2c0::int_ena::BYTE_TRANS_DONE_W
• lp_i2c0::int_ena::DET_START_R
• lp_i2c0::int_ena::DET_START_W
• lp_i2c0::int_ena::END_DETECT_R
• lp_i2c0::int_ena::END_DETECT_W
• lp_i2c0::int_ena::MST_TXFIFO_UDF_R
• lp_i2c0::int_ena::MST_TXFIFO_UDF_W
• lp_i2c0::int_ena::NACK_R
• lp_i2c0::int_ena::NACK_W
• lp_i2c0::int_ena::R
• lp_i2c0::int_ena::RXFIFO_OVF_R
• lp_i2c0::int_ena::RXFIFO_OVF_W
• lp_i2c0::int_ena::RXFIFO_UDF_R
• lp_i2c0::int_ena::RXFIFO_UDF_W
• lp_i2c0::int_ena::RXFIFO_WM_R
• lp_i2c0::int_ena::RXFIFO_WM_W
• lp_i2c0::int_ena::SCL_MAIN_ST_TO_R
• lp_i2c0::int_ena::SCL_MAIN_ST_TO_W
• lp_i2c0::int_ena::SCL_ST_TO_R
• lp_i2c0::int_ena::SCL_ST_TO_W
• lp_i2c0::int_ena::TIME_OUT_R
• lp_i2c0::int_ena::TIME_OUT_W
• lp_i2c0::int_ena::TRANS_COMPLETE_R
• lp_i2c0::int_ena::TRANS_COMPLETE_W
• lp_i2c0::int_ena::TRANS_START_R
• lp_i2c0::int_ena::TRANS_START_W
• lp_i2c0::int_ena::TXFIFO_OVF_R
• lp_i2c0::int_ena::TXFIFO_OVF_W
• lp_i2c0::int_ena::TXFIFO_WM_R
• lp_i2c0::int_ena::TXFIFO_WM_W
• lp_i2c0::int_ena::W
• lp_i2c0::int_raw::ARBITRATION_LOST_R
• lp_i2c0::int_raw::BYTE_TRANS_DONE_R
• lp_i2c0::int_raw::DET_START_R
• lp_i2c0::int_raw::END_DETECT_R
• lp_i2c0::int_raw::MST_TXFIFO_UDF_R
• lp_i2c0::int_raw::NACK_R
• lp_i2c0::int_raw::R
• lp_i2c0::int_raw::RXFIFO_OVF_R
• lp_i2c0::int_raw::RXFIFO_UDF_R
• lp_i2c0::int_raw::RXFIFO_WM_R
• lp_i2c0::int_raw::SCL_MAIN_ST_TO_R
• lp_i2c0::int_raw::SCL_ST_TO_R
• lp_i2c0::int_raw::TIME_OUT_R
• lp_i2c0::int_raw::TRANS_COMPLETE_R
• lp_i2c0::int_raw::TRANS_START_R
• lp_i2c0::int_raw::TXFIFO_OVF_R
• lp_i2c0::int_raw::TXFIFO_WM_R
• lp_i2c0::int_st::ARBITRATION_LOST_R
• lp_i2c0::int_st::BYTE_TRANS_DONE_R
• lp_i2c0::int_st::DET_START_R
• lp_i2c0::int_st::END_DETECT_R
• lp_i2c0::int_st::MST_TXFIFO_UDF_R
• lp_i2c0::int_st::NACK_R
• lp_i2c0::int_st::R
• lp_i2c0::int_st::RXFIFO_OVF_R
• lp_i2c0::int_st::RXFIFO_UDF_R
• lp_i2c0::int_st::RXFIFO_WM_R
• lp_i2c0::int_st::SCL_MAIN_ST_TO_R
• lp_i2c0::int_st::SCL_ST_TO_R
• lp_i2c0::int_st::TIME_OUT_R
• lp_i2c0::int_st::TRANS_COMPLETE_R
• lp_i2c0::int_st::TRANS_START_R
• lp_i2c0::int_st::TXFIFO_OVF_R
• lp_i2c0::int_st::TXFIFO_WM_R
• lp_i2c0::rxfifo_start_addr::R
• lp_i2c0::rxfifo_start_addr::RXFIFO_START_ADDR_R
• lp_i2c0::scl_high_period::R
• lp_i2c0::scl_high_period::SCL_HIGH_PERIOD_R
• lp_i2c0::scl_high_period::SCL_HIGH_PERIOD_W
• lp_i2c0::scl_high_period::SCL_WAIT_HIGH_PERIOD_R
• lp_i2c0::scl_high_period::SCL_WAIT_HIGH_PERIOD_W
• lp_i2c0::scl_high_period::W
• lp_i2c0::scl_low_period::R
• lp_i2c0::scl_low_period::SCL_LOW_PERIOD_R
• lp_i2c0::scl_low_period::SCL_LOW_PERIOD_W
• lp_i2c0::scl_low_period::W
• lp_i2c0::scl_main_st_time_out::R
• lp_i2c0::scl_main_st_time_out::SCL_MAIN_ST_TO_I2C_R
• lp_i2c0::scl_main_st_time_out::SCL_MAIN_ST_TO_I2C_W
• lp_i2c0::scl_main_st_time_out::W
• lp_i2c0::scl_rstart_setup::R
• lp_i2c0::scl_rstart_setup::TIME_R
• lp_i2c0::scl_rstart_setup::TIME_W
• lp_i2c0::scl_rstart_setup::W
• lp_i2c0::scl_sp_conf::R
• lp_i2c0::scl_sp_conf::SCL_PD_EN_R
• lp_i2c0::scl_sp_conf::SCL_PD_EN_W
• lp_i2c0::scl_sp_conf::SCL_RST_SLV_EN_R
• lp_i2c0::scl_sp_conf::SCL_RST_SLV_EN_W
• lp_i2c0::scl_sp_conf::SCL_RST_SLV_NUM_R
• lp_i2c0::scl_sp_conf::SCL_RST_SLV_NUM_W
• lp_i2c0::scl_sp_conf::SDA_PD_EN_R
• lp_i2c0::scl_sp_conf::SDA_PD_EN_W
• lp_i2c0::scl_sp_conf::W
• lp_i2c0::scl_st_time_out::R
• lp_i2c0::scl_st_time_out::SCL_ST_TO_I2C_R
• lp_i2c0::scl_st_time_out::SCL_ST_TO_I2C_W
• lp_i2c0::scl_st_time_out::W
• lp_i2c0::scl_start_hold::R
• lp_i2c0::scl_start_hold::TIME_R
• lp_i2c0::scl_start_hold::TIME_W
• lp_i2c0::scl_start_hold::W
• lp_i2c0::scl_stop_hold::R
• lp_i2c0::scl_stop_hold::TIME_R
• lp_i2c0::scl_stop_hold::TIME_W
• lp_i2c0::scl_stop_hold::W
• lp_i2c0::scl_stop_setup::R
• lp_i2c0::scl_stop_setup::TIME_R
• lp_i2c0::scl_stop_setup::TIME_W
• lp_i2c0::scl_stop_setup::W
• lp_i2c0::sda_hold::R
• lp_i2c0::sda_hold::TIME_R
• lp_i2c0::sda_hold::TIME_W
• lp_i2c0::sda_hold::W
• lp_i2c0::sda_sample::R
• lp_i2c0::sda_sample::TIME_R
• lp_i2c0::sda_sample::TIME_W
• lp_i2c0::sda_sample::W
• lp_i2c0::sr::ARB_LOST_R
• lp_i2c0::sr::BUS_BUSY_R
• lp_i2c0::sr::R
• lp_i2c0::sr::RESP_REC_R
• lp_i2c0::sr::RXFIFO_CNT_R
• lp_i2c0::sr::SCL_MAIN_STATE_LAST_R
• lp_i2c0::sr::SCL_STATE_LAST_R
• lp_i2c0::sr::TXFIFO_CNT_R
• lp_i2c0::to::R
• lp_i2c0::to::TIME_OUT_EN_R
• lp_i2c0::to::TIME_OUT_EN_W
• lp_i2c0::to::TIME_OUT_VALUE_R
• lp_i2c0::to::TIME_OUT_VALUE_W
• lp_i2c0::to::W
• lp_i2c0::txfifo_start_addr::R
• lp_i2c0::txfifo_start_addr::TXFIFO_START_ADDR_R
• lp_i2c_ana_mst::ANA_CONF1
• lp_i2c_ana_mst::DATE
• lp_i2c_ana_mst::DEVICE_EN
• lp_i2c_ana_mst::I2C0_CONF
• lp_i2c_ana_mst::I2C0_CTRL
• lp_i2c_ana_mst::I2C0_DATA
• lp_i2c_ana_mst::NOUSE
• lp_i2c_ana_mst::ana_conf1::LP_I2C_ANA_MAST_ANA_CONF1_R
• lp_i2c_ana_mst::ana_conf1::LP_I2C_ANA_MAST_ANA_CONF1_W
• lp_i2c_ana_mst::ana_conf1::R
• lp_i2c_ana_mst::ana_conf1::W
• lp_i2c_ana_mst::date::LP_I2C_ANA_MAST_I2C_MAT_CLK_EN_R
• lp_i2c_ana_mst::date::LP_I2C_ANA_MAST_I2C_MAT_CLK_EN_W
• lp_i2c_ana_mst::date::LP_I2C_ANA_MAST_I2C_MAT_DATE_R
• lp_i2c_ana_mst::date::LP_I2C_ANA_MAST_I2C_MAT_DATE_W
• lp_i2c_ana_mst::date::R
• lp_i2c_ana_mst::date::W
• lp_i2c_ana_mst::device_en::LP_I2C_ANA_MAST_I2C_DEVICE_EN_R
• lp_i2c_ana_mst::device_en::LP_I2C_ANA_MAST_I2C_DEVICE_EN_W
• lp_i2c_ana_mst::device_en::R
• lp_i2c_ana_mst::device_en::W
• lp_i2c_ana_mst::i2c0_conf::LP_I2C_ANA_MAST_I2C0_CONF_R
• lp_i2c_ana_mst::i2c0_conf::LP_I2C_ANA_MAST_I2C0_CONF_W
• lp_i2c_ana_mst::i2c0_conf::LP_I2C_ANA_MAST_I2C0_STATUS_R
• lp_i2c_ana_mst::i2c0_conf::R
• lp_i2c_ana_mst::i2c0_conf::W
• lp_i2c_ana_mst::i2c0_ctrl::LP_I2C_ANA_MAST_I2C0_BUSY_R
• lp_i2c_ana_mst::i2c0_ctrl::LP_I2C_ANA_MAST_I2C0_CTRL_R
• lp_i2c_ana_mst::i2c0_ctrl::LP_I2C_ANA_MAST_I2C0_CTRL_W
• lp_i2c_ana_mst::i2c0_ctrl::R
• lp_i2c_ana_mst::i2c0_ctrl::W
• lp_i2c_ana_mst::i2c0_data::LP_I2C_ANA_MAST_I2C0_CLK_SEL_R
• lp_i2c_ana_mst::i2c0_data::LP_I2C_ANA_MAST_I2C0_CLK_SEL_W
• lp_i2c_ana_mst::i2c0_data::LP_I2C_ANA_MAST_I2C0_RDATA_R
• lp_i2c_ana_mst::i2c0_data::LP_I2C_ANA_MAST_I2C_MST_SEL_R
• lp_i2c_ana_mst::i2c0_data::LP_I2C_ANA_MAST_I2C_MST_SEL_W
• lp_i2c_ana_mst::i2c0_data::R
• lp_i2c_ana_mst::i2c0_data::W
• lp_i2c_ana_mst::nouse::LP_I2C_ANA_MAST_I2C_MST_NOUSE_R
• lp_i2c_ana_mst::nouse::LP_I2C_ANA_MAST_I2C_MST_NOUSE_W
• lp_i2c_ana_mst::nouse::R
• lp_i2c_ana_mst::nouse::W
• lp_io::DATE
• lp_io::DEBUG_SEL0
• lp_io::DEBUG_SEL1
• lp_io::GPIO
• lp_io::IN
• lp_io::LPI2C
• lp_io::OUT_DATA
• lp_io::OUT_DATA_W1TC
• lp_io::OUT_DATA_W1TS
• lp_io::OUT_ENABLE
• lp_io::OUT_ENABLE_W1TC
• lp_io::OUT_ENABLE_W1TS
• lp_io::PIN
• lp_io::STATUS
• lp_io::STATUS_INTERRUPT
• lp_io::STATUS_W1TC
• lp_io::STATUS_W1TS
• lp_io::date::CLK_EN_R
• lp_io::date::CLK_EN_W
• lp_io::date::LP_IO_DATE_R
• lp_io::date::LP_IO_DATE_W
• lp_io::date::R
• lp_io::date::W
• lp_io::debug_sel0::LP_DEBUG_SEL0_R
• lp_io::debug_sel0::LP_DEBUG_SEL0_W
• lp_io::debug_sel0::LP_DEBUG_SEL1_R
• lp_io::debug_sel0::LP_DEBUG_SEL1_W
• lp_io::debug_sel0::LP_DEBUG_SEL2_R
• lp_io::debug_sel0::LP_DEBUG_SEL2_W
• lp_io::debug_sel0::LP_DEBUG_SEL3_R
• lp_io::debug_sel0::LP_DEBUG_SEL3_W
• lp_io::debug_sel0::R
• lp_io::debug_sel0::W
• lp_io::debug_sel1::LP_DEBUG_SEL4_R
• lp_io::debug_sel1::LP_DEBUG_SEL4_W
• lp_io::debug_sel1::R
• lp_io::debug_sel1::W
• lp_io::gpio::FUN_DRV_R
• lp_io::gpio::FUN_DRV_W
• lp_io::gpio::FUN_IE_R
• lp_io::gpio::FUN_IE_W
• lp_io::gpio::FUN_WPD_R
• lp_io::gpio::FUN_WPD_W
• lp_io::gpio::FUN_WPU_R
• lp_io::gpio::FUN_WPU_W
• lp_io::gpio::MCU_DRV_R
• lp_io::gpio::MCU_DRV_W
• lp_io::gpio::MCU_IE_R
• lp_io::gpio::MCU_IE_W
• lp_io::gpio::MCU_OE_R
• lp_io::gpio::MCU_OE_W
• lp_io::gpio::MCU_SEL_R
• lp_io::gpio::MCU_SEL_W
• lp_io::gpio::MCU_WPD_R
• lp_io::gpio::MCU_WPD_W
• lp_io::gpio::MCU_WPU_R
• lp_io::gpio::MCU_WPU_W
• lp_io::gpio::R
• lp_io::gpio::SLP_SEL_R
• lp_io::gpio::SLP_SEL_W
• lp_io::gpio::W
• lp_io::in_::DATA_NEXT_R
• lp_io::in_::R
• lp_io::lpi2c::LP_I2C_SCL_IE_R
• lp_io::lpi2c::LP_I2C_SCL_IE_W
• lp_io::lpi2c::LP_I2C_SDA_IE_R
• lp_io::lpi2c::LP_I2C_SDA_IE_W
• lp_io::lpi2c::R
• lp_io::lpi2c::W
• lp_io::out_data::OUT_DATA_R
• lp_io::out_data::OUT_DATA_W
• lp_io::out_data::R
• lp_io::out_data::W
• lp_io::out_data_w1tc::OUT_DATA_W1TC_W
• lp_io::out_data_w1tc::W
• lp_io::out_data_w1ts::OUT_DATA_W1TS_W
• lp_io::out_data_w1ts::W
• lp_io::out_enable::ENABLE_R
• lp_io::out_enable::ENABLE_W
• lp_io::out_enable::R
• lp_io::out_enable::W
• lp_io::out_enable_w1tc::ENABLE_W1TC_W
• lp_io::out_enable_w1tc::W
• lp_io::out_enable_w1ts::ENABLE_W1TS_W
• lp_io::out_enable_w1ts::W
• lp_io::pin::EDGE_WAKEUP_CLR_W
• lp_io::pin::FILTER_EN_R
• lp_io::pin::FILTER_EN_W
• lp_io::pin::INT_TYPE_R
• lp_io::pin::INT_TYPE_W
• lp_io::pin::PAD_DRIVER_R
• lp_io::pin::PAD_DRIVER_W
• lp_io::pin::R
• lp_io::pin::SYNC_BYPASS_R
• lp_io::pin::SYNC_BYPASS_W
• lp_io::pin::W
• lp_io::pin::WAKEUP_ENABLE_R
• lp_io::pin::WAKEUP_ENABLE_W
• lp_io::status::INTERRUPT_R
• lp_io::status::INTERRUPT_W
• lp_io::status::R
• lp_io::status::W
• lp_io::status_interrupt::NEXT_R
• lp_io::status_interrupt::R
• lp_io::status_w1tc::STATUS_W1TC_W
• lp_io::status_w1tc::W
• lp_io::status_w1ts::STATUS_W1TS_W
• lp_io::status_w1ts::W
• lp_peri::BUS_TIMEOUT
• lp_peri::BUS_TIMEOUT_ADDR
• lp_peri::BUS_TIMEOUT_UID
• lp_peri::CLK_EN
• lp_peri::CPU
• lp_peri::DATE
• lp_peri::INTERRUPT_SOURCE
• lp_peri::MEM_CTRL
• lp_peri::RESET_EN
• lp_peri::RNG_DATA
• lp_peri::bus_timeout::LP_PERI_TIMEOUT_INT_CLEAR_W
• lp_peri::bus_timeout::LP_PERI_TIMEOUT_PROTECT_EN_R
• lp_peri::bus_timeout::LP_PERI_TIMEOUT_PROTECT_EN_W
• lp_peri::bus_timeout::LP_PERI_TIMEOUT_THRES_R
• lp_peri::bus_timeout::LP_PERI_TIMEOUT_THRES_W
• lp_peri::bus_timeout::R
• lp_peri::bus_timeout::W
• lp_peri::bus_timeout_addr::LP_PERI_TIMEOUT_ADDR_R
• lp_peri::bus_timeout_addr::R
• lp_peri::bus_timeout_uid::LP_PERI_TIMEOUT_UID_R
• lp_peri::bus_timeout_uid::R
• lp_peri::clk_en::EFUSE_CK_EN_R
• lp_peri::clk_en::EFUSE_CK_EN_W
• lp_peri::clk_en::LP_ANA_I2C_CK_EN_R
• lp_peri::clk_en::LP_ANA_I2C_CK_EN_W
• lp_peri::clk_en::LP_CPU_CK_EN_R
• lp_peri::clk_en::LP_CPU_CK_EN_W
• lp_peri::clk_en::LP_EXT_I2C_CK_EN_R
• lp_peri::clk_en::LP_EXT_I2C_CK_EN_W
• lp_peri::clk_en::LP_IO_CK_EN_R
• lp_peri::clk_en::LP_IO_CK_EN_W
• lp_peri::clk_en::LP_TOUCH_CK_EN_R
• lp_peri::clk_en::LP_TOUCH_CK_EN_W
• lp_peri::clk_en::LP_UART_CK_EN_R
• lp_peri::clk_en::LP_UART_CK_EN_W
• lp_peri::clk_en::OTP_DBG_CK_EN_R
• lp_peri::clk_en::OTP_DBG_CK_EN_W
• lp_peri::clk_en::R
• lp_peri::clk_en::RNG_CK_EN_R
• lp_peri::clk_en::RNG_CK_EN_W
• lp_peri::clk_en::W
• lp_peri::cpu::LPCORE_DBGM_UNAVALIABLE_R
• lp_peri::cpu::LPCORE_DBGM_UNAVALIABLE_W
• lp_peri::cpu::R
• lp_peri::cpu::W
• lp_peri::date::CLK_EN_R
• lp_peri::date::CLK_EN_W
• lp_peri::date::LPPERI_DATE_R
• lp_peri::date::LPPERI_DATE_W
• lp_peri::date::R
• lp_peri::date::W
• lp_peri::interrupt_source::LP_INTERRUPT_SOURCE_R
• lp_peri::interrupt_source::R
• lp_peri::mem_ctrl::R
• lp_peri::mem_ctrl::UART_MEM_FORCE_PD_R
• lp_peri::mem_ctrl::UART_MEM_FORCE_PD_W
• lp_peri::mem_ctrl::UART_MEM_FORCE_PU_R
• lp_peri::mem_ctrl::UART_MEM_FORCE_PU_W
• lp_peri::mem_ctrl::UART_WAKEUP_EN_R
• lp_peri::mem_ctrl::UART_WAKEUP_EN_W
• lp_peri::mem_ctrl::UART_WAKEUP_FLAG_CLR_W
• lp_peri::mem_ctrl::UART_WAKEUP_FLAG_R
• lp_peri::mem_ctrl::UART_WAKEUP_FLAG_W
• lp_peri::mem_ctrl::W
• lp_peri::reset_en::BUS_RESET_EN_W
• lp_peri::reset_en::EFUSE_RESET_EN_R
• lp_peri::reset_en::EFUSE_RESET_EN_W
• lp_peri::reset_en::LP_ANA_I2C_RESET_EN_R
• lp_peri::reset_en::LP_ANA_I2C_RESET_EN_W
• lp_peri::reset_en::LP_CPU_RESET_EN_W
• lp_peri::reset_en::LP_EXT_I2C_RESET_EN_R
• lp_peri::reset_en::LP_EXT_I2C_RESET_EN_W
• lp_peri::reset_en::LP_IO_RESET_EN_R
• lp_peri::reset_en::LP_IO_RESET_EN_W
• lp_peri::reset_en::LP_TOUCH_RESET_EN_R
• lp_peri::reset_en::LP_TOUCH_RESET_EN_W
• lp_peri::reset_en::LP_UART_RESET_EN_R
• lp_peri::reset_en::LP_UART_RESET_EN_W
• lp_peri::reset_en::OTP_DBG_RESET_EN_R
• lp_peri::reset_en::OTP_DBG_RESET_EN_W
• lp_peri::reset_en::R
• lp_peri::reset_en::W
• lp_peri::rng_data::R
• lp_peri::rng_data::RND_DATA_R
• lp_tee::CLOCK_GATE
• lp_tee::DATE
• lp_tee::FORCE_ACC_HP
• lp_tee::M_MODE_CTRL
• lp_tee::clock_gate::CLK_EN_R
• lp_tee::clock_gate::CLK_EN_W
• lp_tee::clock_gate::R
• lp_tee::clock_gate::W
• lp_tee::date::DATE_R
• lp_tee::date::DATE_W
• lp_tee::date::R
• lp_tee::date::W
• lp_tee::force_acc_hp::LP_AON_FORCE_ACC_HPMEM_EN_R
• lp_tee::force_acc_hp::LP_AON_FORCE_ACC_HPMEM_EN_W
• lp_tee::force_acc_hp::R
• lp_tee::force_acc_hp::W
• lp_tee::m_mode_ctrl::MODE_R
• lp_tee::m_mode_ctrl::MODE_W
• lp_tee::m_mode_ctrl::R
• lp_tee::m_mode_ctrl::W
• lp_timer::DATE
• lp_timer::INT_CLR
• lp_timer::INT_ENA
• lp_timer::INT_RAW
• lp_timer::INT_ST
• lp_timer::LP_INT_CLR
• lp_timer::LP_INT_ENA
• lp_timer::LP_INT_RAW
• lp_timer::LP_INT_ST
• lp_timer::MAIN_BUF0_HIGH
• lp_timer::MAIN_BUF0_LOW
• lp_timer::MAIN_BUF1_HIGH
• lp_timer::MAIN_BUF1_LOW
• lp_timer::MAIN_OVERFLOW
• lp_timer::TAR0_HIGH
• lp_timer::TAR0_LOW
• lp_timer::TAR1_HIGH
• lp_timer::TAR1_LOW
• lp_timer::UPDATE
• lp_timer::date::CLK_EN_R
• lp_timer::date::CLK_EN_W
• lp_timer::date::DATE_R
• lp_timer::date::DATE_W
• lp_timer::date::R
• lp_timer::date::W
• lp_timer::int_clr::OVERFLOW_W
• lp_timer::int_clr::SOC_WAKEUP_W
• lp_timer::int_clr::W
• lp_timer::int_ena::OVERFLOW_R
• lp_timer::int_ena::OVERFLOW_W
• lp_timer::int_ena::R
• lp_timer::int_ena::SOC_WAKEUP_R
• lp_timer::int_ena::SOC_WAKEUP_W
• lp_timer::int_ena::W
• lp_timer::int_raw::OVERFLOW_R
• lp_timer::int_raw::OVERFLOW_W
• lp_timer::int_raw::R
• lp_timer::int_raw::SOC_WAKEUP_R
• lp_timer::int_raw::SOC_WAKEUP_W
• lp_timer::int_raw::W
• lp_timer::int_st::OVERFLOW_R
• lp_timer::int_st::R
• lp_timer::int_st::SOC_WAKEUP_R
• lp_timer::lp_int_clr::MAIN_TIMER_OVERFLOW_W
• lp_timer::lp_int_clr::MAIN_TIMER_W
• lp_timer::lp_int_clr::W
• lp_timer::lp_int_ena::MAIN_TIMER_OVERFLOW_R
• lp_timer::lp_int_ena::MAIN_TIMER_OVERFLOW_W
• lp_timer::lp_int_ena::MAIN_TIMER_R
• lp_timer::lp_int_ena::MAIN_TIMER_W
• lp_timer::lp_int_ena::R
• lp_timer::lp_int_ena::W
• lp_timer::lp_int_raw::MAIN_TIMER_OVERFLOW_R
• lp_timer::lp_int_raw::MAIN_TIMER_OVERFLOW_W
• lp_timer::lp_int_raw::MAIN_TIMER_R
• lp_timer::lp_int_raw::MAIN_TIMER_W
• lp_timer::lp_int_raw::R
• lp_timer::lp_int_raw::W
• lp_timer::lp_int_st::MAIN_TIMER_OVERFLOW_R
• lp_timer::lp_int_st::MAIN_TIMER_R
• lp_timer::lp_int_st::R
• lp_timer::main_buf0_high::MAIN_TIMER_BUF0_HIGH_R
• lp_timer::main_buf0_high::R
• lp_timer::main_buf0_low::MAIN_TIMER_BUF0_LOW_R
• lp_timer::main_buf0_low::R
• lp_timer::main_buf1_high::MAIN_TIMER_BUF1_HIGH_R
• lp_timer::main_buf1_high::R
• lp_timer::main_buf1_low::MAIN_TIMER_BUF1_LOW_R
• lp_timer::main_buf1_low::R
• lp_timer::main_overflow::MAIN_TIMER_ALARM_LOAD_W
• lp_timer::main_overflow::W
• lp_timer::tar0_high::MAIN_TIMER_TAR_EN0_W
• lp_timer::tar0_high::MAIN_TIMER_TAR_HIGH0_R
• lp_timer::tar0_high::MAIN_TIMER_TAR_HIGH0_W
• lp_timer::tar0_high::R
• lp_timer::tar0_high::W
• lp_timer::tar0_low::MAIN_TIMER_TAR_LOW0_R
• lp_timer::tar0_low::MAIN_TIMER_TAR_LOW0_W
• lp_timer::tar0_low::R
• lp_timer::tar0_low::W
• lp_timer::tar1_high::MAIN_TIMER_TAR_EN1_W
• lp_timer::tar1_high::MAIN_TIMER_TAR_HIGH1_R
• lp_timer::tar1_high::MAIN_TIMER_TAR_HIGH1_W
• lp_timer::tar1_high::R
• lp_timer::tar1_high::W
• lp_timer::tar1_low::MAIN_TIMER_TAR_LOW1_R
• lp_timer::tar1_low::MAIN_TIMER_TAR_LOW1_W
• lp_timer::tar1_low::R
• lp_timer::tar1_low::W
• lp_timer::update::MAIN_TIMER_SYS_RST_R
• lp_timer::update::MAIN_TIMER_SYS_RST_W
• lp_timer::update::MAIN_TIMER_SYS_STALL_R
• lp_timer::update::MAIN_TIMER_SYS_STALL_W
• lp_timer::update::MAIN_TIMER_UPDATE_W
• lp_timer::update::MAIN_TIMER_XTAL_OFF_R
• lp_timer::update::MAIN_TIMER_XTAL_OFF_W
• lp_timer::update::R
• lp_timer::update::W
• lp_uart::AFIFO_STATUS
• lp_uart::AT_CMD_CHAR
• lp_uart::AT_CMD_GAPTOUT
• lp_uart::AT_CMD_POSTCNT
• lp_uart::AT_CMD_PRECNT
• lp_uart::CLKDIV
• lp_uart::CLK_CONF
• lp_uart::CONF0
• lp_uart::CONF1
• lp_uart::DATE
• lp_uart::FIFO
• lp_uart::FSM_STATUS
• lp_uart::HWFC_CONF
• lp_uart::ID
• lp_uart::IDLE_CONF
• lp_uart::INT_CLR
• lp_uart::INT_ENA
• lp_uart::INT_RAW
• lp_uart::INT_ST
• lp_uart::MEM_CONF
• lp_uart::MEM_RX_STATUS
• lp_uart::MEM_TX_STATUS
• lp_uart::REG_UPDATE
• lp_uart::RS485_CONF
• lp_uart::RX_FILT
• lp_uart::SLEEP_CONF0
• lp_uart::SLEEP_CONF1
• lp_uart::SLEEP_CONF2
• lp_uart::STATUS
• lp_uart::SWFC_CONF0
• lp_uart::SWFC_CONF1
• lp_uart::TOUT_CONF
• lp_uart::TXBRK_CONF
• lp_uart::afifo_status::R
• lp_uart::afifo_status::RX_AFIFO_EMPTY_R
• lp_uart::afifo_status::RX_AFIFO_FULL_R
• lp_uart::afifo_status::TX_AFIFO_EMPTY_R
• lp_uart::afifo_status::TX_AFIFO_FULL_R
• lp_uart::at_cmd_char::AT_CMD_CHAR_R
• lp_uart::at_cmd_char::AT_CMD_CHAR_W
• lp_uart::at_cmd_char::CHAR_NUM_R
• lp_uart::at_cmd_char::CHAR_NUM_W
• lp_uart::at_cmd_char::R
• lp_uart::at_cmd_char::W
• lp_uart::at_cmd_gaptout::R
• lp_uart::at_cmd_gaptout::RX_GAP_TOUT_R
• lp_uart::at_cmd_gaptout::RX_GAP_TOUT_W
• lp_uart::at_cmd_gaptout::W
• lp_uart::at_cmd_postcnt::POST_IDLE_NUM_R
• lp_uart::at_cmd_postcnt::POST_IDLE_NUM_W
• lp_uart::at_cmd_postcnt::R
• lp_uart::at_cmd_postcnt::W
• lp_uart::at_cmd_precnt::PRE_IDLE_NUM_R
• lp_uart::at_cmd_precnt::PRE_IDLE_NUM_W
• lp_uart::at_cmd_precnt::R
• lp_uart::at_cmd_precnt::W
• lp_uart::clk_conf::R
• lp_uart::clk_conf::RST_CORE_R
• lp_uart::clk_conf::RST_CORE_W
• lp_uart::clk_conf::RX_RST_CORE_R
• lp_uart::clk_conf::RX_RST_CORE_W
• lp_uart::clk_conf::RX_SCLK_EN_R
• lp_uart::clk_conf::RX_SCLK_EN_W
• lp_uart::clk_conf::SCLK_DIV_A_R
• lp_uart::clk_conf::SCLK_DIV_A_W
• lp_uart::clk_conf::SCLK_DIV_B_R
• lp_uart::clk_conf::SCLK_DIV_B_W
• lp_uart::clk_conf::SCLK_DIV_NUM_R
• lp_uart::clk_conf::SCLK_DIV_NUM_W
• lp_uart::clk_conf::SCLK_EN_R
• lp_uart::clk_conf::SCLK_EN_W
• lp_uart::clk_conf::SCLK_SEL_R
• lp_uart::clk_conf::SCLK_SEL_W
• lp_uart::clk_conf::TX_RST_CORE_R
• lp_uart::clk_conf::TX_RST_CORE_W
• lp_uart::clk_conf::TX_SCLK_EN_R
• lp_uart::clk_conf::TX_SCLK_EN_W
• lp_uart::clk_conf::W
• lp_uart::clkdiv::CLKDIV_R
• lp_uart::clkdiv::CLKDIV_W
• lp_uart::clkdiv::FRAG_R
• lp_uart::clkdiv::FRAG_W
• lp_uart::clkdiv::R
• lp_uart::clkdiv::W
• lp_uart::conf0::BIT_NUM_R
• lp_uart::conf0::BIT_NUM_W
• lp_uart::conf0::DIS_RX_DAT_OVF_R
• lp_uart::conf0::DIS_RX_DAT_OVF_W
• lp_uart::conf0::ERR_WR_MASK_R
• lp_uart::conf0::ERR_WR_MASK_W
• lp_uart::conf0::LOOPBACK_R
• lp_uart::conf0::LOOPBACK_W
• lp_uart::conf0::MEM_CLK_EN_R
• lp_uart::conf0::MEM_CLK_EN_W
• lp_uart::conf0::PARITY_EN_R
• lp_uart::conf0::PARITY_EN_W
• lp_uart::conf0::PARITY_R
• lp_uart::conf0::PARITY_W
• lp_uart::conf0::R
• lp_uart::conf0::RXD_INV_R
• lp_uart::conf0::RXD_INV_W
• lp_uart::conf0::RXFIFO_RST_R
• lp_uart::conf0::RXFIFO_RST_W
• lp_uart::conf0::STOP_BIT_NUM_R
• lp_uart::conf0::STOP_BIT_NUM_W
• lp_uart::conf0::SW_RTS_R
• lp_uart::conf0::SW_RTS_W
• lp_uart::conf0::TXD_BRK_R
• lp_uart::conf0::TXD_BRK_W
• lp_uart::conf0::TXD_INV_R
• lp_uart::conf0::TXD_INV_W
• lp_uart::conf0::TXFIFO_RST_R
• lp_uart::conf0::TXFIFO_RST_W
• lp_uart::conf0::TX_FLOW_EN_R
• lp_uart::conf0::TX_FLOW_EN_W
• lp_uart::conf0::W
• lp_uart::conf1::CLK_EN_R
• lp_uart::conf1::CLK_EN_W
• lp_uart::conf1::CTS_INV_R
• lp_uart::conf1::CTS_INV_W
• lp_uart::conf1::DSR_INV_R
• lp_uart::conf1::DSR_INV_W
• lp_uart::conf1::DTR_INV_R
• lp_uart::conf1::DTR_INV_W
• lp_uart::conf1::R
• lp_uart::conf1::RTS_INV_R
• lp_uart::conf1::RTS_INV_W
• lp_uart::conf1::RXFIFO_FULL_THRHD_R
• lp_uart::conf1::RXFIFO_FULL_THRHD_W
• lp_uart::conf1::SW_DTR_R
• lp_uart::conf1::SW_DTR_W
• lp_uart::conf1::TXFIFO_EMPTY_THRHD_R
• lp_uart::conf1::TXFIFO_EMPTY_THRHD_W
• lp_uart::conf1::W
• lp_uart::date::DATE_R
• lp_uart::date::DATE_W
• lp_uart::date::R
• lp_uart::date::W
• lp_uart::fifo::R
• lp_uart::fifo::RXFIFO_RD_BYTE_R
• lp_uart::fifo::RXFIFO_RD_BYTE_W
• lp_uart::fifo::W
• lp_uart::fsm_status::R
• lp_uart::fsm_status::ST_URX_OUT_R
• lp_uart::fsm_status::ST_UTX_OUT_R
• lp_uart::hwfc_conf::R
• lp_uart::hwfc_conf::RX_FLOW_EN_R
• lp_uart::hwfc_conf::RX_FLOW_EN_W
• lp_uart::hwfc_conf::RX_FLOW_THRHD_R
• lp_uart::hwfc_conf::RX_FLOW_THRHD_W
• lp_uart::hwfc_conf::W
• lp_uart::id::ID_R
• lp_uart::id::ID_W
• lp_uart::id::R
• lp_uart::id::W
• lp_uart::idle_conf::R
• lp_uart::idle_conf::RX_IDLE_THRHD_R
• lp_uart::idle_conf::RX_IDLE_THRHD_W
• lp_uart::idle_conf::TX_IDLE_NUM_R
• lp_uart::idle_conf::TX_IDLE_NUM_W
• lp_uart::idle_conf::W
• lp_uart::int_clr::AT_CMD_CHAR_DET_W
• lp_uart::int_clr::BRK_DET_W
• lp_uart::int_clr::CTS_CHG_W
• lp_uart::int_clr::DSR_CHG_W
• lp_uart::int_clr::FRM_ERR_W
• lp_uart::int_clr::GLITCH_DET_W
• lp_uart::int_clr::PARITY_ERR_W
• lp_uart::int_clr::RXFIFO_FULL_W
• lp_uart::int_clr::RXFIFO_OVF_W
• lp_uart::int_clr::RXFIFO_TOUT_W
• lp_uart::int_clr::SW_XOFF_W
• lp_uart::int_clr::SW_XON_W
• lp_uart::int_clr::TXFIFO_EMPTY_W
• lp_uart::int_clr::TX_BRK_DONE_W
• lp_uart::int_clr::TX_BRK_IDLE_DONE_W
• lp_uart::int_clr::TX_DONE_W
• lp_uart::int_clr::W
• lp_uart::int_clr::WAKEUP_W
• lp_uart::int_ena::AT_CMD_CHAR_DET_R
• lp_uart::int_ena::AT_CMD_CHAR_DET_W
• lp_uart::int_ena::BRK_DET_R
• lp_uart::int_ena::BRK_DET_W
• lp_uart::int_ena::CTS_CHG_R
• lp_uart::int_ena::CTS_CHG_W
• lp_uart::int_ena::DSR_CHG_R
• lp_uart::int_ena::DSR_CHG_W
• lp_uart::int_ena::FRM_ERR_R
• lp_uart::int_ena::FRM_ERR_W
• lp_uart::int_ena::GLITCH_DET_R
• lp_uart::int_ena::GLITCH_DET_W
• lp_uart::int_ena::PARITY_ERR_R
• lp_uart::int_ena::PARITY_ERR_W
• lp_uart::int_ena::R
• lp_uart::int_ena::RXFIFO_FULL_R
• lp_uart::int_ena::RXFIFO_FULL_W
• lp_uart::int_ena::RXFIFO_OVF_R
• lp_uart::int_ena::RXFIFO_OVF_W
• lp_uart::int_ena::RXFIFO_TOUT_R
• lp_uart::int_ena::RXFIFO_TOUT_W
• lp_uart::int_ena::SW_XOFF_R
• lp_uart::int_ena::SW_XOFF_W
• lp_uart::int_ena::SW_XON_R
• lp_uart::int_ena::SW_XON_W
• lp_uart::int_ena::TXFIFO_EMPTY_R
• lp_uart::int_ena::TXFIFO_EMPTY_W
• lp_uart::int_ena::TX_BRK_DONE_R
• lp_uart::int_ena::TX_BRK_DONE_W
• lp_uart::int_ena::TX_BRK_IDLE_DONE_R
• lp_uart::int_ena::TX_BRK_IDLE_DONE_W
• lp_uart::int_ena::TX_DONE_R
• lp_uart::int_ena::TX_DONE_W
• lp_uart::int_ena::W
• lp_uart::int_ena::WAKEUP_R
• lp_uart::int_ena::WAKEUP_W
• lp_uart::int_raw::AT_CMD_CHAR_DET_R
• lp_uart::int_raw::AT_CMD_CHAR_DET_W
• lp_uart::int_raw::BRK_DET_R
• lp_uart::int_raw::BRK_DET_W
• lp_uart::int_raw::CTS_CHG_R
• lp_uart::int_raw::CTS_CHG_W
• lp_uart::int_raw::DSR_CHG_R
• lp_uart::int_raw::DSR_CHG_W
• lp_uart::int_raw::FRM_ERR_R
• lp_uart::int_raw::FRM_ERR_W
• lp_uart::int_raw::GLITCH_DET_R
• lp_uart::int_raw::GLITCH_DET_W
• lp_uart::int_raw::PARITY_ERR_R
• lp_uart::int_raw::PARITY_ERR_W
• lp_uart::int_raw::R
• lp_uart::int_raw::RXFIFO_FULL_R
• lp_uart::int_raw::RXFIFO_FULL_W
• lp_uart::int_raw::RXFIFO_OVF_R
• lp_uart::int_raw::RXFIFO_OVF_W
• lp_uart::int_raw::RXFIFO_TOUT_R
• lp_uart::int_raw::RXFIFO_TOUT_W
• lp_uart::int_raw::SW_XOFF_R
• lp_uart::int_raw::SW_XOFF_W
• lp_uart::int_raw::SW_XON_R
• lp_uart::int_raw::SW_XON_W
• lp_uart::int_raw::TXFIFO_EMPTY_R
• lp_uart::int_raw::TXFIFO_EMPTY_W
• lp_uart::int_raw::TX_BRK_DONE_R
• lp_uart::int_raw::TX_BRK_DONE_W
• lp_uart::int_raw::TX_BRK_IDLE_DONE_R
• lp_uart::int_raw::TX_BRK_IDLE_DONE_W
• lp_uart::int_raw::TX_DONE_R
• lp_uart::int_raw::TX_DONE_W
• lp_uart::int_raw::W
• lp_uart::int_raw::WAKEUP_R
• lp_uart::int_raw::WAKEUP_W
• lp_uart::int_st::AT_CMD_CHAR_DET_R
• lp_uart::int_st::BRK_DET_R
• lp_uart::int_st::CTS_CHG_R
• lp_uart::int_st::DSR_CHG_R
• lp_uart::int_st::FRM_ERR_R
• lp_uart::int_st::GLITCH_DET_R
• lp_uart::int_st::PARITY_ERR_R
• lp_uart::int_st::R
• lp_uart::int_st::RXFIFO_FULL_R
• lp_uart::int_st::RXFIFO_OVF_R
• lp_uart::int_st::RXFIFO_TOUT_R
• lp_uart::int_st::SW_XOFF_R
• lp_uart::int_st::SW_XON_R
• lp_uart::int_st::TXFIFO_EMPTY_R
• lp_uart::int_st::TX_BRK_DONE_R
• lp_uart::int_st::TX_BRK_IDLE_DONE_R
• lp_uart::int_st::TX_DONE_R
• lp_uart::int_st::WAKEUP_R
• lp_uart::mem_conf::MEM_FORCE_PD_R
• lp_uart::mem_conf::MEM_FORCE_PD_W
• lp_uart::mem_conf::MEM_FORCE_PU_R
• lp_uart::mem_conf::MEM_FORCE_PU_W
• lp_uart::mem_conf::R
• lp_uart::mem_conf::W
• lp_uart::mem_rx_status::R
• lp_uart::mem_rx_status::RX_SRAM_RADDR_R
• lp_uart::mem_rx_status::RX_SRAM_WADDR_R
• lp_uart::mem_tx_status::R
• lp_uart::mem_tx_status::TX_SRAM_RADDR_R
• lp_uart::mem_tx_status::TX_SRAM_WADDR_R
• lp_uart::reg_update::R
• lp_uart::reg_update::REG_UPDATE_R
• lp_uart::reg_update::REG_UPDATE_W
• lp_uart::reg_update::W
• lp_uart::rs485_conf::DL0_EN_R
• lp_uart::rs485_conf::DL0_EN_W
• lp_uart::rs485_conf::DL1_EN_R
• lp_uart::rs485_conf::DL1_EN_W
• lp_uart::rs485_conf::R
• lp_uart::rs485_conf::W
• lp_uart::rx_filt::GLITCH_FILT_EN_R
• lp_uart::rx_filt::GLITCH_FILT_EN_W
• lp_uart::rx_filt::GLITCH_FILT_R
• lp_uart::rx_filt::GLITCH_FILT_W
• lp_uart::rx_filt::R
• lp_uart::rx_filt::W
• lp_uart::sleep_conf0::R
• lp_uart::sleep_conf0::W
• lp_uart::sleep_conf0::WK_CHAR1_R
• lp_uart::sleep_conf0::WK_CHAR1_W
• lp_uart::sleep_conf0::WK_CHAR2_R
• lp_uart::sleep_conf0::WK_CHAR2_W
• lp_uart::sleep_conf0::WK_CHAR3_R
• lp_uart::sleep_conf0::WK_CHAR3_W
• lp_uart::sleep_conf0::WK_CHAR4_R
• lp_uart::sleep_conf0::WK_CHAR4_W
• lp_uart::sleep_conf1::R
• lp_uart::sleep_conf1::W
• lp_uart::sleep_conf1::WK_CHAR0_R
• lp_uart::sleep_conf1::WK_CHAR0_W
• lp_uart::sleep_conf2::ACTIVE_THRESHOLD_R
• lp_uart::sleep_conf2::ACTIVE_THRESHOLD_W
• lp_uart::sleep_conf2::R
• lp_uart::sleep_conf2::RX_WAKE_UP_THRHD_R
• lp_uart::sleep_conf2::RX_WAKE_UP_THRHD_W
• lp_uart::sleep_conf2::W
• lp_uart::sleep_conf2::WK_CHAR_MASK_R
• lp_uart::sleep_conf2::WK_CHAR_MASK_W
• lp_uart::sleep_conf2::WK_CHAR_NUM_R
• lp_uart::sleep_conf2::WK_CHAR_NUM_W
• lp_uart::sleep_conf2::WK_MODE_SEL_R
• lp_uart::sleep_conf2::WK_MODE_SEL_W
• lp_uart::status::CTSN_R
• lp_uart::status::DSRN_R
• lp_uart::status::DTRN_R
• lp_uart::status::R
• lp_uart::status::RTSN_R
• lp_uart::status::RXD_R
• lp_uart::status::RXFIFO_CNT_R
• lp_uart::status::TXD_R
• lp_uart::status::TXFIFO_CNT_R
• lp_uart::swfc_conf0::FORCE_XOFF_R
• lp_uart::swfc_conf0::FORCE_XOFF_W
• lp_uart::swfc_conf0::FORCE_XON_R
• lp_uart::swfc_conf0::FORCE_XON_W
• lp_uart::swfc_conf0::R
• lp_uart::swfc_conf0::SEND_XOFF_R
• lp_uart::swfc_conf0::SEND_XOFF_W
• lp_uart::swfc_conf0::SEND_XON_R
• lp_uart::swfc_conf0::SEND_XON_W
• lp_uart::swfc_conf0::SW_FLOW_CON_EN_R
• lp_uart::swfc_conf0::SW_FLOW_CON_EN_W
• lp_uart::swfc_conf0::W
• lp_uart::swfc_conf0::XOFF_CHAR_R
• lp_uart::swfc_conf0::XOFF_CHAR_W
• lp_uart::swfc_conf0::XONOFF_DEL_R
• lp_uart::swfc_conf0::XONOFF_DEL_W
• lp_uart::swfc_conf0::XON_CHAR_R
• lp_uart::swfc_conf0::XON_CHAR_W
• lp_uart::swfc_conf0::XON_XOFF_STILL_SEND_R
• lp_uart::swfc_conf0::XON_XOFF_STILL_SEND_W
• lp_uart::swfc_conf1::R
• lp_uart::swfc_conf1::W
• lp_uart::swfc_conf1::XOFF_THRESHOLD_R
• lp_uart::swfc_conf1::XOFF_THRESHOLD_W
• lp_uart::swfc_conf1::XON_THRESHOLD_R
• lp_uart::swfc_conf1::XON_THRESHOLD_W
• lp_uart::tout_conf::R
• lp_uart::tout_conf::RX_TOUT_EN_R
• lp_uart::tout_conf::RX_TOUT_EN_W
• lp_uart::tout_conf::RX_TOUT_FLOW_DIS_R
• lp_uart::tout_conf::RX_TOUT_FLOW_DIS_W
• lp_uart::tout_conf::RX_TOUT_THRHD_R
• lp_uart::tout_conf::RX_TOUT_THRHD_W
• lp_uart::tout_conf::W
• lp_uart::txbrk_conf::R
• lp_uart::txbrk_conf::TX_BRK_NUM_R
• lp_uart::txbrk_conf::TX_BRK_NUM_W
• lp_uart::txbrk_conf::W
• lp_wdt::CONFIG1
• lp_wdt::CONFIG2
• lp_wdt::CONFIG3
• lp_wdt::CONFIG4
• lp_wdt::DATE
• lp_wdt::INT_CLR
• lp_wdt::INT_ENA
• lp_wdt::INT_RAW
• lp_wdt::INT_ST
• lp_wdt::SWD_CONF
• lp_wdt::SWD_WPROTECT
• lp_wdt::WDTCONFIG0
• lp_wdt::WDTFEED
• lp_wdt::WDTWPROTECT
• lp_wdt::config1::R
• lp_wdt::config1::W
• lp_wdt::config1::WDT_STG0_HOLD_R
• lp_wdt::config1::WDT_STG0_HOLD_W
• lp_wdt::config2::R
• lp_wdt::config2::W
• lp_wdt::config2::WDT_STG1_HOLD_R
• lp_wdt::config2::WDT_STG1_HOLD_W
• lp_wdt::config3::R
• lp_wdt::config3::W
• lp_wdt::config3::WDT_STG2_HOLD_R
• lp_wdt::config3::WDT_STG2_HOLD_W
• lp_wdt::config4::R
• lp_wdt::config4::W
• lp_wdt::config4::WDT_STG3_HOLD_R
• lp_wdt::config4::WDT_STG3_HOLD_W
• lp_wdt::date::CLK_EN_R
• lp_wdt::date::CLK_EN_W
• lp_wdt::date::LP_WDT_DATE_R
• lp_wdt::date::LP_WDT_DATE_W
• lp_wdt::date::R
• lp_wdt::date::W
• lp_wdt::int_clr::SUPER_WDT_W
• lp_wdt::int_clr::W
• lp_wdt::int_clr::WDT_W
• lp_wdt::int_ena::R
• lp_wdt::int_ena::SUPER_WDT_R
• lp_wdt::int_ena::SUPER_WDT_W
• lp_wdt::int_ena::W
• lp_wdt::int_ena::WDT_R
• lp_wdt::int_ena::WDT_W
• lp_wdt::int_raw::LP_WDT_R
• lp_wdt::int_raw::LP_WDT_W
• lp_wdt::int_raw::R
• lp_wdt::int_raw::SUPER_WDT_R
• lp_wdt::int_raw::SUPER_WDT_W
• lp_wdt::int_raw::W
• lp_wdt::int_st::R
• lp_wdt::int_st::SUPER_WDT_R
• lp_wdt::int_st::WDT_R
• lp_wdt::swd_conf::R
• lp_wdt::swd_conf::SWD_AUTO_FEED_EN_R
• lp_wdt::swd_conf::SWD_AUTO_FEED_EN_W
• lp_wdt::swd_conf::SWD_DISABLE_R
• lp_wdt::swd_conf::SWD_DISABLE_W
• lp_wdt::swd_conf::SWD_FEED_W
• lp_wdt::swd_conf::SWD_RESET_FLAG_R
• lp_wdt::swd_conf::SWD_RST_FLAG_CLR_W
• lp_wdt::swd_conf::SWD_SIGNAL_WIDTH_R
• lp_wdt::swd_conf::SWD_SIGNAL_WIDTH_W
• lp_wdt::swd_conf::W
• lp_wdt::swd_wprotect::R
• lp_wdt::swd_wprotect::SWD_WKEY_R
• lp_wdt::swd_wprotect::SWD_WKEY_W
• lp_wdt::swd_wprotect::W
• lp_wdt::wdtconfig0::R
• lp_wdt::wdtconfig0::W
• lp_wdt::wdtconfig0::WDT_APPCPU_RESET_EN_R
• lp_wdt::wdtconfig0::WDT_APPCPU_RESET_EN_W
• lp_wdt::wdtconfig0::WDT_CHIP_RESET_EN_R
• lp_wdt::wdtconfig0::WDT_CHIP_RESET_EN_W
• lp_wdt::wdtconfig0::WDT_CHIP_RESET_WIDTH_R
• lp_wdt::wdtconfig0::WDT_CHIP_RESET_WIDTH_W
• lp_wdt::wdtconfig0::WDT_CPU_RESET_LENGTH_R
• lp_wdt::wdtconfig0::WDT_CPU_RESET_LENGTH_W
• lp_wdt::wdtconfig0::WDT_EN_R
• lp_wdt::wdtconfig0::WDT_EN_W
• lp_wdt::wdtconfig0::WDT_FLASHBOOT_MOD_EN_R
• lp_wdt::wdtconfig0::WDT_FLASHBOOT_MOD_EN_W
• lp_wdt::wdtconfig0::WDT_PAUSE_IN_SLP_R
• lp_wdt::wdtconfig0::WDT_PAUSE_IN_SLP_W
• lp_wdt::wdtconfig0::WDT_PROCPU_RESET_EN_R
• lp_wdt::wdtconfig0::WDT_PROCPU_RESET_EN_W
• lp_wdt::wdtconfig0::WDT_STG0_R
• lp_wdt::wdtconfig0::WDT_STG0_W
• lp_wdt::wdtconfig0::WDT_STG1_R
• lp_wdt::wdtconfig0::WDT_STG1_W
• lp_wdt::wdtconfig0::WDT_STG2_R
• lp_wdt::wdtconfig0::WDT_STG2_W
• lp_wdt::wdtconfig0::WDT_STG3_R
• lp_wdt::wdtconfig0::WDT_STG3_W
• lp_wdt::wdtconfig0::WDT_SYS_RESET_LENGTH_R
• lp_wdt::wdtconfig0::WDT_SYS_RESET_LENGTH_W
• lp_wdt::wdtfeed::W
• lp_wdt::wdtfeed::WDT_FEED_W
• lp_wdt::wdtwprotect::R
• lp_wdt::wdtwprotect::W
• lp_wdt::wdtwprotect::WDT_WKEY_R
• lp_wdt::wdtwprotect::WDT_WKEY_W
• mcpwm0::CAP_CH
• mcpwm0::CAP_CH_CFG
• mcpwm0::CAP_STATUS
• mcpwm0::CAP_TIMER_CFG
• mcpwm0::CAP_TIMER_PHASE
• mcpwm0::CLK
• mcpwm0::CLK_CFG
• mcpwm0::EVT_EN
• mcpwm0::FAULT_DETECT
• mcpwm0::INT_CLR
• mcpwm0::INT_ENA
• mcpwm0::INT_RAW
• mcpwm0::INT_ST
• mcpwm0::OPERATOR_TIMERSEL
• mcpwm0::TASK_EN
• mcpwm0::TIMER_SYNCI_CFG
• mcpwm0::UPDATE_CFG
• mcpwm0::VERSION
• mcpwm0::cap_ch::R
• mcpwm0::cap_ch::VALUE_R
• mcpwm0::cap_ch_cfg::EN_R
• mcpwm0::cap_ch_cfg::EN_W
• mcpwm0::cap_ch_cfg::IN_INVERT_R
• mcpwm0::cap_ch_cfg::IN_INVERT_W
• mcpwm0::cap_ch_cfg::MODE_R
• mcpwm0::cap_ch_cfg::MODE_W
• mcpwm0::cap_ch_cfg::PRESCALE_R
• mcpwm0::cap_ch_cfg::PRESCALE_W
• mcpwm0::cap_ch_cfg::R
• mcpwm0::cap_ch_cfg::SW_W
• mcpwm0::cap_ch_cfg::W
• mcpwm0::cap_status::CAP0_EDGE_R
• mcpwm0::cap_status::CAP1_EDGE_R
• mcpwm0::cap_status::CAP2_EDGE_R
• mcpwm0::cap_status::R
• mcpwm0::cap_timer_cfg::CAP_SYNCI_EN_R
• mcpwm0::cap_timer_cfg::CAP_SYNCI_EN_W
• mcpwm0::cap_timer_cfg::CAP_SYNCI_SEL_R
• mcpwm0::cap_timer_cfg::CAP_SYNCI_SEL_W
• mcpwm0::cap_timer_cfg::CAP_SYNC_SW_W
• mcpwm0::cap_timer_cfg::CAP_TIMER_EN_R
• mcpwm0::cap_timer_cfg::CAP_TIMER_EN_W
• mcpwm0::cap_timer_cfg::R
• mcpwm0::cap_timer_cfg::W
• mcpwm0::cap_timer_phase::CAP_PHASE_R
• mcpwm0::cap_timer_phase::CAP_PHASE_W
• mcpwm0::cap_timer_phase::R
• mcpwm0::cap_timer_phase::W
• mcpwm0::ch::CARRIER_CFG
• mcpwm0::ch::DT_CFG
• mcpwm0::ch::DT_FED_CFG
• mcpwm0::ch::DT_RED_CFG
• mcpwm0::ch::FH_CFG0
• mcpwm0::ch::FH_CFG1
• mcpwm0::ch::FH_STATUS
• mcpwm0::ch::GEN
• mcpwm0::ch::GEN_CFG0
• mcpwm0::ch::GEN_FORCE
• mcpwm0::ch::GEN_STMP_CFG
• mcpwm0::ch::GEN_TSTMP_A
• mcpwm0::ch::GEN_TSTMP_B
• mcpwm0::ch::carrier_cfg::DUTY_R
• mcpwm0::ch::carrier_cfg::DUTY_W
• mcpwm0::ch::carrier_cfg::EN_R
• mcpwm0::ch::carrier_cfg::EN_W
• mcpwm0::ch::carrier_cfg::IN_INVERT_R
• mcpwm0::ch::carrier_cfg::IN_INVERT_W
• mcpwm0::ch::carrier_cfg::OSHTWTH_R
• mcpwm0::ch::carrier_cfg::OSHTWTH_W
• mcpwm0::ch::carrier_cfg::OUT_INVERT_R
• mcpwm0::ch::carrier_cfg::OUT_INVERT_W
• mcpwm0::ch::carrier_cfg::PRESCALE_R
• mcpwm0::ch::carrier_cfg::PRESCALE_W
• mcpwm0::ch::carrier_cfg::R
• mcpwm0::ch::carrier_cfg::W
• mcpwm0::ch::dt_cfg::A_OUTBYPASS_R
• mcpwm0::ch::dt_cfg::A_OUTBYPASS_W
• mcpwm0::ch::dt_cfg::A_OUTSWAP_R
• mcpwm0::ch::dt_cfg::A_OUTSWAP_W
• mcpwm0::ch::dt_cfg::B_OUTBYPASS_R
• mcpwm0::ch::dt_cfg::B_OUTBYPASS_W
• mcpwm0::ch::dt_cfg::B_OUTSWAP_R
• mcpwm0::ch::dt_cfg::B_OUTSWAP_W
• mcpwm0::ch::dt_cfg::CLK_SEL_R
• mcpwm0::ch::dt_cfg::CLK_SEL_W
• mcpwm0::ch::dt_cfg::DEB_MODE_R
• mcpwm0::ch::dt_cfg::DEB_MODE_W
• mcpwm0::ch::dt_cfg::FED_INSEL_R
• mcpwm0::ch::dt_cfg::FED_INSEL_W
• mcpwm0::ch::dt_cfg::FED_OUTINVERT_R
• mcpwm0::ch::dt_cfg::FED_OUTINVERT_W
• mcpwm0::ch::dt_cfg::FED_UPMETHOD_R
• mcpwm0::ch::dt_cfg::FED_UPMETHOD_W
• mcpwm0::ch::dt_cfg::R
• mcpwm0::ch::dt_cfg::RED_INSEL_R
• mcpwm0::ch::dt_cfg::RED_INSEL_W
• mcpwm0::ch::dt_cfg::RED_OUTINVERT_R
• mcpwm0::ch::dt_cfg::RED_OUTINVERT_W
• mcpwm0::ch::dt_cfg::RED_UPMETHOD_R
• mcpwm0::ch::dt_cfg::RED_UPMETHOD_W
• mcpwm0::ch::dt_cfg::W
• mcpwm0::ch::dt_fed_cfg::FED_R
• mcpwm0::ch::dt_fed_cfg::FED_W
• mcpwm0::ch::dt_fed_cfg::R
• mcpwm0::ch::dt_fed_cfg::W
• mcpwm0::ch::dt_red_cfg::R
• mcpwm0::ch::dt_red_cfg::RED_R
• mcpwm0::ch::dt_red_cfg::RED_W
• mcpwm0::ch::dt_red_cfg::W
• mcpwm0::ch::fh_cfg0::A_CBC_D_R
• mcpwm0::ch::fh_cfg0::A_CBC_D_W
• mcpwm0::ch::fh_cfg0::A_CBC_U_R
• mcpwm0::ch::fh_cfg0::A_CBC_U_W
• mcpwm0::ch::fh_cfg0::A_OST_D_R
• mcpwm0::ch::fh_cfg0::A_OST_D_W
• mcpwm0::ch::fh_cfg0::A_OST_U_R
• mcpwm0::ch::fh_cfg0::A_OST_U_W
• mcpwm0::ch::fh_cfg0::B_CBC_D_R
• mcpwm0::ch::fh_cfg0::B_CBC_D_W
• mcpwm0::ch::fh_cfg0::B_CBC_U_R
• mcpwm0::ch::fh_cfg0::B_CBC_U_W
• mcpwm0::ch::fh_cfg0::B_OST_D_R
• mcpwm0::ch::fh_cfg0::B_OST_D_W
• mcpwm0::ch::fh_cfg0::B_OST_U_R
• mcpwm0::ch::fh_cfg0::B_OST_U_W
• mcpwm0::ch::fh_cfg0::F0_CBC_R
• mcpwm0::ch::fh_cfg0::F0_CBC_W
• mcpwm0::ch::fh_cfg0::F0_OST_R
• mcpwm0::ch::fh_cfg0::F0_OST_W
• mcpwm0::ch::fh_cfg0::F1_CBC_R
• mcpwm0::ch::fh_cfg0::F1_CBC_W
• mcpwm0::ch::fh_cfg0::F1_OST_R
• mcpwm0::ch::fh_cfg0::F1_OST_W
• mcpwm0::ch::fh_cfg0::F2_CBC_R
• mcpwm0::ch::fh_cfg0::F2_CBC_W
• mcpwm0::ch::fh_cfg0::F2_OST_R
• mcpwm0::ch::fh_cfg0::F2_OST_W
• mcpwm0::ch::fh_cfg0::R
• mcpwm0::ch::fh_cfg0::SW_CBC_R
• mcpwm0::ch::fh_cfg0::SW_CBC_W
• mcpwm0::ch::fh_cfg0::SW_OST_R
• mcpwm0::ch::fh_cfg0::SW_OST_W
• mcpwm0::ch::fh_cfg0::W
• mcpwm0::ch::fh_cfg1::CBCPULSE_R
• mcpwm0::ch::fh_cfg1::CBCPULSE_W
• mcpwm0::ch::fh_cfg1::CLR_OST_R
• mcpwm0::ch::fh_cfg1::CLR_OST_W
• mcpwm0::ch::fh_cfg1::FORCE_CBC_R
• mcpwm0::ch::fh_cfg1::FORCE_CBC_W
• mcpwm0::ch::fh_cfg1::FORCE_OST_R
• mcpwm0::ch::fh_cfg1::FORCE_OST_W
• mcpwm0::ch::fh_cfg1::R
• mcpwm0::ch::fh_cfg1::W
• mcpwm0::ch::fh_status::CBC_ON_R
• mcpwm0::ch::fh_status::OST_ON_R
• mcpwm0::ch::fh_status::R
• mcpwm0::ch::gen::DT0_R
• mcpwm0::ch::gen::DT0_W
• mcpwm0::ch::gen::DT1_R
• mcpwm0::ch::gen::DT1_W
• mcpwm0::ch::gen::DTEA_R
• mcpwm0::ch::gen::DTEA_W
• mcpwm0::ch::gen::DTEB_R
• mcpwm0::ch::gen::DTEB_W
• mcpwm0::ch::gen::DTEP_R
• mcpwm0::ch::gen::DTEP_W
• mcpwm0::ch::gen::DTEZ_R
• mcpwm0::ch::gen::DTEZ_W
• mcpwm0::ch::gen::R
• mcpwm0::ch::gen::UT0_R
• mcpwm0::ch::gen::UT0_W
• mcpwm0::ch::gen::UT1_R
• mcpwm0::ch::gen::UT1_W
• mcpwm0::ch::gen::UTEA_R
• mcpwm0::ch::gen::UTEA_W
• mcpwm0::ch::gen::UTEB_R
• mcpwm0::ch::gen::UTEB_W
• mcpwm0::ch::gen::UTEP_R
• mcpwm0::ch::gen::UTEP_W
• mcpwm0::ch::gen::UTEZ_R
• mcpwm0::ch::gen::UTEZ_W
• mcpwm0::ch::gen::W
• mcpwm0::ch::gen_cfg0::CFG_UPMETHOD_R
• mcpwm0::ch::gen_cfg0::CFG_UPMETHOD_W
• mcpwm0::ch::gen_cfg0::R
• mcpwm0::ch::gen_cfg0::T0_SEL_R
• mcpwm0::ch::gen_cfg0::T0_SEL_W
• mcpwm0::ch::gen_cfg0::T1_SEL_R
• mcpwm0::ch::gen_cfg0::T1_SEL_W
• mcpwm0::ch::gen_cfg0::W
• mcpwm0::ch::gen_force::A_CNTUFORCE_MODE_R
• mcpwm0::ch::gen_force::A_CNTUFORCE_MODE_W
• mcpwm0::ch::gen_force::A_NCIFORCE_MODE_R
• mcpwm0::ch::gen_force::A_NCIFORCE_MODE_W
• mcpwm0::ch::gen_force::A_NCIFORCE_R
• mcpwm0::ch::gen_force::A_NCIFORCE_W
• mcpwm0::ch::gen_force::B_CNTUFORCE_MODE_R
• mcpwm0::ch::gen_force::B_CNTUFORCE_MODE_W
• mcpwm0::ch::gen_force::B_NCIFORCE_MODE_R
• mcpwm0::ch::gen_force::B_NCIFORCE_MODE_W
• mcpwm0::ch::gen_force::B_NCIFORCE_R
• mcpwm0::ch::gen_force::B_NCIFORCE_W
• mcpwm0::ch::gen_force::CNTUFORCE_UPMETHOD_R
• mcpwm0::ch::gen_force::CNTUFORCE_UPMETHOD_W
• mcpwm0::ch::gen_force::R
• mcpwm0::ch::gen_force::W
• mcpwm0::ch::gen_stmp_cfg::A_SHDW_FULL_R
• mcpwm0::ch::gen_stmp_cfg::A_SHDW_FULL_W
• mcpwm0::ch::gen_stmp_cfg::A_UPMETHOD_R
• mcpwm0::ch::gen_stmp_cfg::A_UPMETHOD_W
• mcpwm0::ch::gen_stmp_cfg::B_SHDW_FULL_R
• mcpwm0::ch::gen_stmp_cfg::B_SHDW_FULL_W
• mcpwm0::ch::gen_stmp_cfg::B_UPMETHOD_R
• mcpwm0::ch::gen_stmp_cfg::B_UPMETHOD_W
• mcpwm0::ch::gen_stmp_cfg::R
• mcpwm0::ch::gen_stmp_cfg::W
• mcpwm0::ch::gen_tstmp_a::A_R
• mcpwm0::ch::gen_tstmp_a::A_W
• mcpwm0::ch::gen_tstmp_a::R
• mcpwm0::ch::gen_tstmp_a::W
• mcpwm0::ch::gen_tstmp_b::B_R
• mcpwm0::ch::gen_tstmp_b::B_W
• mcpwm0::ch::gen_tstmp_b::R
• mcpwm0::ch::gen_tstmp_b::W
• mcpwm0::clk::EN_R
• mcpwm0::clk::EN_W
• mcpwm0::clk::R
• mcpwm0::clk::W
• mcpwm0::clk_cfg::CLK_PRESCALE_R
• mcpwm0::clk_cfg::CLK_PRESCALE_W
• mcpwm0::clk_cfg::R
• mcpwm0::clk_cfg::W
• mcpwm0::evt_en::EVT_CAP0_EN_R
• mcpwm0::evt_en::EVT_CAP0_EN_W
• mcpwm0::evt_en::EVT_CAP1_EN_R
• mcpwm0::evt_en::EVT_CAP1_EN_W
• mcpwm0::evt_en::EVT_CAP2_EN_R
• mcpwm0::evt_en::EVT_CAP2_EN_W
• mcpwm0::evt_en::EVT_F0_CLR_EN_R
• mcpwm0::evt_en::EVT_F0_CLR_EN_W
• mcpwm0::evt_en::EVT_F0_EN_R
• mcpwm0::evt_en::EVT_F0_EN_W
• mcpwm0::evt_en::EVT_F1_CLR_EN_R
• mcpwm0::evt_en::EVT_F1_CLR_EN_W
• mcpwm0::evt_en::EVT_F1_EN_R
• mcpwm0::evt_en::EVT_F1_EN_W
• mcpwm0::evt_en::EVT_F2_CLR_EN_R
• mcpwm0::evt_en::EVT_F2_CLR_EN_W
• mcpwm0::evt_en::EVT_F2_EN_R
• mcpwm0::evt_en::EVT_F2_EN_W
• mcpwm0::evt_en::EVT_OP0_TEA_EN_R
• mcpwm0::evt_en::EVT_OP0_TEA_EN_W
• mcpwm0::evt_en::EVT_OP0_TEB_EN_R
• mcpwm0::evt_en::EVT_OP0_TEB_EN_W
• mcpwm0::evt_en::EVT_OP1_TEA_EN_R
• mcpwm0::evt_en::EVT_OP1_TEA_EN_W
• mcpwm0::evt_en::EVT_OP1_TEB_EN_R
• mcpwm0::evt_en::EVT_OP1_TEB_EN_W
• mcpwm0::evt_en::EVT_OP2_TEA_EN_R
• mcpwm0::evt_en::EVT_OP2_TEA_EN_W
• mcpwm0::evt_en::EVT_OP2_TEB_EN_R
• mcpwm0::evt_en::EVT_OP2_TEB_EN_W
• mcpwm0::evt_en::EVT_TIMER0_STOP_EN_R
• mcpwm0::evt_en::EVT_TIMER0_STOP_EN_W
• mcpwm0::evt_en::EVT_TIMER0_TEP_EN_R
• mcpwm0::evt_en::EVT_TIMER0_TEP_EN_W
• mcpwm0::evt_en::EVT_TIMER0_TEZ_EN_R
• mcpwm0::evt_en::EVT_TIMER0_TEZ_EN_W
• mcpwm0::evt_en::EVT_TIMER1_STOP_EN_R
• mcpwm0::evt_en::EVT_TIMER1_STOP_EN_W
• mcpwm0::evt_en::EVT_TIMER1_TEP_EN_R
• mcpwm0::evt_en::EVT_TIMER1_TEP_EN_W
• mcpwm0::evt_en::EVT_TIMER1_TEZ_EN_R
• mcpwm0::evt_en::EVT_TIMER1_TEZ_EN_W
• mcpwm0::evt_en::EVT_TIMER2_STOP_EN_R
• mcpwm0::evt_en::EVT_TIMER2_STOP_EN_W
• mcpwm0::evt_en::EVT_TIMER2_TEP_EN_R
• mcpwm0::evt_en::EVT_TIMER2_TEP_EN_W
• mcpwm0::evt_en::EVT_TIMER2_TEZ_EN_R
• mcpwm0::evt_en::EVT_TIMER2_TEZ_EN_W
• mcpwm0::evt_en::EVT_TZ0_CBC_EN_R
• mcpwm0::evt_en::EVT_TZ0_CBC_EN_W
• mcpwm0::evt_en::EVT_TZ0_OST_EN_R
• mcpwm0::evt_en::EVT_TZ0_OST_EN_W
• mcpwm0::evt_en::EVT_TZ1_CBC_EN_R
• mcpwm0::evt_en::EVT_TZ1_CBC_EN_W
• mcpwm0::evt_en::EVT_TZ1_OST_EN_R
• mcpwm0::evt_en::EVT_TZ1_OST_EN_W
• mcpwm0::evt_en::EVT_TZ2_CBC_EN_R
• mcpwm0::evt_en::EVT_TZ2_CBC_EN_W
• mcpwm0::evt_en::EVT_TZ2_OST_EN_R
• mcpwm0::evt_en::EVT_TZ2_OST_EN_W
• mcpwm0::evt_en::R
• mcpwm0::evt_en::W
• mcpwm0::fault_detect::EVENT_F0_R
• mcpwm0::fault_detect::EVENT_F1_R
• mcpwm0::fault_detect::EVENT_F2_R
• mcpwm0::fault_detect::F0_EN_R
• mcpwm0::fault_detect::F0_EN_W
• mcpwm0::fault_detect::F0_POLE_R
• mcpwm0::fault_detect::F0_POLE_W
• mcpwm0::fault_detect::F1_EN_R
• mcpwm0::fault_detect::F1_EN_W
• mcpwm0::fault_detect::F1_POLE_R
• mcpwm0::fault_detect::F1_POLE_W
• mcpwm0::fault_detect::F2_EN_R
• mcpwm0::fault_detect::F2_EN_W
• mcpwm0::fault_detect::F2_POLE_R
• mcpwm0::fault_detect::F2_POLE_W
• mcpwm0::fault_detect::R
• mcpwm0::fault_detect::W
• mcpwm0::int_clr::CAP0_W
• mcpwm0::int_clr::CAP1_W
• mcpwm0::int_clr::CAP2_W
• mcpwm0::int_clr::CMPR0_TEA_W
• mcpwm0::int_clr::CMPR0_TEB_W
• mcpwm0::int_clr::CMPR1_TEA_W
• mcpwm0::int_clr::CMPR1_TEB_W
• mcpwm0::int_clr::CMPR2_TEA_W
• mcpwm0::int_clr::CMPR2_TEB_W
• mcpwm0::int_clr::FAULT0_CLR_W
• mcpwm0::int_clr::FAULT0_W
• mcpwm0::int_clr::FAULT1_CLR_W
• mcpwm0::int_clr::FAULT1_W
• mcpwm0::int_clr::FAULT2_CLR_W
• mcpwm0::int_clr::FAULT2_W
• mcpwm0::int_clr::TIMER0_STOP_W
• mcpwm0::int_clr::TIMER0_TEP_W
• mcpwm0::int_clr::TIMER0_TEZ_W
• mcpwm0::int_clr::TIMER1_STOP_W
• mcpwm0::int_clr::TIMER1_TEP_W
• mcpwm0::int_clr::TIMER1_TEZ_W
• mcpwm0::int_clr::TIMER2_STOP_W
• mcpwm0::int_clr::TIMER2_TEP_W
• mcpwm0::int_clr::TIMER2_TEZ_W
• mcpwm0::int_clr::TZ0_CBC_W
• mcpwm0::int_clr::TZ0_OST_W
• mcpwm0::int_clr::TZ1_CBC_W
• mcpwm0::int_clr::TZ1_OST_W
• mcpwm0::int_clr::TZ2_CBC_W
• mcpwm0::int_clr::TZ2_OST_W
• mcpwm0::int_clr::W
• mcpwm0::int_ena::CAP0_R
• mcpwm0::int_ena::CAP0_W
• mcpwm0::int_ena::CAP1_R
• mcpwm0::int_ena::CAP1_W
• mcpwm0::int_ena::CAP2_R
• mcpwm0::int_ena::CAP2_W
• mcpwm0::int_ena::CMPR0_TEA_R
• mcpwm0::int_ena::CMPR0_TEA_W
• mcpwm0::int_ena::CMPR0_TEB_R
• mcpwm0::int_ena::CMPR0_TEB_W
• mcpwm0::int_ena::CMPR1_TEA_R
• mcpwm0::int_ena::CMPR1_TEA_W
• mcpwm0::int_ena::CMPR1_TEB_R
• mcpwm0::int_ena::CMPR1_TEB_W
• mcpwm0::int_ena::CMPR2_TEA_R
• mcpwm0::int_ena::CMPR2_TEA_W
• mcpwm0::int_ena::CMPR2_TEB_R
• mcpwm0::int_ena::CMPR2_TEB_W
• mcpwm0::int_ena::FAULT0_CLR_R
• mcpwm0::int_ena::FAULT0_CLR_W
• mcpwm0::int_ena::FAULT0_R
• mcpwm0::int_ena::FAULT0_W
• mcpwm0::int_ena::FAULT1_CLR_R
• mcpwm0::int_ena::FAULT1_CLR_W
• mcpwm0::int_ena::FAULT1_R
• mcpwm0::int_ena::FAULT1_W
• mcpwm0::int_ena::FAULT2_CLR_R
• mcpwm0::int_ena::FAULT2_CLR_W
• mcpwm0::int_ena::FAULT2_R
• mcpwm0::int_ena::FAULT2_W
• mcpwm0::int_ena::R
• mcpwm0::int_ena::TIMER0_STOP_R
• mcpwm0::int_ena::TIMER0_STOP_W
• mcpwm0::int_ena::TIMER0_TEP_R
• mcpwm0::int_ena::TIMER0_TEP_W
• mcpwm0::int_ena::TIMER0_TEZ_R
• mcpwm0::int_ena::TIMER0_TEZ_W
• mcpwm0::int_ena::TIMER1_STOP_R
• mcpwm0::int_ena::TIMER1_STOP_W
• mcpwm0::int_ena::TIMER1_TEP_R
• mcpwm0::int_ena::TIMER1_TEP_W
• mcpwm0::int_ena::TIMER1_TEZ_R
• mcpwm0::int_ena::TIMER1_TEZ_W
• mcpwm0::int_ena::TIMER2_STOP_R
• mcpwm0::int_ena::TIMER2_STOP_W
• mcpwm0::int_ena::TIMER2_TEP_R
• mcpwm0::int_ena::TIMER2_TEP_W
• mcpwm0::int_ena::TIMER2_TEZ_R
• mcpwm0::int_ena::TIMER2_TEZ_W
• mcpwm0::int_ena::TZ0_CBC_R
• mcpwm0::int_ena::TZ0_CBC_W
• mcpwm0::int_ena::TZ0_OST_R
• mcpwm0::int_ena::TZ0_OST_W
• mcpwm0::int_ena::TZ1_CBC_R
• mcpwm0::int_ena::TZ1_CBC_W
• mcpwm0::int_ena::TZ1_OST_R
• mcpwm0::int_ena::TZ1_OST_W
• mcpwm0::int_ena::TZ2_CBC_R
• mcpwm0::int_ena::TZ2_CBC_W
• mcpwm0::int_ena::TZ2_OST_R
• mcpwm0::int_ena::TZ2_OST_W
• mcpwm0::int_ena::W
• mcpwm0::int_raw::CAP0_R
• mcpwm0::int_raw::CAP0_W
• mcpwm0::int_raw::CAP1_R
• mcpwm0::int_raw::CAP1_W
• mcpwm0::int_raw::CAP2_R
• mcpwm0::int_raw::CAP2_W
• mcpwm0::int_raw::CMPR0_TEA_R
• mcpwm0::int_raw::CMPR0_TEA_W
• mcpwm0::int_raw::CMPR0_TEB_R
• mcpwm0::int_raw::CMPR0_TEB_W
• mcpwm0::int_raw::CMPR1_TEA_R
• mcpwm0::int_raw::CMPR1_TEA_W
• mcpwm0::int_raw::CMPR1_TEB_R
• mcpwm0::int_raw::CMPR1_TEB_W
• mcpwm0::int_raw::CMPR2_TEA_R
• mcpwm0::int_raw::CMPR2_TEA_W
• mcpwm0::int_raw::CMPR2_TEB_R
• mcpwm0::int_raw::CMPR2_TEB_W
• mcpwm0::int_raw::FAULT0_CLR_R
• mcpwm0::int_raw::FAULT0_CLR_W
• mcpwm0::int_raw::FAULT0_R
• mcpwm0::int_raw::FAULT0_W
• mcpwm0::int_raw::FAULT1_CLR_R
• mcpwm0::int_raw::FAULT1_CLR_W
• mcpwm0::int_raw::FAULT1_R
• mcpwm0::int_raw::FAULT1_W
• mcpwm0::int_raw::FAULT2_CLR_R
• mcpwm0::int_raw::FAULT2_CLR_W
• mcpwm0::int_raw::FAULT2_R
• mcpwm0::int_raw::FAULT2_W
• mcpwm0::int_raw::R
• mcpwm0::int_raw::TIMER0_STOP_R
• mcpwm0::int_raw::TIMER0_STOP_W
• mcpwm0::int_raw::TIMER0_TEP_R
• mcpwm0::int_raw::TIMER0_TEP_W
• mcpwm0::int_raw::TIMER0_TEZ_R
• mcpwm0::int_raw::TIMER0_TEZ_W
• mcpwm0::int_raw::TIMER1_STOP_R
• mcpwm0::int_raw::TIMER1_STOP_W
• mcpwm0::int_raw::TIMER1_TEP_R
• mcpwm0::int_raw::TIMER1_TEP_W
• mcpwm0::int_raw::TIMER1_TEZ_R
• mcpwm0::int_raw::TIMER1_TEZ_W
• mcpwm0::int_raw::TIMER2_STOP_R
• mcpwm0::int_raw::TIMER2_STOP_W
• mcpwm0::int_raw::TIMER2_TEP_R
• mcpwm0::int_raw::TIMER2_TEP_W
• mcpwm0::int_raw::TIMER2_TEZ_R
• mcpwm0::int_raw::TIMER2_TEZ_W
• mcpwm0::int_raw::TZ0_CBC_R
• mcpwm0::int_raw::TZ0_CBC_W
• mcpwm0::int_raw::TZ0_OST_R
• mcpwm0::int_raw::TZ0_OST_W
• mcpwm0::int_raw::TZ1_CBC_R
• mcpwm0::int_raw::TZ1_CBC_W
• mcpwm0::int_raw::TZ1_OST_R
• mcpwm0::int_raw::TZ1_OST_W
• mcpwm0::int_raw::TZ2_CBC_R
• mcpwm0::int_raw::TZ2_CBC_W
• mcpwm0::int_raw::TZ2_OST_R
• mcpwm0::int_raw::TZ2_OST_W
• mcpwm0::int_raw::W
• mcpwm0::int_st::CAP0_R
• mcpwm0::int_st::CAP1_R
• mcpwm0::int_st::CAP2_R
• mcpwm0::int_st::CMPR0_TEA_R
• mcpwm0::int_st::CMPR0_TEB_R
• mcpwm0::int_st::CMPR1_TEA_R
• mcpwm0::int_st::CMPR1_TEB_R
• mcpwm0::int_st::CMPR2_TEA_R
• mcpwm0::int_st::CMPR2_TEB_R
• mcpwm0::int_st::FAULT0_CLR_R
• mcpwm0::int_st::FAULT0_R
• mcpwm0::int_st::FAULT1_CLR_R
• mcpwm0::int_st::FAULT1_R
• mcpwm0::int_st::FAULT2_CLR_R
• mcpwm0::int_st::FAULT2_R
• mcpwm0::int_st::R
• mcpwm0::int_st::TIMER0_STOP_R
• mcpwm0::int_st::TIMER0_TEP_R
• mcpwm0::int_st::TIMER0_TEZ_R
• mcpwm0::int_st::TIMER1_STOP_R
• mcpwm0::int_st::TIMER1_TEP_R
• mcpwm0::int_st::TIMER1_TEZ_R
• mcpwm0::int_st::TIMER2_STOP_R
• mcpwm0::int_st::TIMER2_TEP_R
• mcpwm0::int_st::TIMER2_TEZ_R
• mcpwm0::int_st::TZ0_CBC_R
• mcpwm0::int_st::TZ0_OST_R
• mcpwm0::int_st::TZ1_CBC_R
• mcpwm0::int_st::TZ1_OST_R
• mcpwm0::int_st::TZ2_CBC_R
• mcpwm0::int_st::TZ2_OST_R
• mcpwm0::operator_timersel::OPERATOR0_TIMERSEL_R
• mcpwm0::operator_timersel::OPERATOR0_TIMERSEL_W
• mcpwm0::operator_timersel::OPERATOR1_TIMERSEL_R
• mcpwm0::operator_timersel::OPERATOR1_TIMERSEL_W
• mcpwm0::operator_timersel::OPERATOR2_TIMERSEL_R
• mcpwm0::operator_timersel::OPERATOR2_TIMERSEL_W
• mcpwm0::operator_timersel::R
• mcpwm0::operator_timersel::W
• mcpwm0::task_en::R
• mcpwm0::task_en::TASK_CAP0_EN_R
• mcpwm0::task_en::TASK_CAP0_EN_W
• mcpwm0::task_en::TASK_CAP1_EN_R
• mcpwm0::task_en::TASK_CAP1_EN_W
• mcpwm0::task_en::TASK_CAP2_EN_R
• mcpwm0::task_en::TASK_CAP2_EN_W
• mcpwm0::task_en::TASK_CLR0_OST_EN_R
• mcpwm0::task_en::TASK_CLR0_OST_EN_W
• mcpwm0::task_en::TASK_CLR1_OST_EN_R
• mcpwm0::task_en::TASK_CLR1_OST_EN_W
• mcpwm0::task_en::TASK_CLR2_OST_EN_R
• mcpwm0::task_en::TASK_CLR2_OST_EN_W
• mcpwm0::task_en::TASK_CMPR0_A_UP_EN_R
• mcpwm0::task_en::TASK_CMPR0_A_UP_EN_W
• mcpwm0::task_en::TASK_CMPR0_B_UP_EN_R
• mcpwm0::task_en::TASK_CMPR0_B_UP_EN_W
• mcpwm0::task_en::TASK_CMPR1_A_UP_EN_R
• mcpwm0::task_en::TASK_CMPR1_A_UP_EN_W
• mcpwm0::task_en::TASK_CMPR1_B_UP_EN_R
• mcpwm0::task_en::TASK_CMPR1_B_UP_EN_W
• mcpwm0::task_en::TASK_CMPR2_A_UP_EN_R
• mcpwm0::task_en::TASK_CMPR2_A_UP_EN_W
• mcpwm0::task_en::TASK_CMPR2_B_UP_EN_R
• mcpwm0::task_en::TASK_CMPR2_B_UP_EN_W
• mcpwm0::task_en::TASK_GEN_STOP_EN_R
• mcpwm0::task_en::TASK_GEN_STOP_EN_W
• mcpwm0::task_en::TASK_TIMER0_PERIOD_UP_EN_R
• mcpwm0::task_en::TASK_TIMER0_PERIOD_UP_EN_W
• mcpwm0::task_en::TASK_TIMER0_SYNC_EN_R
• mcpwm0::task_en::TASK_TIMER0_SYNC_EN_W
• mcpwm0::task_en::TASK_TIMER1_PERIOD_UP_EN_R
• mcpwm0::task_en::TASK_TIMER1_PERIOD_UP_EN_W
• mcpwm0::task_en::TASK_TIMER1_SYNC_EN_R
• mcpwm0::task_en::TASK_TIMER1_SYNC_EN_W
• mcpwm0::task_en::TASK_TIMER2_PERIOD_UP_EN_R
• mcpwm0::task_en::TASK_TIMER2_PERIOD_UP_EN_W
• mcpwm0::task_en::TASK_TIMER2_SYNC_EN_R
• mcpwm0::task_en::TASK_TIMER2_SYNC_EN_W
• mcpwm0::task_en::TASK_TZ0_OST_EN_R
• mcpwm0::task_en::TASK_TZ0_OST_EN_W
• mcpwm0::task_en::TASK_TZ1_OST_EN_R
• mcpwm0::task_en::TASK_TZ1_OST_EN_W
• mcpwm0::task_en::TASK_TZ2_OST_EN_R
• mcpwm0::task_en::TASK_TZ2_OST_EN_W
• mcpwm0::task_en::W
• mcpwm0::timer::CFG0
• mcpwm0::timer::CFG1
• mcpwm0::timer::STATUS
• mcpwm0::timer::SYNC
• mcpwm0::timer::cfg0::PERIOD_R
• mcpwm0::timer::cfg0::PERIOD_UPMETHOD_R
• mcpwm0::timer::cfg0::PERIOD_UPMETHOD_W
• mcpwm0::timer::cfg0::PERIOD_W
• mcpwm0::timer::cfg0::PRESCALE_R
• mcpwm0::timer::cfg0::PRESCALE_W
• mcpwm0::timer::cfg0::R
• mcpwm0::timer::cfg0::W
• mcpwm0::timer::cfg1::MOD_R
• mcpwm0::timer::cfg1::MOD_W
• mcpwm0::timer::cfg1::R
• mcpwm0::timer::cfg1::START_R
• mcpwm0::timer::cfg1::START_W
• mcpwm0::timer::cfg1::W
• mcpwm0::timer::status::DIRECTION_R
• mcpwm0::timer::status::R
• mcpwm0::timer::status::VALUE_R
• mcpwm0::timer::sync::PHASE_DIRECTION_R
• mcpwm0::timer::sync::PHASE_DIRECTION_W
• mcpwm0::timer::sync::PHASE_R
• mcpwm0::timer::sync::PHASE_W
• mcpwm0::timer::sync::R
• mcpwm0::timer::sync::SW_R
• mcpwm0::timer::sync::SW_W
• mcpwm0::timer::sync::SYNCI_EN_R
• mcpwm0::timer::sync::SYNCI_EN_W
• mcpwm0::timer::sync::SYNCO_SEL_R
• mcpwm0::timer::sync::SYNCO_SEL_W
• mcpwm0::timer::sync::W
• mcpwm0::timer_synci_cfg::EXTERNAL_SYNCI0_INVERT_R
• mcpwm0::timer_synci_cfg::EXTERNAL_SYNCI0_INVERT_W
• mcpwm0::timer_synci_cfg::EXTERNAL_SYNCI1_INVERT_R
• mcpwm0::timer_synci_cfg::EXTERNAL_SYNCI1_INVERT_W
• mcpwm0::timer_synci_cfg::EXTERNAL_SYNCI2_INVERT_R
• mcpwm0::timer_synci_cfg::EXTERNAL_SYNCI2_INVERT_W
• mcpwm0::timer_synci_cfg::R
• mcpwm0::timer_synci_cfg::TIMER0_SYNCISEL_R
• mcpwm0::timer_synci_cfg::TIMER0_SYNCISEL_W
• mcpwm0::timer_synci_cfg::TIMER1_SYNCISEL_R
• mcpwm0::timer_synci_cfg::TIMER1_SYNCISEL_W
• mcpwm0::timer_synci_cfg::TIMER2_SYNCISEL_R
• mcpwm0::timer_synci_cfg::TIMER2_SYNCISEL_W
• mcpwm0::timer_synci_cfg::W
• mcpwm0::update_cfg::GLOBAL_FORCE_UP_R
• mcpwm0::update_cfg::GLOBAL_FORCE_UP_W
• mcpwm0::update_cfg::GLOBAL_UP_EN_R
• mcpwm0::update_cfg::GLOBAL_UP_EN_W
• mcpwm0::update_cfg::OP0_FORCE_UP_R
• mcpwm0::update_cfg::OP0_FORCE_UP_W
• mcpwm0::update_cfg::OP0_UP_EN_R
• mcpwm0::update_cfg::OP0_UP_EN_W
• mcpwm0::update_cfg::OP1_FORCE_UP_R
• mcpwm0::update_cfg::OP1_FORCE_UP_W
• mcpwm0::update_cfg::OP1_UP_EN_R
• mcpwm0::update_cfg::OP1_UP_EN_W
• mcpwm0::update_cfg::OP2_FORCE_UP_R
• mcpwm0::update_cfg::OP2_FORCE_UP_W
• mcpwm0::update_cfg::OP2_UP_EN_R
• mcpwm0::update_cfg::OP2_UP_EN_W
• mcpwm0::update_cfg::R
• mcpwm0::update_cfg::W
• mcpwm0::version::DATE_R
• mcpwm0::version::DATE_W
• mcpwm0::version::R
• mcpwm0::version::W
• mem_monitor::CLOCK_GATE
• mem_monitor::DATE
• mem_monitor::LOG_CHECK_DATA
• mem_monitor::LOG_DATA_MASK
• mem_monitor::LOG_MAX
• mem_monitor::LOG_MEM_ADDR_UPDATE
• mem_monitor::LOG_MEM_CURRENT_ADDR
• mem_monitor::LOG_MEM_END
• mem_monitor::LOG_MEM_FULL_FLAG
• mem_monitor::LOG_MEM_START
• mem_monitor::LOG_MIN
• mem_monitor::LOG_SETTING
• mem_monitor::clock_gate::CLK_EN_R
• mem_monitor::clock_gate::CLK_EN_W
• mem_monitor::clock_gate::R
• mem_monitor::clock_gate::W
• mem_monitor::date::DATE_R
• mem_monitor::date::DATE_W
• mem_monitor::date::R
• mem_monitor::date::W
• mem_monitor::log_check_data::LOG_CHECK_DATA_R
• mem_monitor::log_check_data::LOG_CHECK_DATA_W
• mem_monitor::log_check_data::R
• mem_monitor::log_check_data::W
• mem_monitor::log_data_mask::LOG_DATA_MASK_R
• mem_monitor::log_data_mask::LOG_DATA_MASK_W
• mem_monitor::log_data_mask::R
• mem_monitor::log_data_mask::W
• mem_monitor::log_max::LOG_MAX_R
• mem_monitor::log_max::LOG_MAX_W
• mem_monitor::log_max::R
• mem_monitor::log_max::W
• mem_monitor::log_mem_addr_update::LOG_MEM_ADDR_UPDATE_W
• mem_monitor::log_mem_addr_update::W
• mem_monitor::log_mem_current_addr::LOG_MEM_CURRENT_ADDR_R
• mem_monitor::log_mem_current_addr::R
• mem_monitor::log_mem_end::LOG_MEM_END_R
• mem_monitor::log_mem_end::LOG_MEM_END_W
• mem_monitor::log_mem_end::R
• mem_monitor::log_mem_end::W
• mem_monitor::log_mem_full_flag::CLR_LOG_MEM_FULL_FLAG_W
• mem_monitor::log_mem_full_flag::LOG_MEM_FULL_FLAG_R
• mem_monitor::log_mem_full_flag::R
• mem_monitor::log_mem_full_flag::W
• mem_monitor::log_mem_start::LOG_MEM_START_R
• mem_monitor::log_mem_start::LOG_MEM_START_W
• mem_monitor::log_mem_start::R
• mem_monitor::log_mem_start::W
• mem_monitor::log_min::LOG_MIN_R
• mem_monitor::log_min::LOG_MIN_W
• mem_monitor::log_min::R
• mem_monitor::log_min::W
• mem_monitor::log_setting::LOG_ENA_R
• mem_monitor::log_setting::LOG_ENA_W
• mem_monitor::log_setting::LOG_MEM_LOOP_ENABLE_R
• mem_monitor::log_setting::LOG_MEM_LOOP_ENABLE_W
• mem_monitor::log_setting::LOG_MODE_R
• mem_monitor::log_setting::LOG_MODE_W
• mem_monitor::log_setting::R
• mem_monitor::log_setting::W
• modem_lpcon::CLK_CONF
• modem_lpcon::CLK_CONF_FORCE_ON
• modem_lpcon::CLK_CONF_POWER_ST
• modem_lpcon::COEX_LP_CLK_CONF
• modem_lpcon::DATE
• modem_lpcon::I2C_MST_CLK_CONF
• modem_lpcon::LP_TIMER_CONF
• modem_lpcon::MEM_CONF
• modem_lpcon::MODEM_32K_CLK_CONF
• modem_lpcon::RST_CONF
• modem_lpcon::TEST_CONF
• modem_lpcon::WIFI_LP_CLK_CONF
• modem_lpcon::clk_conf::CLK_COEX_EN_R
• modem_lpcon::clk_conf::CLK_COEX_EN_W
• modem_lpcon::clk_conf::CLK_I2C_MST_EN_R
• modem_lpcon::clk_conf::CLK_I2C_MST_EN_W
• modem_lpcon::clk_conf::CLK_LP_TIMER_EN_R
• modem_lpcon::clk_conf::CLK_LP_TIMER_EN_W
• modem_lpcon::clk_conf::CLK_WIFIPWR_EN_R
• modem_lpcon::clk_conf::CLK_WIFIPWR_EN_W
• modem_lpcon::clk_conf::R
• modem_lpcon::clk_conf::W
• modem_lpcon::clk_conf_force_on::CLK_AGC_MEM_FO_R
• modem_lpcon::clk_conf_force_on::CLK_AGC_MEM_FO_W
• modem_lpcon::clk_conf_force_on::CLK_BCMEM_FO_R
• modem_lpcon::clk_conf_force_on::CLK_BCMEM_FO_W
• modem_lpcon::clk_conf_force_on::CLK_CHAN_FREQ_MEM_FO_R
• modem_lpcon::clk_conf_force_on::CLK_CHAN_FREQ_MEM_FO_W
• modem_lpcon::clk_conf_force_on::CLK_COEX_FO_R
• modem_lpcon::clk_conf_force_on::CLK_COEX_FO_W
• modem_lpcon::clk_conf_force_on::CLK_DC_MEM_FO_R
• modem_lpcon::clk_conf_force_on::CLK_DC_MEM_FO_W
• modem_lpcon::clk_conf_force_on::CLK_I2C_MST_FO_R
• modem_lpcon::clk_conf_force_on::CLK_I2C_MST_FO_W
• modem_lpcon::clk_conf_force_on::CLK_I2C_MST_MEM_FO_R
• modem_lpcon::clk_conf_force_on::CLK_I2C_MST_MEM_FO_W
• modem_lpcon::clk_conf_force_on::CLK_LP_TIMER_FO_R
• modem_lpcon::clk_conf_force_on::CLK_LP_TIMER_FO_W
• modem_lpcon::clk_conf_force_on::CLK_PBUS_MEM_FO_R
• modem_lpcon::clk_conf_force_on::CLK_PBUS_MEM_FO_W
• modem_lpcon::clk_conf_force_on::CLK_WIFIPWR_FO_R
• modem_lpcon::clk_conf_force_on::CLK_WIFIPWR_FO_W
• modem_lpcon::clk_conf_force_on::R
• modem_lpcon::clk_conf_force_on::W
• modem_lpcon::clk_conf_power_st::CLK_COEX_ST_MAP_R
• modem_lpcon::clk_conf_power_st::CLK_COEX_ST_MAP_W
• modem_lpcon::clk_conf_power_st::CLK_I2C_MST_ST_MAP_R
• modem_lpcon::clk_conf_power_st::CLK_I2C_MST_ST_MAP_W
• modem_lpcon::clk_conf_power_st::CLK_LP_APB_ST_MAP_R
• modem_lpcon::clk_conf_power_st::CLK_LP_APB_ST_MAP_W
• modem_lpcon::clk_conf_power_st::CLK_WIFIPWR_ST_MAP_R
• modem_lpcon::clk_conf_power_st::CLK_WIFIPWR_ST_MAP_W
• modem_lpcon::clk_conf_power_st::R
• modem_lpcon::clk_conf_power_st::W
• modem_lpcon::coex_lp_clk_conf::CLK_COEX_LP_DIV_NUM_R
• modem_lpcon::coex_lp_clk_conf::CLK_COEX_LP_DIV_NUM_W
• modem_lpcon::coex_lp_clk_conf::CLK_COEX_LP_SEL_OSC_FAST_R
• modem_lpcon::coex_lp_clk_conf::CLK_COEX_LP_SEL_OSC_FAST_W
• modem_lpcon::coex_lp_clk_conf::CLK_COEX_LP_SEL_OSC_SLOW_R
• modem_lpcon::coex_lp_clk_conf::CLK_COEX_LP_SEL_OSC_SLOW_W
• modem_lpcon::coex_lp_clk_conf::CLK_COEX_LP_SEL_XTAL32K_R
• modem_lpcon::coex_lp_clk_conf::CLK_COEX_LP_SEL_XTAL32K_W
• modem_lpcon::coex_lp_clk_conf::CLK_COEX_LP_SEL_XTAL_R
• modem_lpcon::coex_lp_clk_conf::CLK_COEX_LP_SEL_XTAL_W
• modem_lpcon::coex_lp_clk_conf::R
• modem_lpcon::coex_lp_clk_conf::W
• modem_lpcon::date::DATE_R
• modem_lpcon::date::DATE_W
• modem_lpcon::date::R
• modem_lpcon::date::W
• modem_lpcon::i2c_mst_clk_conf::CLK_I2C_MST_SEL_160M_R
• modem_lpcon::i2c_mst_clk_conf::CLK_I2C_MST_SEL_160M_W
• modem_lpcon::i2c_mst_clk_conf::R
• modem_lpcon::i2c_mst_clk_conf::W
• modem_lpcon::lp_timer_conf::CLK_LP_TIMER_DIV_NUM_R
• modem_lpcon::lp_timer_conf::CLK_LP_TIMER_DIV_NUM_W
• modem_lpcon::lp_timer_conf::CLK_LP_TIMER_SEL_OSC_FAST_R
• modem_lpcon::lp_timer_conf::CLK_LP_TIMER_SEL_OSC_FAST_W
• modem_lpcon::lp_timer_conf::CLK_LP_TIMER_SEL_OSC_SLOW_R
• modem_lpcon::lp_timer_conf::CLK_LP_TIMER_SEL_OSC_SLOW_W
• modem_lpcon::lp_timer_conf::CLK_LP_TIMER_SEL_XTAL32K_R
• modem_lpcon::lp_timer_conf::CLK_LP_TIMER_SEL_XTAL32K_W
• modem_lpcon::lp_timer_conf::CLK_LP_TIMER_SEL_XTAL_R
• modem_lpcon::lp_timer_conf::CLK_LP_TIMER_SEL_XTAL_W
• modem_lpcon::lp_timer_conf::R
• modem_lpcon::lp_timer_conf::W
• modem_lpcon::mem_conf::AGC_MEM_FORCE_PD_R
• modem_lpcon::mem_conf::AGC_MEM_FORCE_PD_W
• modem_lpcon::mem_conf::AGC_MEM_FORCE_PU_R
• modem_lpcon::mem_conf::AGC_MEM_FORCE_PU_W
• modem_lpcon::mem_conf::BC_MEM_FORCE_PD_R
• modem_lpcon::mem_conf::BC_MEM_FORCE_PD_W
• modem_lpcon::mem_conf::BC_MEM_FORCE_PU_R
• modem_lpcon::mem_conf::BC_MEM_FORCE_PU_W
• modem_lpcon::mem_conf::CHAN_FREQ_MEM_FORCE_PD_R
• modem_lpcon::mem_conf::CHAN_FREQ_MEM_FORCE_PD_W
• modem_lpcon::mem_conf::CHAN_FREQ_MEM_FORCE_PU_R
• modem_lpcon::mem_conf::CHAN_FREQ_MEM_FORCE_PU_W
• modem_lpcon::mem_conf::DC_MEM_FORCE_PD_R
• modem_lpcon::mem_conf::DC_MEM_FORCE_PD_W
• modem_lpcon::mem_conf::DC_MEM_FORCE_PU_R
• modem_lpcon::mem_conf::DC_MEM_FORCE_PU_W
• modem_lpcon::mem_conf::I2C_MST_MEM_FORCE_PD_R
• modem_lpcon::mem_conf::I2C_MST_MEM_FORCE_PD_W
• modem_lpcon::mem_conf::I2C_MST_MEM_FORCE_PU_R
• modem_lpcon::mem_conf::I2C_MST_MEM_FORCE_PU_W
• modem_lpcon::mem_conf::MODEM_PWR_MEM_RA_R
• modem_lpcon::mem_conf::MODEM_PWR_MEM_RA_W
• modem_lpcon::mem_conf::MODEM_PWR_MEM_WA_R
• modem_lpcon::mem_conf::MODEM_PWR_MEM_WA_W
• modem_lpcon::mem_conf::MODEM_PWR_MEM_WP_R
• modem_lpcon::mem_conf::MODEM_PWR_MEM_WP_W
• modem_lpcon::mem_conf::PBUS_MEM_FORCE_PD_R
• modem_lpcon::mem_conf::PBUS_MEM_FORCE_PD_W
• modem_lpcon::mem_conf::PBUS_MEM_FORCE_PU_R
• modem_lpcon::mem_conf::PBUS_MEM_FORCE_PU_W
• modem_lpcon::mem_conf::R
• modem_lpcon::mem_conf::W
• modem_lpcon::modem_32k_clk_conf::CLK_MODEM_32K_SEL_R
• modem_lpcon::modem_32k_clk_conf::CLK_MODEM_32K_SEL_W
• modem_lpcon::modem_32k_clk_conf::R
• modem_lpcon::modem_32k_clk_conf::W
• modem_lpcon::rst_conf::RST_COEX_W
• modem_lpcon::rst_conf::RST_I2C_MST_W
• modem_lpcon::rst_conf::RST_LP_TIMER_W
• modem_lpcon::rst_conf::RST_WIFIPWR_W
• modem_lpcon::rst_conf::W
• modem_lpcon::test_conf::CLK_DEBUG_ENA_R
• modem_lpcon::test_conf::CLK_DEBUG_ENA_W
• modem_lpcon::test_conf::CLK_EN_R
• modem_lpcon::test_conf::CLK_EN_W
• modem_lpcon::test_conf::R
• modem_lpcon::test_conf::W
• modem_lpcon::wifi_lp_clk_conf::CLK_WIFIPWR_LP_DIV_NUM_R
• modem_lpcon::wifi_lp_clk_conf::CLK_WIFIPWR_LP_DIV_NUM_W
• modem_lpcon::wifi_lp_clk_conf::CLK_WIFIPWR_LP_SEL_OSC_FAST_R
• modem_lpcon::wifi_lp_clk_conf::CLK_WIFIPWR_LP_SEL_OSC_FAST_W
• modem_lpcon::wifi_lp_clk_conf::CLK_WIFIPWR_LP_SEL_OSC_SLOW_R
• modem_lpcon::wifi_lp_clk_conf::CLK_WIFIPWR_LP_SEL_OSC_SLOW_W
• modem_lpcon::wifi_lp_clk_conf::CLK_WIFIPWR_LP_SEL_XTAL32K_R
• modem_lpcon::wifi_lp_clk_conf::CLK_WIFIPWR_LP_SEL_XTAL32K_W
• modem_lpcon::wifi_lp_clk_conf::CLK_WIFIPWR_LP_SEL_XTAL_R
• modem_lpcon::wifi_lp_clk_conf::CLK_WIFIPWR_LP_SEL_XTAL_W
• modem_lpcon::wifi_lp_clk_conf::R
• modem_lpcon::wifi_lp_clk_conf::W
• modem_syscon::CLK_CONF
• modem_syscon::CLK_CONF1
• modem_syscon::CLK_CONF1_FORCE_ON
• modem_syscon::CLK_CONF_FORCE_ON
• modem_syscon::CLK_CONF_POWER_ST
• modem_syscon::DATE
• modem_syscon::MEM_CONF
• modem_syscon::MODEM_RST_CONF
• modem_syscon::TEST_CONF
• modem_syscon::WIFI_BB_CFG
• modem_syscon::clk_conf1::CLK_BT_APB_EN_R
• modem_syscon::clk_conf1::CLK_BT_APB_EN_W
• modem_syscon::clk_conf1::CLK_BT_EN_R
• modem_syscon::clk_conf1::CLK_BT_EN_W
• modem_syscon::clk_conf1::CLK_FE_160M_EN_R
• modem_syscon::clk_conf1::CLK_FE_160M_EN_W
• modem_syscon::clk_conf1::CLK_FE_20M_EN_R
• modem_syscon::clk_conf1::CLK_FE_20M_EN_W
• modem_syscon::clk_conf1::CLK_FE_40M_EN_R
• modem_syscon::clk_conf1::CLK_FE_40M_EN_W
• modem_syscon::clk_conf1::CLK_FE_480M_EN_R
• modem_syscon::clk_conf1::CLK_FE_480M_EN_W
• modem_syscon::clk_conf1::CLK_FE_80M_EN_R
• modem_syscon::clk_conf1::CLK_FE_80M_EN_W
• modem_syscon::clk_conf1::CLK_FE_ANAMODE_160M_EN_R
• modem_syscon::clk_conf1::CLK_FE_ANAMODE_160M_EN_W
• modem_syscon::clk_conf1::CLK_FE_ANAMODE_40M_EN_R
• modem_syscon::clk_conf1::CLK_FE_ANAMODE_40M_EN_W
• modem_syscon::clk_conf1::CLK_FE_ANAMODE_80M_EN_R
• modem_syscon::clk_conf1::CLK_FE_ANAMODE_80M_EN_W
• modem_syscon::clk_conf1::CLK_FE_APB_EN_R
• modem_syscon::clk_conf1::CLK_FE_APB_EN_W
• modem_syscon::clk_conf1::CLK_FE_CAL_160M_EN_R
• modem_syscon::clk_conf1::CLK_FE_CAL_160M_EN_W
• modem_syscon::clk_conf1::CLK_WIFIBB_160X1_EN_R
• modem_syscon::clk_conf1::CLK_WIFIBB_160X1_EN_W
• modem_syscon::clk_conf1::CLK_WIFIBB_22M_EN_R
• modem_syscon::clk_conf1::CLK_WIFIBB_22M_EN_W
• modem_syscon::clk_conf1::CLK_WIFIBB_40M_EN_R
• modem_syscon::clk_conf1::CLK_WIFIBB_40M_EN_W
• modem_syscon::clk_conf1::CLK_WIFIBB_40X1_EN_R
• modem_syscon::clk_conf1::CLK_WIFIBB_40X1_EN_W
• modem_syscon::clk_conf1::CLK_WIFIBB_40X_EN_R
• modem_syscon::clk_conf1::CLK_WIFIBB_40X_EN_W
• modem_syscon::clk_conf1::CLK_WIFIBB_44M_EN_R
• modem_syscon::clk_conf1::CLK_WIFIBB_44M_EN_W
• modem_syscon::clk_conf1::CLK_WIFIBB_480M_EN_R
• modem_syscon::clk_conf1::CLK_WIFIBB_480M_EN_W
• modem_syscon::clk_conf1::CLK_WIFIBB_80M_EN_R
• modem_syscon::clk_conf1::CLK_WIFIBB_80M_EN_W
• modem_syscon::clk_conf1::CLK_WIFIBB_80X1_EN_R
• modem_syscon::clk_conf1::CLK_WIFIBB_80X1_EN_W
• modem_syscon::clk_conf1::CLK_WIFIBB_80X_EN_R
• modem_syscon::clk_conf1::CLK_WIFIBB_80X_EN_W
• modem_syscon::clk_conf1::CLK_WIFIMAC_EN_R
• modem_syscon::clk_conf1::CLK_WIFIMAC_EN_W
• modem_syscon::clk_conf1::CLK_WIFI_APB_EN_R
• modem_syscon::clk_conf1::CLK_WIFI_APB_EN_W
• modem_syscon::clk_conf1::R
• modem_syscon::clk_conf1::W
• modem_syscon::clk_conf1_force_on::CLK_BT_APB_FO_R
• modem_syscon::clk_conf1_force_on::CLK_BT_APB_FO_W
• modem_syscon::clk_conf1_force_on::CLK_BT_FO_R
• modem_syscon::clk_conf1_force_on::CLK_BT_FO_W
• modem_syscon::clk_conf1_force_on::CLK_FE_160M_FO_R
• modem_syscon::clk_conf1_force_on::CLK_FE_160M_FO_W
• modem_syscon::clk_conf1_force_on::CLK_FE_20M_FO_R
• modem_syscon::clk_conf1_force_on::CLK_FE_20M_FO_W
• modem_syscon::clk_conf1_force_on::CLK_FE_40M_FO_R
• modem_syscon::clk_conf1_force_on::CLK_FE_40M_FO_W
• modem_syscon::clk_conf1_force_on::CLK_FE_480M_FO_R
• modem_syscon::clk_conf1_force_on::CLK_FE_480M_FO_W
• modem_syscon::clk_conf1_force_on::CLK_FE_80M_FO_R
• modem_syscon::clk_conf1_force_on::CLK_FE_80M_FO_W
• modem_syscon::clk_conf1_force_on::CLK_FE_ANAMODE_160M_FO_R
• modem_syscon::clk_conf1_force_on::CLK_FE_ANAMODE_160M_FO_W
• modem_syscon::clk_conf1_force_on::CLK_FE_ANAMODE_40M_FO_R
• modem_syscon::clk_conf1_force_on::CLK_FE_ANAMODE_40M_FO_W
• modem_syscon::clk_conf1_force_on::CLK_FE_ANAMODE_80M_FO_R
• modem_syscon::clk_conf1_force_on::CLK_FE_ANAMODE_80M_FO_W
• modem_syscon::clk_conf1_force_on::CLK_FE_APB_FO_R
• modem_syscon::clk_conf1_force_on::CLK_FE_APB_FO_W
• modem_syscon::clk_conf1_force_on::CLK_FE_CAL_160M_FO_R
• modem_syscon::clk_conf1_force_on::CLK_FE_CAL_160M_FO_W
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_160X1_FO_R
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_160X1_FO_W
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_22M_FO_R
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_22M_FO_W
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_40M_FO_R
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_40M_FO_W
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_40X1_FO_R
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_40X1_FO_W
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_40X_FO_R
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_40X_FO_W
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_44M_FO_R
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_44M_FO_W
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_480M_FO_R
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_480M_FO_W
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_80M_FO_R
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_80M_FO_W
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_80X1_FO_R
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_80X1_FO_W
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_80X_FO_R
• modem_syscon::clk_conf1_force_on::CLK_WIFIBB_80X_FO_W
• modem_syscon::clk_conf1_force_on::CLK_WIFIMAC_FO_R
• modem_syscon::clk_conf1_force_on::CLK_WIFIMAC_FO_W
• modem_syscon::clk_conf1_force_on::CLK_WIFI_APB_FO_R
• modem_syscon::clk_conf1_force_on::CLK_WIFI_APB_FO_W
• modem_syscon::clk_conf1_force_on::R
• modem_syscon::clk_conf1_force_on::W
• modem_syscon::clk_conf::CLK_BLE_TIMER_EN_R
• modem_syscon::clk_conf::CLK_BLE_TIMER_EN_W
• modem_syscon::clk_conf::CLK_DATA_DUMP_EN_R
• modem_syscon::clk_conf::CLK_DATA_DUMP_EN_W
• modem_syscon::clk_conf::CLK_DATA_DUMP_MUX_R
• modem_syscon::clk_conf::CLK_DATA_DUMP_MUX_W
• modem_syscon::clk_conf::CLK_ETM_EN_R
• modem_syscon::clk_conf::CLK_ETM_EN_W
• modem_syscon::clk_conf::CLK_MODEM_SEC_APB_EN_R
• modem_syscon::clk_conf::CLK_MODEM_SEC_APB_EN_W
• modem_syscon::clk_conf::CLK_MODEM_SEC_BAH_EN_R
• modem_syscon::clk_conf::CLK_MODEM_SEC_BAH_EN_W
• modem_syscon::clk_conf::CLK_MODEM_SEC_CCM_EN_R
• modem_syscon::clk_conf::CLK_MODEM_SEC_CCM_EN_W
• modem_syscon::clk_conf::CLK_MODEM_SEC_ECB_EN_R
• modem_syscon::clk_conf::CLK_MODEM_SEC_ECB_EN_W
• modem_syscon::clk_conf::CLK_MODEM_SEC_EN_R
• modem_syscon::clk_conf::CLK_MODEM_SEC_EN_W
• modem_syscon::clk_conf::CLK_ZB_APB_EN_R
• modem_syscon::clk_conf::CLK_ZB_APB_EN_W
• modem_syscon::clk_conf::CLK_ZB_MAC_EN_R
• modem_syscon::clk_conf::CLK_ZB_MAC_EN_W
• modem_syscon::clk_conf::R
• modem_syscon::clk_conf::W
• modem_syscon::clk_conf_force_on::CLK_BLE_TIMER_FO_R
• modem_syscon::clk_conf_force_on::CLK_BLE_TIMER_FO_W
• modem_syscon::clk_conf_force_on::CLK_DATA_DUMP_FO_R
• modem_syscon::clk_conf_force_on::CLK_DATA_DUMP_FO_W
• modem_syscon::clk_conf_force_on::CLK_ETM_FO_R
• modem_syscon::clk_conf_force_on::CLK_ETM_FO_W
• modem_syscon::clk_conf_force_on::CLK_MODEM_SEC_APB_FO_R
• modem_syscon::clk_conf_force_on::CLK_MODEM_SEC_APB_FO_W
• modem_syscon::clk_conf_force_on::CLK_MODEM_SEC_BAH_FO_R
• modem_syscon::clk_conf_force_on::CLK_MODEM_SEC_BAH_FO_W
• modem_syscon::clk_conf_force_on::CLK_MODEM_SEC_CCM_FO_R
• modem_syscon::clk_conf_force_on::CLK_MODEM_SEC_CCM_FO_W
• modem_syscon::clk_conf_force_on::CLK_MODEM_SEC_ECB_FO_R
• modem_syscon::clk_conf_force_on::CLK_MODEM_SEC_ECB_FO_W
• modem_syscon::clk_conf_force_on::CLK_MODEM_SEC_FO_R
• modem_syscon::clk_conf_force_on::CLK_MODEM_SEC_FO_W
• modem_syscon::clk_conf_force_on::CLK_ZB_APB_FO_R
• modem_syscon::clk_conf_force_on::CLK_ZB_APB_FO_W
• modem_syscon::clk_conf_force_on::CLK_ZB_MAC_FO_R
• modem_syscon::clk_conf_force_on::CLK_ZB_MAC_FO_W
• modem_syscon::clk_conf_force_on::R
• modem_syscon::clk_conf_force_on::W
• modem_syscon::clk_conf_power_st::CLK_BT_ST_MAP_R
• modem_syscon::clk_conf_power_st::CLK_BT_ST_MAP_W
• modem_syscon::clk_conf_power_st::CLK_FE_ST_MAP_R
• modem_syscon::clk_conf_power_st::CLK_FE_ST_MAP_W
• modem_syscon::clk_conf_power_st::CLK_MODEM_APB_ST_MAP_R
• modem_syscon::clk_conf_power_st::CLK_MODEM_APB_ST_MAP_W
• modem_syscon::clk_conf_power_st::CLK_MODEM_PERI_ST_MAP_R
• modem_syscon::clk_conf_power_st::CLK_MODEM_PERI_ST_MAP_W
• modem_syscon::clk_conf_power_st::CLK_WIFI_ST_MAP_R
• modem_syscon::clk_conf_power_st::CLK_WIFI_ST_MAP_W
• modem_syscon::clk_conf_power_st::CLK_ZB_ST_MAP_R
• modem_syscon::clk_conf_power_st::CLK_ZB_ST_MAP_W
• modem_syscon::clk_conf_power_st::R
• modem_syscon::clk_conf_power_st::W
• modem_syscon::date::DATE_R
• modem_syscon::date::DATE_W
• modem_syscon::date::R
• modem_syscon::date::W
• modem_syscon::mem_conf::MODEM_MEM_RA_R
• modem_syscon::mem_conf::MODEM_MEM_RA_W
• modem_syscon::mem_conf::MODEM_MEM_WA_R
• modem_syscon::mem_conf::MODEM_MEM_WA_W
• modem_syscon::mem_conf::MODEM_MEM_WP_R
• modem_syscon::mem_conf::MODEM_MEM_WP_W
• modem_syscon::mem_conf::R
• modem_syscon::mem_conf::W
• modem_syscon::modem_rst_conf::R
• modem_syscon::modem_rst_conf::RST_BLE_TIMER_R
• modem_syscon::modem_rst_conf::RST_BLE_TIMER_W
• modem_syscon::modem_rst_conf::RST_BTBB_APB_R
• modem_syscon::modem_rst_conf::RST_BTBB_APB_W
• modem_syscon::modem_rst_conf::RST_BTBB_R
• modem_syscon::modem_rst_conf::RST_BTBB_W
• modem_syscon::modem_rst_conf::RST_BTMAC_APB_R
• modem_syscon::modem_rst_conf::RST_BTMAC_APB_W
• modem_syscon::modem_rst_conf::RST_BTMAC_R
• modem_syscon::modem_rst_conf::RST_BTMAC_W
• modem_syscon::modem_rst_conf::RST_DATA_DUMP_R
• modem_syscon::modem_rst_conf::RST_DATA_DUMP_W
• modem_syscon::modem_rst_conf::RST_ETM_R
• modem_syscon::modem_rst_conf::RST_ETM_W
• modem_syscon::modem_rst_conf::RST_FE_R
• modem_syscon::modem_rst_conf::RST_FE_W
• modem_syscon::modem_rst_conf::RST_MODEM_BAH_R
• modem_syscon::modem_rst_conf::RST_MODEM_BAH_W
• modem_syscon::modem_rst_conf::RST_MODEM_CCM_R
• modem_syscon::modem_rst_conf::RST_MODEM_CCM_W
• modem_syscon::modem_rst_conf::RST_MODEM_ECB_R
• modem_syscon::modem_rst_conf::RST_MODEM_ECB_W
• modem_syscon::modem_rst_conf::RST_MODEM_SEC_R
• modem_syscon::modem_rst_conf::RST_MODEM_SEC_W
• modem_syscon::modem_rst_conf::RST_WIFIBB_R
• modem_syscon::modem_rst_conf::RST_WIFIBB_W
• modem_syscon::modem_rst_conf::RST_WIFIMAC_R
• modem_syscon::modem_rst_conf::RST_WIFIMAC_W
• modem_syscon::modem_rst_conf::RST_ZBMAC_R
• modem_syscon::modem_rst_conf::RST_ZBMAC_W
• modem_syscon::modem_rst_conf::W
• modem_syscon::test_conf::CLK_EN_R
• modem_syscon::test_conf::CLK_EN_W
• modem_syscon::test_conf::R
• modem_syscon::test_conf::W
• modem_syscon::wifi_bb_cfg::R
• modem_syscon::wifi_bb_cfg::W
• modem_syscon::wifi_bb_cfg::WIFI_BB_CFG_R
• modem_syscon::wifi_bb_cfg::WIFI_BB_CFG_W
• otp_debug::APB2OTP_EN
• otp_debug::BLK0_BACKUP1_W1
• otp_debug::BLK0_BACKUP1_W2
• otp_debug::BLK0_BACKUP1_W3
• otp_debug::BLK0_BACKUP1_W4
• otp_debug::BLK0_BACKUP1_W5
• otp_debug::BLK0_BACKUP2_W1
• otp_debug::BLK0_BACKUP2_W2
• otp_debug::BLK0_BACKUP2_W3
• otp_debug::BLK0_BACKUP2_W4
• otp_debug::BLK0_BACKUP2_W5
• otp_debug::BLK0_BACKUP3_W1
• otp_debug::BLK0_BACKUP3_W2
• otp_debug::BLK0_BACKUP3_W3
• otp_debug::BLK0_BACKUP3_W4
• otp_debug::BLK0_BACKUP3_W5
• otp_debug::BLK0_BACKUP4_W1
• otp_debug::BLK0_BACKUP4_W2
• otp_debug::BLK0_BACKUP4_W3
• otp_debug::BLK0_BACKUP4_W4
• otp_debug::BLK0_BACKUP4_W5
• otp_debug::BLK10_W1
• otp_debug::BLK10_W10
• otp_debug::BLK10_W11
• otp_debug::BLK10_W2
• otp_debug::BLK10_W3
• otp_debug::BLK10_W4
• otp_debug::BLK10_W5
• otp_debug::BLK10_W6
• otp_debug::BLK10_W7
• otp_debug::BLK10_W8
• otp_debug::BLK10_W9
• otp_debug::BLK1_W1
• otp_debug::BLK1_W2
• otp_debug::BLK1_W3
• otp_debug::BLK1_W4
• otp_debug::BLK1_W5
• otp_debug::BLK1_W6
• otp_debug::BLK1_W7
• otp_debug::BLK1_W8
• otp_debug::BLK1_W9
• otp_debug::BLK2_W1
• otp_debug::BLK2_W10
• otp_debug::BLK2_W11
• otp_debug::BLK2_W2
• otp_debug::BLK2_W3
• otp_debug::BLK2_W4
• otp_debug::BLK2_W5
• otp_debug::BLK2_W6
• otp_debug::BLK2_W7
• otp_debug::BLK2_W8
• otp_debug::BLK2_W9
• otp_debug::BLK3_W1
• otp_debug::BLK3_W10
• otp_debug::BLK3_W11
• otp_debug::BLK3_W2
• otp_debug::BLK3_W3
• otp_debug::BLK3_W4
• otp_debug::BLK3_W5
• otp_debug::BLK3_W6
• otp_debug::BLK3_W7
• otp_debug::BLK3_W8
• otp_debug::BLK3_W9
• otp_debug::BLK4_W1
• otp_debug::BLK4_W10
• otp_debug::BLK4_W11
• otp_debug::BLK4_W2
• otp_debug::BLK4_W3
• otp_debug::BLK4_W4
• otp_debug::BLK4_W5
• otp_debug::BLK4_W6
• otp_debug::BLK4_W7
• otp_debug::BLK4_W8
• otp_debug::BLK4_W9
• otp_debug::BLK5_W1
• otp_debug::BLK5_W10
• otp_debug::BLK5_W11
• otp_debug::BLK5_W2
• otp_debug::BLK5_W3
• otp_debug::BLK5_W4
• otp_debug::BLK5_W5
• otp_debug::BLK5_W6
• otp_debug::BLK5_W7
• otp_debug::BLK5_W8
• otp_debug::BLK5_W9
• otp_debug::BLK6_W1
• otp_debug::BLK6_W10
• otp_debug::BLK6_W11
• otp_debug::BLK6_W2
• otp_debug::BLK6_W3
• otp_debug::BLK6_W4
• otp_debug::BLK6_W5
• otp_debug::BLK6_W6
• otp_debug::BLK6_W7
• otp_debug::BLK6_W8
• otp_debug::BLK6_W9
• otp_debug::BLK7_W1
• otp_debug::BLK7_W10
• otp_debug::BLK7_W11
• otp_debug::BLK7_W2
• otp_debug::BLK7_W3
• otp_debug::BLK7_W4
• otp_debug::BLK7_W5
• otp_debug::BLK7_W6
• otp_debug::BLK7_W7
• otp_debug::BLK7_W8
• otp_debug::BLK7_W9
• otp_debug::BLK8_W1
• otp_debug::BLK8_W10
• otp_debug::BLK8_W11
• otp_debug::BLK8_W2
• otp_debug::BLK8_W3
• otp_debug::BLK8_W4
• otp_debug::BLK8_W5
• otp_debug::BLK8_W6
• otp_debug::BLK8_W7
• otp_debug::BLK8_W8
• otp_debug::BLK8_W9
• otp_debug::BLK9_W1
• otp_debug::BLK9_W10
• otp_debug::BLK9_W11
• otp_debug::BLK9_W2
• otp_debug::BLK9_W3
• otp_debug::BLK9_W4
• otp_debug::BLK9_W5
• otp_debug::BLK9_W6
• otp_debug::BLK9_W7
• otp_debug::BLK9_W8
• otp_debug::BLK9_W9
• otp_debug::CLK
• otp_debug::DATE
• otp_debug::WR_DIS
• otp_debug::apb2otp_en::APB2OTP_EN_R
• otp_debug::apb2otp_en::APB2OTP_EN_W
• otp_debug::apb2otp_en::R
• otp_debug::apb2otp_en::W
• otp_debug::blk0_backup1_w1::OTP_BEBUG_BLOCK0_BACKUP1_W1_R
• otp_debug::blk0_backup1_w1::R
• otp_debug::blk0_backup1_w2::OTP_BEBUG_BLOCK0_BACKUP1_W2_R
• otp_debug::blk0_backup1_w2::R
• otp_debug::blk0_backup1_w3::OTP_BEBUG_BLOCK0_BACKUP1_W3_R
• otp_debug::blk0_backup1_w3::R
• otp_debug::blk0_backup1_w4::OTP_BEBUG_BLOCK0_BACKUP1_W4_R
• otp_debug::blk0_backup1_w4::R
• otp_debug::blk0_backup1_w5::OTP_BEBUG_BLOCK0_BACKUP1_W5_R
• otp_debug::blk0_backup1_w5::R
• otp_debug::blk0_backup2_w1::OTP_BEBUG_BLOCK0_BACKUP2_W1_R
• otp_debug::blk0_backup2_w1::R
• otp_debug::blk0_backup2_w2::OTP_BEBUG_BLOCK0_BACKUP2_W2_R
• otp_debug::blk0_backup2_w2::R
• otp_debug::blk0_backup2_w3::OTP_BEBUG_BLOCK0_BACKUP2_W3_R
• otp_debug::blk0_backup2_w3::R
• otp_debug::blk0_backup2_w4::OTP_BEBUG_BLOCK0_BACKUP2_W4_R
• otp_debug::blk0_backup2_w4::R
• otp_debug::blk0_backup2_w5::OTP_BEBUG_BLOCK0_BACKUP2_W5_R
• otp_debug::blk0_backup2_w5::R
• otp_debug::blk0_backup3_w1::OTP_BEBUG_BLOCK0_BACKUP3_W1_R
• otp_debug::blk0_backup3_w1::R
• otp_debug::blk0_backup3_w2::OTP_BEBUG_BLOCK0_BACKUP3_W2_R
• otp_debug::blk0_backup3_w2::R
• otp_debug::blk0_backup3_w3::OTP_BEBUG_BLOCK0_BACKUP3_W3_R
• otp_debug::blk0_backup3_w3::R
• otp_debug::blk0_backup3_w4::OTP_BEBUG_BLOCK0_BACKUP3_W4_R
• otp_debug::blk0_backup3_w4::R
• otp_debug::blk0_backup3_w5::OTP_BEBUG_BLOCK0_BACKUP3_W5_R
• otp_debug::blk0_backup3_w5::R
• otp_debug::blk0_backup4_w1::OTP_BEBUG_BLOCK0_BACKUP4_W1_R
• otp_debug::blk0_backup4_w1::R
• otp_debug::blk0_backup4_w2::OTP_BEBUG_BLOCK0_BACKUP4_W2_R
• otp_debug::blk0_backup4_w2::R
• otp_debug::blk0_backup4_w3::OTP_BEBUG_BLOCK0_BACKUP4_W3_R
• otp_debug::blk0_backup4_w3::R
• otp_debug::blk0_backup4_w4::OTP_BEBUG_BLOCK0_BACKUP4_W4_R
• otp_debug::blk0_backup4_w4::R
• otp_debug::blk0_backup4_w5::OTP_BEBUG_BLOCK0_BACKUP4_W5_R
• otp_debug::blk0_backup4_w5::R
• otp_debug::blk10_w10::BLOCK19_W10_R
• otp_debug::blk10_w10::R
• otp_debug::blk10_w11::BLOCK10_W11_R
• otp_debug::blk10_w11::R
• otp_debug::blk10_w1::BLOCK10_W1_R
• otp_debug::blk10_w1::R
• otp_debug::blk10_w2::BLOCK10_W2_R
• otp_debug::blk10_w2::R
• otp_debug::blk10_w3::BLOCK10_W3_R
• otp_debug::blk10_w3::R
• otp_debug::blk10_w4::BLOCK10_W4_R
• otp_debug::blk10_w4::R
• otp_debug::blk10_w5::BLOCK10_W5_R
• otp_debug::blk10_w5::R
• otp_debug::blk10_w6::BLOCK10_W6_R
• otp_debug::blk10_w6::R
• otp_debug::blk10_w7::BLOCK10_W7_R
• otp_debug::blk10_w7::R
• otp_debug::blk10_w8::BLOCK10_W8_R
• otp_debug::blk10_w8::R
• otp_debug::blk10_w9::BLOCK10_W9_R
• otp_debug::blk10_w9::R
• otp_debug::blk1_w1::BLOCK1_W1_R
• otp_debug::blk1_w1::R
• otp_debug::blk1_w2::BLOCK1_W2_R
• otp_debug::blk1_w2::R
• otp_debug::blk1_w3::BLOCK1_W3_R
• otp_debug::blk1_w3::R
• otp_debug::blk1_w4::BLOCK1_W4_R
• otp_debug::blk1_w4::R
• otp_debug::blk1_w5::BLOCK1_W5_R
• otp_debug::blk1_w5::R
• otp_debug::blk1_w6::BLOCK1_W6_R
• otp_debug::blk1_w6::R
• otp_debug::blk1_w7::BLOCK1_W7_R
• otp_debug::blk1_w7::R
• otp_debug::blk1_w8::BLOCK1_W8_R
• otp_debug::blk1_w8::R
• otp_debug::blk1_w9::BLOCK1_W9_R
• otp_debug::blk1_w9::R
• otp_debug::blk2_w10::BLOCK2_W10_R
• otp_debug::blk2_w10::R
• otp_debug::blk2_w11::BLOCK2_W11_R
• otp_debug::blk2_w11::R
• otp_debug::blk2_w1::BLOCK2_W1_R
• otp_debug::blk2_w1::R
• otp_debug::blk2_w2::BLOCK2_W2_R
• otp_debug::blk2_w2::R
• otp_debug::blk2_w3::BLOCK2_W3_R
• otp_debug::blk2_w3::R
• otp_debug::blk2_w4::BLOCK2_W4_R
• otp_debug::blk2_w4::R
• otp_debug::blk2_w5::BLOCK2_W5_R
• otp_debug::blk2_w5::R
• otp_debug::blk2_w6::BLOCK2_W6_R
• otp_debug::blk2_w6::R
• otp_debug::blk2_w7::BLOCK2_W7_R
• otp_debug::blk2_w7::R
• otp_debug::blk2_w8::BLOCK2_W8_R
• otp_debug::blk2_w8::R
• otp_debug::blk2_w9::BLOCK2_W9_R
• otp_debug::blk2_w9::R
• otp_debug::blk3_w10::BLOCK3_W10_R
• otp_debug::blk3_w10::R
• otp_debug::blk3_w11::BLOCK3_W11_R
• otp_debug::blk3_w11::R
• otp_debug::blk3_w1::BLOCK3_W1_R
• otp_debug::blk3_w1::R
• otp_debug::blk3_w2::BLOCK3_W2_R
• otp_debug::blk3_w2::R
• otp_debug::blk3_w3::BLOCK3_W3_R
• otp_debug::blk3_w3::R
• otp_debug::blk3_w4::BLOCK3_W4_R
• otp_debug::blk3_w4::R
• otp_debug::blk3_w5::BLOCK3_W5_R
• otp_debug::blk3_w5::R
• otp_debug::blk3_w6::BLOCK3_W6_R
• otp_debug::blk3_w6::R
• otp_debug::blk3_w7::BLOCK3_W7_R
• otp_debug::blk3_w7::R
• otp_debug::blk3_w8::BLOCK3_W8_R
• otp_debug::blk3_w8::R
• otp_debug::blk3_w9::BLOCK3_W9_R
• otp_debug::blk3_w9::R
• otp_debug::blk4_w10::BLOCK4_W10_R
• otp_debug::blk4_w10::R
• otp_debug::blk4_w11::BLOCK4_W11_R
• otp_debug::blk4_w11::R
• otp_debug::blk4_w1::BLOCK4_W1_R
• otp_debug::blk4_w1::R
• otp_debug::blk4_w2::BLOCK4_W2_R
• otp_debug::blk4_w2::R
• otp_debug::blk4_w3::BLOCK4_W3_R
• otp_debug::blk4_w3::R
• otp_debug::blk4_w4::BLOCK4_W4_R
• otp_debug::blk4_w4::R
• otp_debug::blk4_w5::BLOCK4_W5_R
• otp_debug::blk4_w5::R
• otp_debug::blk4_w6::BLOCK4_W6_R
• otp_debug::blk4_w6::R
• otp_debug::blk4_w7::BLOCK4_W7_R
• otp_debug::blk4_w7::R
• otp_debug::blk4_w8::BLOCK4_W8_R
• otp_debug::blk4_w8::R
• otp_debug::blk4_w9::BLOCK4_W9_R
• otp_debug::blk4_w9::R
• otp_debug::blk5_w10::BLOCK5_W10_R
• otp_debug::blk5_w10::R
• otp_debug::blk5_w11::BLOCK5_W11_R
• otp_debug::blk5_w11::R
• otp_debug::blk5_w1::BLOCK5_W1_R
• otp_debug::blk5_w1::R
• otp_debug::blk5_w2::BLOCK5_W2_R
• otp_debug::blk5_w2::R
• otp_debug::blk5_w3::BLOCK5_W3_R
• otp_debug::blk5_w3::R
• otp_debug::blk5_w4::BLOCK5_W4_R
• otp_debug::blk5_w4::R
• otp_debug::blk5_w5::BLOCK5_W5_R
• otp_debug::blk5_w5::R
• otp_debug::blk5_w6::BLOCK5_W6_R
• otp_debug::blk5_w6::R
• otp_debug::blk5_w7::BLOCK5_W7_R
• otp_debug::blk5_w7::R
• otp_debug::blk5_w8::BLOCK5_W8_R
• otp_debug::blk5_w8::R
• otp_debug::blk5_w9::BLOCK5_W9_R
• otp_debug::blk5_w9::R
• otp_debug::blk6_w10::BLOCK6_W10_R
• otp_debug::blk6_w10::R
• otp_debug::blk6_w11::BLOCK6_W11_R
• otp_debug::blk6_w11::R
• otp_debug::blk6_w1::BLOCK6_W1_R
• otp_debug::blk6_w1::R
• otp_debug::blk6_w2::BLOCK6_W2_R
• otp_debug::blk6_w2::R
• otp_debug::blk6_w3::BLOCK6_W3_R
• otp_debug::blk6_w3::R
• otp_debug::blk6_w4::BLOCK6_W4_R
• otp_debug::blk6_w4::R
• otp_debug::blk6_w5::BLOCK6_W5_R
• otp_debug::blk6_w5::R
• otp_debug::blk6_w6::BLOCK6_W6_R
• otp_debug::blk6_w6::R
• otp_debug::blk6_w7::BLOCK6_W7_R
• otp_debug::blk6_w7::R
• otp_debug::blk6_w8::BLOCK6_W8_R
• otp_debug::blk6_w8::R
• otp_debug::blk6_w9::BLOCK6_W9_R
• otp_debug::blk6_w9::R
• otp_debug::blk7_w10::BLOCK7_W10_R
• otp_debug::blk7_w10::R
• otp_debug::blk7_w11::BLOCK7_W11_R
• otp_debug::blk7_w11::R
• otp_debug::blk7_w1::BLOCK7_W1_R
• otp_debug::blk7_w1::R
• otp_debug::blk7_w2::BLOCK7_W2_R
• otp_debug::blk7_w2::R
• otp_debug::blk7_w3::BLOCK7_W3_R
• otp_debug::blk7_w3::R
• otp_debug::blk7_w4::BLOCK7_W4_R
• otp_debug::blk7_w4::R
• otp_debug::blk7_w5::BLOCK7_W5_R
• otp_debug::blk7_w5::R
• otp_debug::blk7_w6::BLOCK7_W6_R
• otp_debug::blk7_w6::R
• otp_debug::blk7_w7::BLOCK7_W7_R
• otp_debug::blk7_w7::R
• otp_debug::blk7_w8::BLOCK7_W8_R
• otp_debug::blk7_w8::R
• otp_debug::blk7_w9::BLOCK7_W9_R
• otp_debug::blk7_w9::R
• otp_debug::blk8_w10::BLOCK8_W10_R
• otp_debug::blk8_w10::R
• otp_debug::blk8_w11::BLOCK8_W11_R
• otp_debug::blk8_w11::R
• otp_debug::blk8_w1::BLOCK8_W1_R
• otp_debug::blk8_w1::R
• otp_debug::blk8_w2::BLOCK8_W2_R
• otp_debug::blk8_w2::R
• otp_debug::blk8_w3::BLOCK8_W3_R
• otp_debug::blk8_w3::R
• otp_debug::blk8_w4::BLOCK8_W4_R
• otp_debug::blk8_w4::R
• otp_debug::blk8_w5::BLOCK8_W5_R
• otp_debug::blk8_w5::R
• otp_debug::blk8_w6::BLOCK8_W6_R
• otp_debug::blk8_w6::R
• otp_debug::blk8_w7::BLOCK8_W7_R
• otp_debug::blk8_w7::R
• otp_debug::blk8_w8::BLOCK8_W8_R
• otp_debug::blk8_w8::R
• otp_debug::blk8_w9::BLOCK8_W9_R
• otp_debug::blk8_w9::R
• otp_debug::blk9_w10::BLOCK9_W10_R
• otp_debug::blk9_w10::R
• otp_debug::blk9_w11::BLOCK9_W11_R
• otp_debug::blk9_w11::R
• otp_debug::blk9_w1::BLOCK9_W1_R
• otp_debug::blk9_w1::R
• otp_debug::blk9_w2::BLOCK9_W2_R
• otp_debug::blk9_w2::R
• otp_debug::blk9_w3::BLOCK9_W3_R
• otp_debug::blk9_w3::R
• otp_debug::blk9_w4::BLOCK9_W4_R
• otp_debug::blk9_w4::R
• otp_debug::blk9_w5::BLOCK9_W5_R
• otp_debug::blk9_w5::R
• otp_debug::blk9_w6::BLOCK9_W6_R
• otp_debug::blk9_w6::R
• otp_debug::blk9_w7::BLOCK9_W7_R
• otp_debug::blk9_w7::R
• otp_debug::blk9_w8::BLOCK9_W8_R
• otp_debug::blk9_w8::R
• otp_debug::blk9_w9::BLOCK9_W9_R
• otp_debug::blk9_w9::R
• otp_debug::clk::EN_R
• otp_debug::clk::EN_W
• otp_debug::clk::R
• otp_debug::clk::W
• otp_debug::date::DATE_R
• otp_debug::date::DATE_W
• otp_debug::date::R
• otp_debug::date::W
• otp_debug::wr_dis::BLOCK0_WR_DIS_R
• otp_debug::wr_dis::R
• parl_io::CLK
• parl_io::INT_CLR
• parl_io::INT_ENA
• parl_io::INT_RAW
• parl_io::INT_ST
• parl_io::RX_CFG0
• parl_io::RX_CFG1
• parl_io::ST
• parl_io::TX_CFG0
• parl_io::TX_CFG1
• parl_io::VERSION
• parl_io::clk::EN_R
• parl_io::clk::EN_W
• parl_io::clk::R
• parl_io::clk::W
• parl_io::int_clr::RX_FIFO_WOVF_W
• parl_io::int_clr::TX_EOF_W
• parl_io::int_clr::TX_FIFO_REMPTY_W
• parl_io::int_clr::W
• parl_io::int_ena::R
• parl_io::int_ena::RX_FIFO_WOVF_R
• parl_io::int_ena::RX_FIFO_WOVF_W
• parl_io::int_ena::TX_EOF_R
• parl_io::int_ena::TX_EOF_W
• parl_io::int_ena::TX_FIFO_REMPTY_R
• parl_io::int_ena::TX_FIFO_REMPTY_W
• parl_io::int_ena::W
• parl_io::int_raw::R
• parl_io::int_raw::RX_FIFO_WOVF_R
• parl_io::int_raw::RX_FIFO_WOVF_W
• parl_io::int_raw::TX_EOF_R
• parl_io::int_raw::TX_EOF_W
• parl_io::int_raw::TX_FIFO_REMPTY_R
• parl_io::int_raw::TX_FIFO_REMPTY_W
• parl_io::int_raw::W
• parl_io::int_st::R
• parl_io::int_st::RX_FIFO_WOVF_R
• parl_io::int_st::TX_EOF_R
• parl_io::int_st::TX_FIFO_REMPTY_R
• parl_io::rx_cfg0::R
• parl_io::rx_cfg0::RX_BIT_PACK_ORDER_R
• parl_io::rx_cfg0::RX_BIT_PACK_ORDER_W
• parl_io::rx_cfg0::RX_BUS_WID_SEL_R
• parl_io::rx_cfg0::RX_BUS_WID_SEL_W
• parl_io::rx_cfg0::RX_CLK_EDGE_SEL_R
• parl_io::rx_cfg0::RX_CLK_EDGE_SEL_W
• parl_io::rx_cfg0::RX_DATA_BYTELEN_R
• parl_io::rx_cfg0::RX_DATA_BYTELEN_W
• parl_io::rx_cfg0::RX_EOF_GEN_SEL_R
• parl_io::rx_cfg0::RX_EOF_GEN_SEL_W
• parl_io::rx_cfg0::RX_FIFO_SRST_R
• parl_io::rx_cfg0::RX_FIFO_SRST_W
• parl_io::rx_cfg0::RX_LEVEL_SUBMODE_SEL_R
• parl_io::rx_cfg0::RX_LEVEL_SUBMODE_SEL_W
• parl_io::rx_cfg0::RX_PULSE_SUBMODE_SEL_R
• parl_io::rx_cfg0::RX_PULSE_SUBMODE_SEL_W
• parl_io::rx_cfg0::RX_SMP_MODE_SEL_R
• parl_io::rx_cfg0::RX_SMP_MODE_SEL_W
• parl_io::rx_cfg0::RX_START_R
• parl_io::rx_cfg0::RX_START_W
• parl_io::rx_cfg0::RX_SW_EN_R
• parl_io::rx_cfg0::RX_SW_EN_W
• parl_io::rx_cfg0::W
• parl_io::rx_cfg1::R
• parl_io::rx_cfg1::RX_EXT_EN_SEL_R
• parl_io::rx_cfg1::RX_EXT_EN_SEL_W
• parl_io::rx_cfg1::RX_REG_UPDATE_W
• parl_io::rx_cfg1::RX_TIMEOUT_EN_R
• parl_io::rx_cfg1::RX_TIMEOUT_EN_W
• parl_io::rx_cfg1::RX_TIMEOUT_THRESHOLD_R
• parl_io::rx_cfg1::RX_TIMEOUT_THRESHOLD_W
• parl_io::rx_cfg1::W
• parl_io::st::R
• parl_io::st::TX_READY_R
• parl_io::tx_cfg0::R
• parl_io::tx_cfg0::TX_BIT_UNPACK_ORDER_R
• parl_io::tx_cfg0::TX_BIT_UNPACK_ORDER_W
• parl_io::tx_cfg0::TX_BUS_WID_SEL_R
• parl_io::tx_cfg0::TX_BUS_WID_SEL_W
• parl_io::tx_cfg0::TX_BYTELEN_R
• parl_io::tx_cfg0::TX_BYTELEN_W
• parl_io::tx_cfg0::TX_FIFO_SRST_R
• parl_io::tx_cfg0::TX_FIFO_SRST_W
• parl_io::tx_cfg0::TX_GATING_EN_R
• parl_io::tx_cfg0::TX_GATING_EN_W
• parl_io::tx_cfg0::TX_HW_VALID_EN_R
• parl_io::tx_cfg0::TX_HW_VALID_EN_W
• parl_io::tx_cfg0::TX_SMP_EDGE_SEL_R
• parl_io::tx_cfg0::TX_SMP_EDGE_SEL_W
• parl_io::tx_cfg0::TX_START_R
• parl_io::tx_cfg0::TX_START_W
• parl_io::tx_cfg0::W
• parl_io::tx_cfg1::R
• parl_io::tx_cfg1::TX_IDLE_VALUE_R
• parl_io::tx_cfg1::TX_IDLE_VALUE_W
• parl_io::tx_cfg1::W
• parl_io::version::DATE_R
• parl_io::version::DATE_W
• parl_io::version::R
• parl_io::version::W
• pau::DATE
• pau::INT_CLR
• pau::INT_ENA
• pau::INT_RAW
• pau::INT_ST
• pau::REGDMA_BACKUP_ADDR
• pau::REGDMA_BKP_CONF
• pau::REGDMA_CLK_CONF
• pau::REGDMA_CONF
• pau::REGDMA_CURRENT_LINK_ADDR
• pau::REGDMA_ETM_CTRL
• pau::REGDMA_LINK_0_ADDR
• pau::REGDMA_LINK_1_ADDR
• pau::REGDMA_LINK_2_ADDR
• pau::REGDMA_LINK_3_ADDR
• pau::REGDMA_LINK_MAC_ADDR
• pau::REGDMA_MEM_ADDR
• pau::RETENTION_CFG
• pau::RETENTION_LINK_BASE
• pau::date::DATE_R
• pau::date::DATE_W
• pau::date::R
• pau::date::W
• pau::int_clr::DONE_W
• pau::int_clr::ERROR_W
• pau::int_clr::W
• pau::int_ena::DONE_R
• pau::int_ena::DONE_W
• pau::int_ena::ERROR_R
• pau::int_ena::ERROR_W
• pau::int_ena::R
• pau::int_ena::W
• pau::int_raw::DONE_R
• pau::int_raw::DONE_W
• pau::int_raw::ERROR_R
• pau::int_raw::ERROR_W
• pau::int_raw::R
• pau::int_raw::W
• pau::int_st::DONE_R
• pau::int_st::ERROR_R
• pau::int_st::R
• pau::regdma_backup_addr::BACKUP_ADDR_R
• pau::regdma_backup_addr::R
• pau::regdma_bkp_conf::BACKUP_TOUT_THRES_R
• pau::regdma_bkp_conf::BACKUP_TOUT_THRES_W
• pau::regdma_bkp_conf::BURST_LIMIT_R
• pau::regdma_bkp_conf::BURST_LIMIT_W
• pau::regdma_bkp_conf::LINK_TOUT_THRES_R
• pau::regdma_bkp_conf::LINK_TOUT_THRES_W
• pau::regdma_bkp_conf::R
• pau::regdma_bkp_conf::READ_INTERVAL_R
• pau::regdma_bkp_conf::READ_INTERVAL_W
• pau::regdma_bkp_conf::W
• pau::regdma_clk_conf::CLK_EN_R
• pau::regdma_clk_conf::CLK_EN_W
• pau::regdma_clk_conf::R
• pau::regdma_clk_conf::W
• pau::regdma_conf::FLOW_ERR_R
• pau::regdma_conf::LINK_SEL_R
• pau::regdma_conf::LINK_SEL_W
• pau::regdma_conf::R
• pau::regdma_conf::SEL_MAC_R
• pau::regdma_conf::SEL_MAC_W
• pau::regdma_conf::START_MAC_W
• pau::regdma_conf::START_W
• pau::regdma_conf::TO_MEM_MAC_R
• pau::regdma_conf::TO_MEM_MAC_W
• pau::regdma_conf::TO_MEM_R
• pau::regdma_conf::TO_MEM_W
• pau::regdma_conf::W
• pau::regdma_current_link_addr::CURRENT_LINK_ADDR_R
• pau::regdma_current_link_addr::R
• pau::regdma_etm_ctrl::ETM_START_0_W
• pau::regdma_etm_ctrl::ETM_START_1_W
• pau::regdma_etm_ctrl::ETM_START_2_W
• pau::regdma_etm_ctrl::ETM_START_3_W
• pau::regdma_etm_ctrl::W
• pau::regdma_link_0_addr::LINK_ADDR_0_R
• pau::regdma_link_0_addr::LINK_ADDR_0_W
• pau::regdma_link_0_addr::R
• pau::regdma_link_0_addr::W
• pau::regdma_link_1_addr::LINK_ADDR_1_R
• pau::regdma_link_1_addr::LINK_ADDR_1_W
• pau::regdma_link_1_addr::R
• pau::regdma_link_1_addr::W
• pau::regdma_link_2_addr::LINK_ADDR_2_R
• pau::regdma_link_2_addr::LINK_ADDR_2_W
• pau::regdma_link_2_addr::R
• pau::regdma_link_2_addr::W
• pau::regdma_link_3_addr::LINK_ADDR_3_R
• pau::regdma_link_3_addr::LINK_ADDR_3_W
• pau::regdma_link_3_addr::R
• pau::regdma_link_3_addr::W
• pau::regdma_link_mac_addr::LINK_ADDR_MAC_R
• pau::regdma_link_mac_addr::LINK_ADDR_MAC_W
• pau::regdma_link_mac_addr::R
• pau::regdma_link_mac_addr::W
• pau::regdma_mem_addr::MEM_ADDR_R
• pau::regdma_mem_addr::R
• pau::retention_cfg::R
• pau::retention_cfg::RET_INV_CFG_R
• pau::retention_cfg::RET_INV_CFG_W
• pau::retention_cfg::W
• pau::retention_link_base::LINK_BASE_ADDR_R
• pau::retention_link_base::LINK_BASE_ADDR_W
• pau::retention_link_base::R
• pau::retention_link_base::W
• pcnt::CTRL
• pcnt::DATE
• pcnt::INT_CLR
• pcnt::INT_ENA
• pcnt::INT_RAW
• pcnt::INT_ST
• pcnt::U_CNT
• pcnt::U_STATUS
• pcnt::ctrl::CLK_EN_R
• pcnt::ctrl::CLK_EN_W
• pcnt::ctrl::CNT_PAUSE_U_R
• pcnt::ctrl::CNT_PAUSE_U_W
• pcnt::ctrl::CNT_RST_U_R
• pcnt::ctrl::CNT_RST_U_W
• pcnt::ctrl::R
• pcnt::ctrl::W
• pcnt::date::DATE_R
• pcnt::date::DATE_W
• pcnt::date::R
• pcnt::date::W
• pcnt::int_clr::CNT_THR_EVENT_U_W
• pcnt::int_clr::W
• pcnt::int_ena::CNT_THR_EVENT_U_R
• pcnt::int_ena::CNT_THR_EVENT_U_W
• pcnt::int_ena::R
• pcnt::int_ena::W
• pcnt::int_raw::CNT_THR_EVENT_U_R
• pcnt::int_raw::R
• pcnt::int_st::CNT_THR_EVENT_U_R
• pcnt::int_st::R
• pcnt::u_cnt::CNT_R
• pcnt::u_cnt::R
• pcnt::u_status::H_LIM_R
• pcnt::u_status::L_LIM_R
• pcnt::u_status::R
• pcnt::u_status::THRES0_R
• pcnt::u_status::THRES1_R
• pcnt::u_status::ZERO_MODE_R
• pcnt::u_status::ZERO_R
• pcnt::unit::CONF0
• pcnt::unit::CONF1
• pcnt::unit::CONF2
• pcnt::unit::conf0::CH_HCTRL_MODE_R
• pcnt::unit::conf0::CH_HCTRL_MODE_W
• pcnt::unit::conf0::CH_NEG_MODE_R
• pcnt::unit::conf0::CH_NEG_MODE_W
• pcnt::unit::conf0::FILTER_EN_R
• pcnt::unit::conf0::FILTER_EN_W
• pcnt::unit::conf0::FILTER_THRES_R
• pcnt::unit::conf0::FILTER_THRES_W
• pcnt::unit::conf0::R
• pcnt::unit::conf0::THR_H_LIM_EN_R
• pcnt::unit::conf0::THR_H_LIM_EN_W
• pcnt::unit::conf0::THR_L_LIM_EN_R
• pcnt::unit::conf0::THR_L_LIM_EN_W
• pcnt::unit::conf0::THR_THRES0_EN_R
• pcnt::unit::conf0::THR_THRES0_EN_W
• pcnt::unit::conf0::THR_THRES1_EN_R
• pcnt::unit::conf0::THR_THRES1_EN_W
• pcnt::unit::conf0::THR_ZERO_EN_R
• pcnt::unit::conf0::THR_ZERO_EN_W
• pcnt::unit::conf0::W
• pcnt::unit::conf1::CNT_THRES0_R
• pcnt::unit::conf1::CNT_THRES0_W
• pcnt::unit::conf1::CNT_THRES1_R
• pcnt::unit::conf1::CNT_THRES1_W
• pcnt::unit::conf1::R
• pcnt::unit::conf1::W
• pcnt::unit::conf2::CNT_H_LIM_R
• pcnt::unit::conf2::CNT_H_LIM_W
• pcnt::unit::conf2::CNT_L_LIM_R
• pcnt::unit::conf2::CNT_L_LIM_W
• pcnt::unit::conf2::R
• pcnt::unit::conf2::W
• pcr::AES_CONF
• pcr::AHB_FREQ_CONF
• pcr::APB_FREQ_CONF
• pcr::ASSIST_CONF
• pcr::CACHE_CONF
• pcr::CLOCK_GATE
• pcr::CPU_FREQ_CONF
• pcr::CPU_WAITI_CONF
• pcr::CTRL_32K_CONF
• pcr::CTRL_CLK_OUT_EN
• pcr::CTRL_TICK_CONF
• pcr::DATE
• pcr::DS_CONF
• pcr::ECC_CONF
• pcr::ECC_PD_CTRL
• pcr::ETM_CONF
• pcr::FPGA_DEBUG
• pcr::GDMA_CONF
• pcr::HMAC_CONF
• pcr::I2C0_CONF
• pcr::I2C_SCLK_CONF
• pcr::I2S_CONF
• pcr::I2S_RX_CLKM_CONF
• pcr::I2S_RX_CLKM_DIV_CONF
• pcr::I2S_TX_CLKM_CONF
• pcr::I2S_TX_CLKM_DIV_CONF
• pcr::INTMTX_CONF
• pcr::IOMUX_CLK_CONF
• pcr::IOMUX_CONF
• pcr::LEDC_CONF
• pcr::LEDC_SCLK_CONF
• pcr::MEM_MONITOR_CONF
• pcr::MODEM_APB_CONF
• pcr::MSPI_CLK_CONF
• pcr::MSPI_CONF
• pcr::PARL_CLK_RX_CONF
• pcr::PARL_CLK_TX_CONF
• pcr::PARL_IO_CONF
• pcr::PCNT_CONF
• pcr::PLL_DIV_CLK_EN
• pcr::PVT_MONITOR_CONF
• pcr::PVT_MONITOR_FUNC_CLK_CONF
• pcr::PWM_CLK_CONF
• pcr::PWM_CONF
• pcr::REGDMA_CONF
• pcr::RESET_EVENT_BYPASS
• pcr::RETENTION_CONF
• pcr::RMT_CONF
• pcr::RMT_SCLK_CONF
• pcr::RSA_CONF
• pcr::RSA_PD_CTRL
• pcr::SARADC_CLKM_CONF
• pcr::SARADC_CONF
• pcr::SDIO_SLAVE_CONF
• pcr::SHA_CONF
• pcr::SPI2_CLKM_CONF
• pcr::SPI2_CONF
• pcr::SRAM_POWER_CONF
• pcr::SYSCLK_CONF
• pcr::SYSCLK_FREQ_QUERY_0
• pcr::SYSTIMER_CONF
• pcr::SYSTIMER_FUNC_CLK_CONF
• pcr::TIMEOUT_CONF
• pcr::TIMERGROUP0_CONF
• pcr::TIMERGROUP0_TIMER_CLK_CONF
• pcr::TIMERGROUP0_WDT_CLK_CONF
• pcr::TIMERGROUP1_CONF
• pcr::TIMERGROUP1_TIMER_CLK_CONF
• pcr::TIMERGROUP1_WDT_CLK_CONF
• pcr::TRACE_CONF
• pcr::TSENS_CLK_CONF
• pcr::TWAI0_CONF
• pcr::TWAI0_FUNC_CLK_CONF
• pcr::TWAI1_CONF
• pcr::TWAI1_FUNC_CLK_CONF
• pcr::UHCI_CONF
• pcr::USB_DEVICE_CONF
• pcr::aes_conf::AES_CLK_EN_R
• pcr::aes_conf::AES_CLK_EN_W
• pcr::aes_conf::AES_RST_EN_R
• pcr::aes_conf::AES_RST_EN_W
• pcr::aes_conf::R
• pcr::aes_conf::W
• pcr::ahb_freq_conf::AHB_HS_DIV_NUM_R
• pcr::ahb_freq_conf::AHB_HS_DIV_NUM_W
• pcr::ahb_freq_conf::AHB_LS_DIV_NUM_R
• pcr::ahb_freq_conf::AHB_LS_DIV_NUM_W
• pcr::ahb_freq_conf::R
• pcr::ahb_freq_conf::W
• pcr::apb_freq_conf::APB_DECREASE_DIV_NUM_R
• pcr::apb_freq_conf::APB_DECREASE_DIV_NUM_W
• pcr::apb_freq_conf::APB_DIV_NUM_R
• pcr::apb_freq_conf::APB_DIV_NUM_W
• pcr::apb_freq_conf::R
• pcr::apb_freq_conf::W
• pcr::assist_conf::ASSIST_CLK_EN_R
• pcr::assist_conf::ASSIST_CLK_EN_W
• pcr::assist_conf::ASSIST_RST_EN_R
• pcr::assist_conf::ASSIST_RST_EN_W
• pcr::assist_conf::R
• pcr::assist_conf::W
• pcr::cache_conf::CACHE_CLK_EN_R
• pcr::cache_conf::CACHE_CLK_EN_W
• pcr::cache_conf::CACHE_RST_EN_R
• pcr::cache_conf::CACHE_RST_EN_W
• pcr::cache_conf::R
• pcr::cache_conf::W
• pcr::clock_gate::CLK_EN_R
• pcr::clock_gate::CLK_EN_W
• pcr::clock_gate::R
• pcr::clock_gate::W
• pcr::cpu_freq_conf::CPU_HS_120M_FORCE_R
• pcr::cpu_freq_conf::CPU_HS_120M_FORCE_W
• pcr::cpu_freq_conf::CPU_HS_DIV_NUM_R
• pcr::cpu_freq_conf::CPU_HS_DIV_NUM_W
• pcr::cpu_freq_conf::CPU_LS_DIV_NUM_R
• pcr::cpu_freq_conf::CPU_LS_DIV_NUM_W
• pcr::cpu_freq_conf::R
• pcr::cpu_freq_conf::W
• pcr::cpu_waiti_conf::CPUPERIOD_SEL_R
• pcr::cpu_waiti_conf::CPU_WAITI_DELAY_NUM_R
• pcr::cpu_waiti_conf::CPU_WAITI_DELAY_NUM_W
• pcr::cpu_waiti_conf::CPU_WAIT_MODE_FORCE_ON_R
• pcr::cpu_waiti_conf::CPU_WAIT_MODE_FORCE_ON_W
• pcr::cpu_waiti_conf::PLL_FREQ_SEL_R
• pcr::cpu_waiti_conf::R
• pcr::cpu_waiti_conf::W
• pcr::ctrl_32k_conf::CLK_32K_SEL_R
• pcr::ctrl_32k_conf::CLK_32K_SEL_W
• pcr::ctrl_32k_conf::R
• pcr::ctrl_32k_conf::W
• pcr::ctrl_clk_out_en::CLK160_OEN_R
• pcr::ctrl_clk_out_en::CLK160_OEN_W
• pcr::ctrl_clk_out_en::CLK20_OEN_R
• pcr::ctrl_clk_out_en::CLK20_OEN_W
• pcr::ctrl_clk_out_en::CLK22_OEN_R
• pcr::ctrl_clk_out_en::CLK22_OEN_W
• pcr::ctrl_clk_out_en::CLK40X_BB_OEN_R
• pcr::ctrl_clk_out_en::CLK40X_BB_OEN_W
• pcr::ctrl_clk_out_en::CLK44_OEN_R
• pcr::ctrl_clk_out_en::CLK44_OEN_W
• pcr::ctrl_clk_out_en::CLK80_OEN_R
• pcr::ctrl_clk_out_en::CLK80_OEN_W
• pcr::ctrl_clk_out_en::CLK_320M_OEN_R
• pcr::ctrl_clk_out_en::CLK_320M_OEN_W
• pcr::ctrl_clk_out_en::CLK_ADC_INF_OEN_R
• pcr::ctrl_clk_out_en::CLK_ADC_INF_OEN_W
• pcr::ctrl_clk_out_en::CLK_BB_OEN_R
• pcr::ctrl_clk_out_en::CLK_BB_OEN_W
• pcr::ctrl_clk_out_en::CLK_DAC_CPU_OEN_R
• pcr::ctrl_clk_out_en::CLK_DAC_CPU_OEN_W
• pcr::ctrl_clk_out_en::CLK_XTAL_OEN_R
• pcr::ctrl_clk_out_en::CLK_XTAL_OEN_W
• pcr::ctrl_clk_out_en::R
• pcr::ctrl_clk_out_en::W
• pcr::ctrl_tick_conf::FOSC_TICK_NUM_R
• pcr::ctrl_tick_conf::FOSC_TICK_NUM_W
• pcr::ctrl_tick_conf::R
• pcr::ctrl_tick_conf::RST_TICK_CNT_R
• pcr::ctrl_tick_conf::RST_TICK_CNT_W
• pcr::ctrl_tick_conf::TICK_ENABLE_R
• pcr::ctrl_tick_conf::TICK_ENABLE_W
• pcr::ctrl_tick_conf::W
• pcr::ctrl_tick_conf::XTAL_TICK_NUM_R
• pcr::ctrl_tick_conf::XTAL_TICK_NUM_W
• pcr::date::DATE_R
• pcr::date::DATE_W
• pcr::date::R
• pcr::date::W
• pcr::ds_conf::DS_CLK_EN_R
• pcr::ds_conf::DS_CLK_EN_W
• pcr::ds_conf::DS_RST_EN_R
• pcr::ds_conf::DS_RST_EN_W
• pcr::ds_conf::R
• pcr::ds_conf::W
• pcr::ecc_conf::ECC_CLK_EN_R
• pcr::ecc_conf::ECC_CLK_EN_W
• pcr::ecc_conf::ECC_RST_EN_R
• pcr::ecc_conf::ECC_RST_EN_W
• pcr::ecc_conf::R
• pcr::ecc_conf::W
• pcr::ecc_pd_ctrl::ECC_MEM_FORCE_PD_R
• pcr::ecc_pd_ctrl::ECC_MEM_FORCE_PD_W
• pcr::ecc_pd_ctrl::ECC_MEM_FORCE_PU_R
• pcr::ecc_pd_ctrl::ECC_MEM_FORCE_PU_W
• pcr::ecc_pd_ctrl::ECC_MEM_PD_R
• pcr::ecc_pd_ctrl::ECC_MEM_PD_W
• pcr::ecc_pd_ctrl::R
• pcr::ecc_pd_ctrl::W
• pcr::etm_conf::ETM_CLK_EN_R
• pcr::etm_conf::ETM_CLK_EN_W
• pcr::etm_conf::ETM_RST_EN_R
• pcr::etm_conf::ETM_RST_EN_W
• pcr::etm_conf::R
• pcr::etm_conf::W
• pcr::fpga_debug::FPGA_DEBUG_R
• pcr::fpga_debug::FPGA_DEBUG_W
• pcr::fpga_debug::R
• pcr::fpga_debug::W
• pcr::gdma_conf::GDMA_CLK_EN_R
• pcr::gdma_conf::GDMA_CLK_EN_W
• pcr::gdma_conf::GDMA_RST_EN_R
• pcr::gdma_conf::GDMA_RST_EN_W
• pcr::gdma_conf::R
• pcr::gdma_conf::W
• pcr::hmac_conf::HMAC_CLK_EN_R
• pcr::hmac_conf::HMAC_CLK_EN_W
• pcr::hmac_conf::HMAC_RST_EN_R
• pcr::hmac_conf::HMAC_RST_EN_W
• pcr::hmac_conf::R
• pcr::hmac_conf::W
• pcr::i2c0_conf::I2C0_CLK_EN_R
• pcr::i2c0_conf::I2C0_CLK_EN_W
• pcr::i2c0_conf::I2C0_RST_EN_R
• pcr::i2c0_conf::I2C0_RST_EN_W
• pcr::i2c0_conf::R
• pcr::i2c0_conf::W
• pcr::i2c_sclk_conf::I2C_SCLK_DIV_A_R
• pcr::i2c_sclk_conf::I2C_SCLK_DIV_A_W
• pcr::i2c_sclk_conf::I2C_SCLK_DIV_B_R
• pcr::i2c_sclk_conf::I2C_SCLK_DIV_B_W
• pcr::i2c_sclk_conf::I2C_SCLK_DIV_NUM_R
• pcr::i2c_sclk_conf::I2C_SCLK_DIV_NUM_W
• pcr::i2c_sclk_conf::I2C_SCLK_EN_R
• pcr::i2c_sclk_conf::I2C_SCLK_EN_W
• pcr::i2c_sclk_conf::I2C_SCLK_SEL_R
• pcr::i2c_sclk_conf::I2C_SCLK_SEL_W
• pcr::i2c_sclk_conf::R
• pcr::i2c_sclk_conf::W
• pcr::i2s_conf::I2S_CLK_EN_R
• pcr::i2s_conf::I2S_CLK_EN_W
• pcr::i2s_conf::I2S_RST_EN_R
• pcr::i2s_conf::I2S_RST_EN_W
• pcr::i2s_conf::R
• pcr::i2s_conf::W
• pcr::i2s_rx_clkm_conf::I2S_MCLK_SEL_R
• pcr::i2s_rx_clkm_conf::I2S_MCLK_SEL_W
• pcr::i2s_rx_clkm_conf::I2S_RX_CLKM_DIV_NUM_R
• pcr::i2s_rx_clkm_conf::I2S_RX_CLKM_DIV_NUM_W
• pcr::i2s_rx_clkm_conf::I2S_RX_CLKM_EN_R
• pcr::i2s_rx_clkm_conf::I2S_RX_CLKM_EN_W
• pcr::i2s_rx_clkm_conf::I2S_RX_CLKM_SEL_R
• pcr::i2s_rx_clkm_conf::I2S_RX_CLKM_SEL_W
• pcr::i2s_rx_clkm_conf::R
• pcr::i2s_rx_clkm_conf::W
• pcr::i2s_rx_clkm_div_conf::I2S_RX_CLKM_DIV_X_R
• pcr::i2s_rx_clkm_div_conf::I2S_RX_CLKM_DIV_X_W
• pcr::i2s_rx_clkm_div_conf::I2S_RX_CLKM_DIV_YN1_R
• pcr::i2s_rx_clkm_div_conf::I2S_RX_CLKM_DIV_YN1_W
• pcr::i2s_rx_clkm_div_conf::I2S_RX_CLKM_DIV_Y_R
• pcr::i2s_rx_clkm_div_conf::I2S_RX_CLKM_DIV_Y_W
• pcr::i2s_rx_clkm_div_conf::I2S_RX_CLKM_DIV_Z_R
• pcr::i2s_rx_clkm_div_conf::I2S_RX_CLKM_DIV_Z_W
• pcr::i2s_rx_clkm_div_conf::R
• pcr::i2s_rx_clkm_div_conf::W
• pcr::i2s_tx_clkm_conf::I2S_TX_CLKM_DIV_NUM_R
• pcr::i2s_tx_clkm_conf::I2S_TX_CLKM_DIV_NUM_W
• pcr::i2s_tx_clkm_conf::I2S_TX_CLKM_EN_R
• pcr::i2s_tx_clkm_conf::I2S_TX_CLKM_EN_W
• pcr::i2s_tx_clkm_conf::I2S_TX_CLKM_SEL_R
• pcr::i2s_tx_clkm_conf::I2S_TX_CLKM_SEL_W
• pcr::i2s_tx_clkm_conf::R
• pcr::i2s_tx_clkm_conf::W
• pcr::i2s_tx_clkm_div_conf::I2S_TX_CLKM_DIV_X_R
• pcr::i2s_tx_clkm_div_conf::I2S_TX_CLKM_DIV_X_W
• pcr::i2s_tx_clkm_div_conf::I2S_TX_CLKM_DIV_YN1_R
• pcr::i2s_tx_clkm_div_conf::I2S_TX_CLKM_DIV_YN1_W
• pcr::i2s_tx_clkm_div_conf::I2S_TX_CLKM_DIV_Y_R
• pcr::i2s_tx_clkm_div_conf::I2S_TX_CLKM_DIV_Y_W
• pcr::i2s_tx_clkm_div_conf::I2S_TX_CLKM_DIV_Z_R
• pcr::i2s_tx_clkm_div_conf::I2S_TX_CLKM_DIV_Z_W
• pcr::i2s_tx_clkm_div_conf::R
• pcr::i2s_tx_clkm_div_conf::W
• pcr::intmtx_conf::INTMTX_CLK_EN_R
• pcr::intmtx_conf::INTMTX_CLK_EN_W
• pcr::intmtx_conf::INTMTX_RST_EN_R
• pcr::intmtx_conf::INTMTX_RST_EN_W
• pcr::intmtx_conf::R
• pcr::intmtx_conf::W
• pcr::iomux_clk_conf::IOMUX_FUNC_CLK_EN_R
• pcr::iomux_clk_conf::IOMUX_FUNC_CLK_EN_W
• pcr::iomux_clk_conf::IOMUX_FUNC_CLK_SEL_R
• pcr::iomux_clk_conf::IOMUX_FUNC_CLK_SEL_W
• pcr::iomux_clk_conf::R
• pcr::iomux_clk_conf::W
• pcr::iomux_conf::IOMUX_CLK_EN_R
• pcr::iomux_conf::IOMUX_CLK_EN_W
• pcr::iomux_conf::IOMUX_RST_EN_R
• pcr::iomux_conf::IOMUX_RST_EN_W
• pcr::iomux_conf::R
• pcr::iomux_conf::W
• pcr::ledc_conf::LEDC_CLK_EN_R
• pcr::ledc_conf::LEDC_CLK_EN_W
• pcr::ledc_conf::LEDC_RST_EN_R
• pcr::ledc_conf::LEDC_RST_EN_W
• pcr::ledc_conf::R
• pcr::ledc_conf::W
• pcr::ledc_sclk_conf::LEDC_SCLK_EN_R
• pcr::ledc_sclk_conf::LEDC_SCLK_EN_W
• pcr::ledc_sclk_conf::LEDC_SCLK_SEL_R
• pcr::ledc_sclk_conf::LEDC_SCLK_SEL_W
• pcr::ledc_sclk_conf::R
• pcr::ledc_sclk_conf::W
• pcr::mem_monitor_conf::MEM_MONITOR_CLK_EN_R
• pcr::mem_monitor_conf::MEM_MONITOR_CLK_EN_W
• pcr::mem_monitor_conf::MEM_MONITOR_RST_EN_R
• pcr::mem_monitor_conf::MEM_MONITOR_RST_EN_W
• pcr::mem_monitor_conf::R
• pcr::mem_monitor_conf::W
• pcr::modem_apb_conf::MODEM_APB_CLK_EN_R
• pcr::modem_apb_conf::MODEM_APB_CLK_EN_W
• pcr::modem_apb_conf::MODEM_RST_EN_R
• pcr::modem_apb_conf::MODEM_RST_EN_W
• pcr::modem_apb_conf::R
• pcr::modem_apb_conf::W
• pcr::mspi_clk_conf::MSPI_FAST_HS_DIV_NUM_R
• pcr::mspi_clk_conf::MSPI_FAST_HS_DIV_NUM_W
• pcr::mspi_clk_conf::MSPI_FAST_LS_DIV_NUM_R
• pcr::mspi_clk_conf::MSPI_FAST_LS_DIV_NUM_W
• pcr::mspi_clk_conf::R
• pcr::mspi_clk_conf::W
• pcr::mspi_conf::MSPI_CLK_EN_R
• pcr::mspi_conf::MSPI_CLK_EN_W
• pcr::mspi_conf::MSPI_PLL_CLK_EN_R
• pcr::mspi_conf::MSPI_PLL_CLK_EN_W
• pcr::mspi_conf::MSPI_RST_EN_R
• pcr::mspi_conf::MSPI_RST_EN_W
• pcr::mspi_conf::R
• pcr::mspi_conf::W
• pcr::parl_clk_rx_conf::PARL_CLK_RX_DIV_NUM_R
• pcr::parl_clk_rx_conf::PARL_CLK_RX_DIV_NUM_W
• pcr::parl_clk_rx_conf::PARL_CLK_RX_EN_R
• pcr::parl_clk_rx_conf::PARL_CLK_RX_EN_W
• pcr::parl_clk_rx_conf::PARL_CLK_RX_SEL_R
• pcr::parl_clk_rx_conf::PARL_CLK_RX_SEL_W
• pcr::parl_clk_rx_conf::PARL_RX_RST_EN_R
• pcr::parl_clk_rx_conf::PARL_RX_RST_EN_W
• pcr::parl_clk_rx_conf::R
• pcr::parl_clk_rx_conf::W
• pcr::parl_clk_tx_conf::PARL_CLK_TX_DIV_NUM_R
• pcr::parl_clk_tx_conf::PARL_CLK_TX_DIV_NUM_W
• pcr::parl_clk_tx_conf::PARL_CLK_TX_EN_R
• pcr::parl_clk_tx_conf::PARL_CLK_TX_EN_W
• pcr::parl_clk_tx_conf::PARL_CLK_TX_SEL_R
• pcr::parl_clk_tx_conf::PARL_CLK_TX_SEL_W
• pcr::parl_clk_tx_conf::PARL_TX_RST_EN_R
• pcr::parl_clk_tx_conf::PARL_TX_RST_EN_W
• pcr::parl_clk_tx_conf::R
• pcr::parl_clk_tx_conf::W
• pcr::parl_io_conf::PARL_CLK_EN_R
• pcr::parl_io_conf::PARL_CLK_EN_W
• pcr::parl_io_conf::PARL_RST_EN_R
• pcr::parl_io_conf::PARL_RST_EN_W
• pcr::parl_io_conf::R
• pcr::parl_io_conf::W
• pcr::pcnt_conf::PCNT_CLK_EN_R
• pcr::pcnt_conf::PCNT_CLK_EN_W
• pcr::pcnt_conf::PCNT_RST_EN_R
• pcr::pcnt_conf::PCNT_RST_EN_W
• pcr::pcnt_conf::R
• pcr::pcnt_conf::W
• pcr::pll_div_clk_en::PLL_120M_CLK_EN_R
• pcr::pll_div_clk_en::PLL_120M_CLK_EN_W
• pcr::pll_div_clk_en::PLL_160M_CLK_EN_R
• pcr::pll_div_clk_en::PLL_160M_CLK_EN_W
• pcr::pll_div_clk_en::PLL_20M_CLK_EN_R
• pcr::pll_div_clk_en::PLL_20M_CLK_EN_W
• pcr::pll_div_clk_en::PLL_240M_CLK_EN_R
• pcr::pll_div_clk_en::PLL_240M_CLK_EN_W
• pcr::pll_div_clk_en::PLL_40M_CLK_EN_R
• pcr::pll_div_clk_en::PLL_40M_CLK_EN_W
• pcr::pll_div_clk_en::PLL_48M_CLK_EN_R
• pcr::pll_div_clk_en::PLL_48M_CLK_EN_W
• pcr::pll_div_clk_en::PLL_80M_CLK_EN_R
• pcr::pll_div_clk_en::PLL_80M_CLK_EN_W
• pcr::pll_div_clk_en::R
• pcr::pll_div_clk_en::W
• pcr::pvt_monitor_conf::PVT_MONITOR_CLK_EN_R
• pcr::pvt_monitor_conf::PVT_MONITOR_CLK_EN_W
• pcr::pvt_monitor_conf::PVT_MONITOR_RST_EN_R
• pcr::pvt_monitor_conf::PVT_MONITOR_RST_EN_W
• pcr::pvt_monitor_conf::PVT_MONITOR_SITE1_CLK_EN_R
• pcr::pvt_monitor_conf::PVT_MONITOR_SITE1_CLK_EN_W
• pcr::pvt_monitor_conf::PVT_MONITOR_SITE2_CLK_EN_R
• pcr::pvt_monitor_conf::PVT_MONITOR_SITE2_CLK_EN_W
• pcr::pvt_monitor_conf::PVT_MONITOR_SITE3_CLK_EN_R
• pcr::pvt_monitor_conf::PVT_MONITOR_SITE3_CLK_EN_W
• pcr::pvt_monitor_conf::R
• pcr::pvt_monitor_conf::W
• pcr::pvt_monitor_func_clk_conf::PVT_MONITOR_FUNC_CLK_DIV_NUM_R
• pcr::pvt_monitor_func_clk_conf::PVT_MONITOR_FUNC_CLK_DIV_NUM_W
• pcr::pvt_monitor_func_clk_conf::PVT_MONITOR_FUNC_CLK_EN_R
• pcr::pvt_monitor_func_clk_conf::PVT_MONITOR_FUNC_CLK_EN_W
• pcr::pvt_monitor_func_clk_conf::PVT_MONITOR_FUNC_CLK_SEL_R
• pcr::pvt_monitor_func_clk_conf::PVT_MONITOR_FUNC_CLK_SEL_W
• pcr::pvt_monitor_func_clk_conf::R
• pcr::pvt_monitor_func_clk_conf::W
• pcr::pwm_clk_conf::PWM_CLKM_EN_R
• pcr::pwm_clk_conf::PWM_CLKM_EN_W
• pcr::pwm_clk_conf::PWM_CLKM_SEL_R
• pcr::pwm_clk_conf::PWM_CLKM_SEL_W
• pcr::pwm_clk_conf::PWM_DIV_NUM_R
• pcr::pwm_clk_conf::PWM_DIV_NUM_W
• pcr::pwm_clk_conf::R
• pcr::pwm_clk_conf::W
• pcr::pwm_conf::PWM_CLK_EN_R
• pcr::pwm_conf::PWM_CLK_EN_W
• pcr::pwm_conf::PWM_RST_EN_R
• pcr::pwm_conf::PWM_RST_EN_W
• pcr::pwm_conf::R
• pcr::pwm_conf::W
• pcr::regdma_conf::R
• pcr::regdma_conf::REGDMA_CLK_EN_R
• pcr::regdma_conf::REGDMA_CLK_EN_W
• pcr::regdma_conf::REGDMA_RST_EN_R
• pcr::regdma_conf::REGDMA_RST_EN_W
• pcr::regdma_conf::W
• pcr::reset_event_bypass::APM_R
• pcr::reset_event_bypass::APM_W
• pcr::reset_event_bypass::R
• pcr::reset_event_bypass::RESET_EVENT_BYPASS_R
• pcr::reset_event_bypass::RESET_EVENT_BYPASS_W
• pcr::reset_event_bypass::W
• pcr::retention_conf::R
• pcr::retention_conf::RETENTION_CLK_EN_R
• pcr::retention_conf::RETENTION_CLK_EN_W
• pcr::retention_conf::RETENTION_RST_EN_R
• pcr::retention_conf::RETENTION_RST_EN_W
• pcr::retention_conf::W
• pcr::rmt_conf::R
• pcr::rmt_conf::RMT_CLK_EN_R
• pcr::rmt_conf::RMT_CLK_EN_W
• pcr::rmt_conf::RMT_RST_EN_R
• pcr::rmt_conf::RMT_RST_EN_W
• pcr::rmt_conf::W
• pcr::rmt_sclk_conf::R
• pcr::rmt_sclk_conf::SCLK_DIV_A_R
• pcr::rmt_sclk_conf::SCLK_DIV_A_W
• pcr::rmt_sclk_conf::SCLK_DIV_B_R
• pcr::rmt_sclk_conf::SCLK_DIV_B_W
• pcr::rmt_sclk_conf::SCLK_DIV_NUM_R
• pcr::rmt_sclk_conf::SCLK_DIV_NUM_W
• pcr::rmt_sclk_conf::SCLK_EN_R
• pcr::rmt_sclk_conf::SCLK_EN_W
• pcr::rmt_sclk_conf::SCLK_SEL_R
• pcr::rmt_sclk_conf::SCLK_SEL_W
• pcr::rmt_sclk_conf::W
• pcr::rsa_conf::R
• pcr::rsa_conf::RSA_CLK_EN_R
• pcr::rsa_conf::RSA_CLK_EN_W
• pcr::rsa_conf::RSA_RST_EN_R
• pcr::rsa_conf::RSA_RST_EN_W
• pcr::rsa_conf::W
• pcr::rsa_pd_ctrl::R
• pcr::rsa_pd_ctrl::RSA_MEM_FORCE_PD_R
• pcr::rsa_pd_ctrl::RSA_MEM_FORCE_PD_W
• pcr::rsa_pd_ctrl::RSA_MEM_FORCE_PU_R
• pcr::rsa_pd_ctrl::RSA_MEM_FORCE_PU_W
• pcr::rsa_pd_ctrl::RSA_MEM_PD_R
• pcr::rsa_pd_ctrl::RSA_MEM_PD_W
• pcr::rsa_pd_ctrl::W
• pcr::saradc_clkm_conf::R
• pcr::saradc_clkm_conf::SARADC_CLKM_DIV_A_R
• pcr::saradc_clkm_conf::SARADC_CLKM_DIV_A_W
• pcr::saradc_clkm_conf::SARADC_CLKM_DIV_B_R
• pcr::saradc_clkm_conf::SARADC_CLKM_DIV_B_W
• pcr::saradc_clkm_conf::SARADC_CLKM_DIV_NUM_R
• pcr::saradc_clkm_conf::SARADC_CLKM_DIV_NUM_W
• pcr::saradc_clkm_conf::SARADC_CLKM_EN_R
• pcr::saradc_clkm_conf::SARADC_CLKM_EN_W
• pcr::saradc_clkm_conf::SARADC_CLKM_SEL_R
• pcr::saradc_clkm_conf::SARADC_CLKM_SEL_W
• pcr::saradc_clkm_conf::W
• pcr::saradc_conf::R
• pcr::saradc_conf::SARADC_CLK_EN_R
• pcr::saradc_conf::SARADC_CLK_EN_W
• pcr::saradc_conf::SARADC_REG_CLK_EN_R
• pcr::saradc_conf::SARADC_REG_CLK_EN_W
• pcr::saradc_conf::SARADC_REG_RST_EN_R
• pcr::saradc_conf::SARADC_REG_RST_EN_W
• pcr::saradc_conf::SARADC_RST_EN_R
• pcr::saradc_conf::SARADC_RST_EN_W
• pcr::saradc_conf::W
• pcr::sdio_slave_conf::R
• pcr::sdio_slave_conf::SDIO_SLAVE_CLK_EN_R
• pcr::sdio_slave_conf::SDIO_SLAVE_CLK_EN_W
• pcr::sdio_slave_conf::SDIO_SLAVE_RST_EN_R
• pcr::sdio_slave_conf::SDIO_SLAVE_RST_EN_W
• pcr::sdio_slave_conf::W
• pcr::sha_conf::R
• pcr::sha_conf::SHA_CLK_EN_R
• pcr::sha_conf::SHA_CLK_EN_W
• pcr::sha_conf::SHA_RST_EN_R
• pcr::sha_conf::SHA_RST_EN_W
• pcr::sha_conf::W
• pcr::spi2_clkm_conf::R
• pcr::spi2_clkm_conf::SPI2_CLKM_EN_R
• pcr::spi2_clkm_conf::SPI2_CLKM_EN_W
• pcr::spi2_clkm_conf::SPI2_CLKM_SEL_R
• pcr::spi2_clkm_conf::SPI2_CLKM_SEL_W
• pcr::spi2_clkm_conf::W
• pcr::spi2_conf::R
• pcr::spi2_conf::SPI2_CLK_EN_R
• pcr::spi2_conf::SPI2_CLK_EN_W
• pcr::spi2_conf::SPI2_RST_EN_R
• pcr::spi2_conf::SPI2_RST_EN_W
• pcr::spi2_conf::W
• pcr::sram_power_conf::R
• pcr::sram_power_conf::ROM_CLKGATE_FORCE_ON_R
• pcr::sram_power_conf::ROM_CLKGATE_FORCE_ON_W
• pcr::sram_power_conf::ROM_FORCE_PD_R
• pcr::sram_power_conf::ROM_FORCE_PD_W
• pcr::sram_power_conf::ROM_FORCE_PU_R
• pcr::sram_power_conf::ROM_FORCE_PU_W
• pcr::sram_power_conf::SRAM_CLKGATE_FORCE_ON_R
• pcr::sram_power_conf::SRAM_CLKGATE_FORCE_ON_W
• pcr::sram_power_conf::SRAM_FORCE_PD_R
• pcr::sram_power_conf::SRAM_FORCE_PD_W
• pcr::sram_power_conf::SRAM_FORCE_PU_R
• pcr::sram_power_conf::SRAM_FORCE_PU_W
• pcr::sram_power_conf::W
• pcr::sysclk_conf::CLK_XTAL_FREQ_R
• pcr::sysclk_conf::HS_DIV_NUM_R
• pcr::sysclk_conf::LS_DIV_NUM_R
• pcr::sysclk_conf::R
• pcr::sysclk_conf::SOC_CLK_SEL_R
• pcr::sysclk_conf::SOC_CLK_SEL_W
• pcr::sysclk_conf::W
• pcr::sysclk_freq_query_0::FOSC_FREQ_R
• pcr::sysclk_freq_query_0::PLL_FREQ_R
• pcr::sysclk_freq_query_0::R
• pcr::systimer_conf::R
• pcr::systimer_conf::SYSTIMER_CLK_EN_R
• pcr::systimer_conf::SYSTIMER_CLK_EN_W
• pcr::systimer_conf::SYSTIMER_RST_EN_R
• pcr::systimer_conf::SYSTIMER_RST_EN_W
• pcr::systimer_conf::W
• pcr::systimer_func_clk_conf::R
• pcr::systimer_func_clk_conf::SYSTIMER_FUNC_CLK_EN_R
• pcr::systimer_func_clk_conf::SYSTIMER_FUNC_CLK_EN_W
• pcr::systimer_func_clk_conf::SYSTIMER_FUNC_CLK_SEL_R
• pcr::systimer_func_clk_conf::SYSTIMER_FUNC_CLK_SEL_W
• pcr::systimer_func_clk_conf::W
• pcr::timeout_conf::CPU_TIMEOUT_RST_EN_R
• pcr::timeout_conf::CPU_TIMEOUT_RST_EN_W
• pcr::timeout_conf::HP_TIMEOUT_RST_EN_R
• pcr::timeout_conf::HP_TIMEOUT_RST_EN_W
• pcr::timeout_conf::R
• pcr::timeout_conf::W
• pcr::timergroup0_conf::R
• pcr::timergroup0_conf::TG0_CLK_EN_R
• pcr::timergroup0_conf::TG0_CLK_EN_W
• pcr::timergroup0_conf::TG0_RST_EN_R
• pcr::timergroup0_conf::TG0_RST_EN_W
• pcr::timergroup0_conf::W
• pcr::timergroup0_timer_clk_conf::R
• pcr::timergroup0_timer_clk_conf::TG0_TIMER_CLK_EN_R
• pcr::timergroup0_timer_clk_conf::TG0_TIMER_CLK_EN_W
• pcr::timergroup0_timer_clk_conf::TG0_TIMER_CLK_SEL_R
• pcr::timergroup0_timer_clk_conf::TG0_TIMER_CLK_SEL_W
• pcr::timergroup0_timer_clk_conf::W
• pcr::timergroup0_wdt_clk_conf::R
• pcr::timergroup0_wdt_clk_conf::TG0_WDT_CLK_EN_R
• pcr::timergroup0_wdt_clk_conf::TG0_WDT_CLK_EN_W
• pcr::timergroup0_wdt_clk_conf::TG0_WDT_CLK_SEL_R
• pcr::timergroup0_wdt_clk_conf::TG0_WDT_CLK_SEL_W
• pcr::timergroup0_wdt_clk_conf::W
• pcr::timergroup1_conf::R
• pcr::timergroup1_conf::TG1_CLK_EN_R
• pcr::timergroup1_conf::TG1_CLK_EN_W
• pcr::timergroup1_conf::TG1_RST_EN_R
• pcr::timergroup1_conf::TG1_RST_EN_W
• pcr::timergroup1_conf::W
• pcr::timergroup1_timer_clk_conf::R
• pcr::timergroup1_timer_clk_conf::TG1_TIMER_CLK_EN_R
• pcr::timergroup1_timer_clk_conf::TG1_TIMER_CLK_EN_W
• pcr::timergroup1_timer_clk_conf::TG1_TIMER_CLK_SEL_R
• pcr::timergroup1_timer_clk_conf::TG1_TIMER_CLK_SEL_W
• pcr::timergroup1_timer_clk_conf::W
• pcr::timergroup1_wdt_clk_conf::R
• pcr::timergroup1_wdt_clk_conf::TG1_WDT_CLK_EN_R
• pcr::timergroup1_wdt_clk_conf::TG1_WDT_CLK_EN_W
• pcr::timergroup1_wdt_clk_conf::TG1_WDT_CLK_SEL_R
• pcr::timergroup1_wdt_clk_conf::TG1_WDT_CLK_SEL_W
• pcr::timergroup1_wdt_clk_conf::W
• pcr::trace_conf::R
• pcr::trace_conf::TRACE_CLK_EN_R
• pcr::trace_conf::TRACE_CLK_EN_W
• pcr::trace_conf::TRACE_RST_EN_R
• pcr::trace_conf::TRACE_RST_EN_W
• pcr::trace_conf::W
• pcr::tsens_clk_conf::R
• pcr::tsens_clk_conf::TSENS_CLK_EN_R
• pcr::tsens_clk_conf::TSENS_CLK_EN_W
• pcr::tsens_clk_conf::TSENS_CLK_SEL_R
• pcr::tsens_clk_conf::TSENS_CLK_SEL_W
• pcr::tsens_clk_conf::TSENS_RST_EN_R
• pcr::tsens_clk_conf::TSENS_RST_EN_W
• pcr::tsens_clk_conf::W
• pcr::twai0_conf::R
• pcr::twai0_conf::TWAI0_CLK_EN_R
• pcr::twai0_conf::TWAI0_CLK_EN_W
• pcr::twai0_conf::TWAI0_RST_EN_R
• pcr::twai0_conf::TWAI0_RST_EN_W
• pcr::twai0_conf::W
• pcr::twai0_func_clk_conf::R
• pcr::twai0_func_clk_conf::TWAI0_FUNC_CLK_EN_R
• pcr::twai0_func_clk_conf::TWAI0_FUNC_CLK_EN_W
• pcr::twai0_func_clk_conf::TWAI0_FUNC_CLK_SEL_R
• pcr::twai0_func_clk_conf::TWAI0_FUNC_CLK_SEL_W
• pcr::twai0_func_clk_conf::W
• pcr::twai1_conf::R
• pcr::twai1_conf::TWAI1_CLK_EN_R
• pcr::twai1_conf::TWAI1_CLK_EN_W
• pcr::twai1_conf::TWAI1_RST_EN_R
• pcr::twai1_conf::TWAI1_RST_EN_W
• pcr::twai1_conf::W
• pcr::twai1_func_clk_conf::R
• pcr::twai1_func_clk_conf::TWAI1_FUNC_CLK_EN_R
• pcr::twai1_func_clk_conf::TWAI1_FUNC_CLK_EN_W
• pcr::twai1_func_clk_conf::TWAI1_FUNC_CLK_SEL_R
• pcr::twai1_func_clk_conf::TWAI1_FUNC_CLK_SEL_W
• pcr::twai1_func_clk_conf::W
• pcr::uart::CLK_CONF
• pcr::uart::CONF
• pcr::uart::PD_CTRL
• pcr::uart::clk_conf::R
• pcr::uart::clk_conf::SCLK_DIV_A_R
• pcr::uart::clk_conf::SCLK_DIV_A_W
• pcr::uart::clk_conf::SCLK_DIV_B_R
• pcr::uart::clk_conf::SCLK_DIV_B_W
• pcr::uart::clk_conf::SCLK_DIV_NUM_R
• pcr::uart::clk_conf::SCLK_DIV_NUM_W
• pcr::uart::clk_conf::SCLK_EN_R
• pcr::uart::clk_conf::SCLK_EN_W
• pcr::uart::clk_conf::SCLK_SEL_R
• pcr::uart::clk_conf::SCLK_SEL_W
• pcr::uart::clk_conf::W
• pcr::uart::conf::CLK_EN_R
• pcr::uart::conf::CLK_EN_W
• pcr::uart::conf::R
• pcr::uart::conf::RST_EN_R
• pcr::uart::conf::RST_EN_W
• pcr::uart::conf::W
• pcr::uart::pd_ctrl::MEM_FORCE_PD_R
• pcr::uart::pd_ctrl::MEM_FORCE_PD_W
• pcr::uart::pd_ctrl::MEM_FORCE_PU_R
• pcr::uart::pd_ctrl::MEM_FORCE_PU_W
• pcr::uart::pd_ctrl::R
• pcr::uart::pd_ctrl::W
• pcr::uhci_conf::R
• pcr::uhci_conf::UHCI_CLK_EN_R
• pcr::uhci_conf::UHCI_CLK_EN_W
• pcr::uhci_conf::UHCI_RST_EN_R
• pcr::uhci_conf::UHCI_RST_EN_W
• pcr::uhci_conf::W
• pcr::usb_device_conf::R
• pcr::usb_device_conf::USB_DEVICE_CLK_EN_R
• pcr::usb_device_conf::USB_DEVICE_CLK_EN_W
• pcr::usb_device_conf::USB_DEVICE_RST_EN_R
• pcr::usb_device_conf::USB_DEVICE_RST_EN_W
• pcr::usb_device_conf::W
• plic_mx::EMIP_STATUS
• plic_mx::MXINT_CLAIM
• plic_mx::MXINT_CLEAR
• plic_mx::MXINT_ENABLE
• plic_mx::MXINT_PRI
• plic_mx::MXINT_THRESH
• plic_mx::MXINT_TYPE
• plic_mx::emip_status::CPU_EIP_STATUS_R
• plic_mx::emip_status::R
• plic_mx::mxint_claim::CPU_MXINT_CLAIM_R
• plic_mx::mxint_claim::CPU_MXINT_CLAIM_W
• plic_mx::mxint_claim::R
• plic_mx::mxint_claim::W
• plic_mx::mxint_clear::CPU_MXINT_CLEAR_R
• plic_mx::mxint_clear::CPU_MXINT_CLEAR_W
• plic_mx::mxint_clear::R
• plic_mx::mxint_clear::W
• plic_mx::mxint_enable::CPU_MXINT_ENABLE_R
• plic_mx::mxint_enable::CPU_MXINT_ENABLE_W
• plic_mx::mxint_enable::R
• plic_mx::mxint_enable::W
• plic_mx::mxint_pri::CPU_MXINT_PRI_R
• plic_mx::mxint_pri::CPU_MXINT_PRI_W
• plic_mx::mxint_pri::R
• plic_mx::mxint_pri::W
• plic_mx::mxint_thresh::CPU_MXINT_THRESH_R
• plic_mx::mxint_thresh::CPU_MXINT_THRESH_W
• plic_mx::mxint_thresh::R
• plic_mx::mxint_thresh::W
• plic_mx::mxint_type::CPU_MXINT_TYPE_R
• plic_mx::mxint_type::CPU_MXINT_TYPE_W
• plic_mx::mxint_type::R
• plic_mx::mxint_type::W
• plic_ux::EUIP_STATUS
• plic_ux::UXINT_CLAIM
• plic_ux::UXINT_CLEAR
• plic_ux::UXINT_ENABLE
• plic_ux::UXINT_PRI
• plic_ux::UXINT_THRESH
• plic_ux::UXINT_TYPE
• plic_ux::euip_status::CPU_EIP_STATUS_R
• plic_ux::euip_status::R
• plic_ux::uxint_claim::CPU_UXINT_CLAIM_R
• plic_ux::uxint_claim::CPU_UXINT_CLAIM_W
• plic_ux::uxint_claim::R
• plic_ux::uxint_claim::W
• plic_ux::uxint_clear::CPU_UXINT_CLEAR_R
• plic_ux::uxint_clear::CPU_UXINT_CLEAR_W
• plic_ux::uxint_clear::R
• plic_ux::uxint_clear::W
• plic_ux::uxint_enable::CPU_UXINT_ENABLE_R
• plic_ux::uxint_enable::CPU_UXINT_ENABLE_W
• plic_ux::uxint_enable::R
• plic_ux::uxint_enable::W
• plic_ux::uxint_pri::CPU_UXINT_PRI_R
• plic_ux::uxint_pri::CPU_UXINT_PRI_W
• plic_ux::uxint_pri::R
• plic_ux::uxint_pri::W
• plic_ux::uxint_thresh::CPU_UXINT_THRESH_R
• plic_ux::uxint_thresh::CPU_UXINT_THRESH_W
• plic_ux::uxint_thresh::R
• plic_ux::uxint_thresh::W
• plic_ux::uxint_type::CPU_UXINT_TYPE_R
• plic_ux::uxint_type::CPU_UXINT_TYPE_W
• plic_ux::uxint_type::R
• plic_ux::uxint_type::W
• pmu::BACKUP_CFG
• pmu::CLK_STATE0
• pmu::CLK_STATE1
• pmu::CLK_STATE2
• pmu::DATE
• pmu::HP_ACTIVE_BACKUP
• pmu::HP_ACTIVE_BACKUP_CLK
• pmu::HP_ACTIVE_BIAS
• pmu::HP_ACTIVE_DIG_POWER
• pmu::HP_ACTIVE_HP_CK_POWER
• pmu::HP_ACTIVE_HP_REGULATOR0
• pmu::HP_ACTIVE_HP_REGULATOR1
• pmu::HP_ACTIVE_HP_SYS_CNTL
• pmu::HP_ACTIVE_ICG_HP_APB
• pmu::HP_ACTIVE_ICG_HP_FUNC
• pmu::HP_ACTIVE_ICG_MODEM
• pmu::HP_ACTIVE_SYSCLK
• pmu::HP_ACTIVE_XTAL
• pmu::HP_CK_CNTL
• pmu::HP_CK_POWERON
• pmu::HP_LP_CPU_COMM
• pmu::HP_MODEM_BACKUP
• pmu::HP_MODEM_BACKUP_CLK
• pmu::HP_MODEM_BIAS
• pmu::HP_MODEM_DIG_POWER
• pmu::HP_MODEM_HP_CK_POWER
• pmu::HP_MODEM_HP_REGULATOR0
• pmu::HP_MODEM_HP_REGULATOR1
• pmu::HP_MODEM_HP_SYS_CNTL
• pmu::HP_MODEM_ICG_HP_APB
• pmu::HP_MODEM_ICG_HP_FUNC
• pmu::HP_MODEM_ICG_MODEM
• pmu::HP_MODEM_SYSCLK
• pmu::HP_MODEM_XTAL
• pmu::HP_REGULATOR_CFG
• pmu::HP_SLEEP_BACKUP
• pmu::HP_SLEEP_BACKUP_CLK
• pmu::HP_SLEEP_BIAS
• pmu::HP_SLEEP_DIG_POWER
• pmu::HP_SLEEP_HP_CK_POWER
• pmu::HP_SLEEP_HP_REGULATOR0
• pmu::HP_SLEEP_HP_REGULATOR1
• pmu::HP_SLEEP_HP_SYS_CNTL
• pmu::HP_SLEEP_ICG_HP_APB
• pmu::HP_SLEEP_ICG_HP_FUNC
• pmu::HP_SLEEP_ICG_MODEM
• pmu::HP_SLEEP_LP_CK_POWER
• pmu::HP_SLEEP_LP_DCDC_RESERVE
• pmu::HP_SLEEP_LP_DIG_POWER
• pmu::HP_SLEEP_LP_REGULATOR0
• pmu::HP_SLEEP_LP_REGULATOR1
• pmu::HP_SLEEP_SYSCLK
• pmu::HP_SLEEP_XTAL
• pmu::IMM_HP_APB_ICG
• pmu::IMM_HP_CK_POWER
• pmu::IMM_HP_FUNC_ICG
• pmu::IMM_I2C_ISO
• pmu::IMM_LP_ICG
• pmu::IMM_MODEM_ICG
• pmu::IMM_PAD_HOLD_ALL
• pmu::IMM_SLEEP_SYSCLK
• pmu::INT_CLR
• pmu::INT_ENA
• pmu::INT_RAW
• pmu::INT_ST
• pmu::LP_CPU_PWR0
• pmu::LP_CPU_PWR1
• pmu::LP_INT_CLR
• pmu::LP_INT_ENA
• pmu::LP_INT_RAW
• pmu::LP_INT_ST
• pmu::LP_SLEEP_BIAS
• pmu::LP_SLEEP_LP_BIAS_RESERVE
• pmu::LP_SLEEP_LP_CK_POWER
• pmu::LP_SLEEP_LP_DIG_POWER
• pmu::LP_SLEEP_LP_REGULATOR0
• pmu::LP_SLEEP_LP_REGULATOR1
• pmu::LP_SLEEP_XTAL
• pmu::MAIN_STATE
• pmu::POR_STATUS
• pmu::POWER_CK_WAIT_CNTL
• pmu::POWER_HP_PAD
• pmu::POWER_PD_HPAON_CNTL
• pmu::POWER_PD_HPCPU_CNTL
• pmu::POWER_PD_HPPERI_RESERVE
• pmu::POWER_PD_HPWIFI_CNTL
• pmu::POWER_PD_LPPERI_CNTL
• pmu::POWER_PD_MEM_CNTL
• pmu::POWER_PD_MEM_MASK
• pmu::POWER_PD_TOP_CNTL
• pmu::POWER_VDD_SPI_CNTL
• pmu::POWER_WAIT_TIMER0
• pmu::POWER_WAIT_TIMER1
• pmu::PWR_STATE
• pmu::RF_PWC
• pmu::SLP_WAKEUP_CNTL0
• pmu::SLP_WAKEUP_CNTL1
• pmu::SLP_WAKEUP_CNTL2
• pmu::SLP_WAKEUP_CNTL3
• pmu::SLP_WAKEUP_CNTL4
• pmu::SLP_WAKEUP_CNTL5
• pmu::SLP_WAKEUP_CNTL6
• pmu::SLP_WAKEUP_CNTL7
• pmu::SLP_WAKEUP_STATUS0
• pmu::SLP_WAKEUP_STATUS1
• pmu::VDD_SPI_STATUS
• pmu::backup_cfg::BACKUP_SYS_CLK_NO_DIV_R
• pmu::backup_cfg::BACKUP_SYS_CLK_NO_DIV_W
• pmu::backup_cfg::R
• pmu::backup_cfg::W
• pmu::clk_state0::ANA_I2C_ISO_EN_STATE_R
• pmu::clk_state0::ANA_I2C_RETENTION_STATE_R
• pmu::clk_state0::ANA_XPD_BBPLL_I2C_STATE_R
• pmu::clk_state0::ANA_XPD_BBPLL_STATE_R
• pmu::clk_state0::ANA_XPD_BB_I2C_STATE_R
• pmu::clk_state0::ANA_XPD_XTAL_STATE_R
• pmu::clk_state0::ICG_GLOBAL_PLL_STATE_R
• pmu::clk_state0::ICG_GLOBAL_XTAL_STATE_R
• pmu::clk_state0::ICG_MODEM_CODE_STATE_R
• pmu::clk_state0::ICG_MODEM_SWITCH_STATE_R
• pmu::clk_state0::ICG_SLP_SEL_STATE_R
• pmu::clk_state0::ICG_SYS_CLK_EN_STATE_R
• pmu::clk_state0::R
• pmu::clk_state0::STABLE_XPD_BBPLL_STATE_R
• pmu::clk_state0::STABLE_XPD_XTAL_STATE_R
• pmu::clk_state0::SYS_CLK_NO_DIV_STATE_R
• pmu::clk_state0::SYS_CLK_SEL_STATE_R
• pmu::clk_state0::SYS_CLK_SLP_SEL_STATE_R
• pmu::clk_state1::ICG_FUNC_EN_STATE_R
• pmu::clk_state1::R
• pmu::clk_state2::ICG_APB_EN_STATE_R
• pmu::clk_state2::R
• pmu::date::CLK_EN_R
• pmu::date::CLK_EN_W
• pmu::date::PMU_DATE_R
• pmu::date::PMU_DATE_W
• pmu::date::R
• pmu::date::W
• pmu::hp_active_backup::HP_ACTIVE_RETENTION_MODE_R
• pmu::hp_active_backup::HP_ACTIVE_RETENTION_MODE_W
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_CLK_SEL_R
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_CLK_SEL_W
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_EN_R
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_EN_W
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_R
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_W
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_MODE_R
• pmu::hp_active_backup::HP_MODEM2ACTIVE_BACKUP_MODE_W
• pmu::hp_active_backup::HP_MODEM2ACTIVE_RETENTION_EN_R
• pmu::hp_active_backup::HP_MODEM2ACTIVE_RETENTION_EN_W
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_R
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_CLK_SEL_W
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_EN_R
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_EN_W
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_R
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_MODEM_CLK_CODE_W
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_MODE_R
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_BACKUP_MODE_W
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_RETENTION_EN_R
• pmu::hp_active_backup::HP_SLEEP2ACTIVE_RETENTION_EN_W
• pmu::hp_active_backup::R
• pmu::hp_active_backup::W
• pmu::hp_active_backup_clk::HP_ACTIVE_BACKUP_ICG_FUNC_EN_R
• pmu::hp_active_backup_clk::HP_ACTIVE_BACKUP_ICG_FUNC_EN_W
• pmu::hp_active_backup_clk::R
• pmu::hp_active_backup_clk::W
• pmu::hp_active_bias::HP_ACTIVE_DBG_ATTEN_R
• pmu::hp_active_bias::HP_ACTIVE_DBG_ATTEN_W
• pmu::hp_active_bias::HP_ACTIVE_PD_CUR_R
• pmu::hp_active_bias::HP_ACTIVE_PD_CUR_W
• pmu::hp_active_bias::HP_ACTIVE_XPD_BIAS_R
• pmu::hp_active_bias::HP_ACTIVE_XPD_BIAS_W
• pmu::hp_active_bias::R
• pmu::hp_active_bias::SLEEP_R
• pmu::hp_active_bias::SLEEP_W
• pmu::hp_active_bias::W
• pmu::hp_active_dig_power::HP_ACTIVE_HP_MEM_DSLP_R
• pmu::hp_active_dig_power::HP_ACTIVE_HP_MEM_DSLP_W
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_AON_PD_EN_R
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_AON_PD_EN_W
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_CPU_PD_EN_R
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_CPU_PD_EN_W
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_MEM_PD_EN_R
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_MEM_PD_EN_W
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_WIFI_PD_EN_R
• pmu::hp_active_dig_power::HP_ACTIVE_PD_HP_WIFI_PD_EN_W
• pmu::hp_active_dig_power::HP_ACTIVE_PD_TOP_PD_EN_R
• pmu::hp_active_dig_power::HP_ACTIVE_PD_TOP_PD_EN_W
• pmu::hp_active_dig_power::HP_ACTIVE_VDD_SPI_PD_EN_R
• pmu::hp_active_dig_power::HP_ACTIVE_VDD_SPI_PD_EN_W
• pmu::hp_active_dig_power::R
• pmu::hp_active_dig_power::W
• pmu::hp_active_hp_ck_power::HP_ACTIVE_I2C_ISO_EN_R
• pmu::hp_active_hp_ck_power::HP_ACTIVE_I2C_ISO_EN_W
• pmu::hp_active_hp_ck_power::HP_ACTIVE_I2C_RETENTION_R
• pmu::hp_active_hp_ck_power::HP_ACTIVE_I2C_RETENTION_W
• pmu::hp_active_hp_ck_power::HP_ACTIVE_XPD_BBPLL_I2C_R
• pmu::hp_active_hp_ck_power::HP_ACTIVE_XPD_BBPLL_I2C_W
• pmu::hp_active_hp_ck_power::HP_ACTIVE_XPD_BBPLL_R
• pmu::hp_active_hp_ck_power::HP_ACTIVE_XPD_BBPLL_W
• pmu::hp_active_hp_ck_power::HP_ACTIVE_XPD_BB_I2C_R
• pmu::hp_active_hp_ck_power::HP_ACTIVE_XPD_BB_I2C_W
• pmu::hp_active_hp_ck_power::R
• pmu::hp_active_hp_ck_power::W
• pmu::hp_active_hp_regulator0::DIG_DBIAS_INIT_W
• pmu::hp_active_hp_regulator0::DIG_REGULATOR0_DBIAS_SEL_R
• pmu::hp_active_hp_regulator0::DIG_REGULATOR0_DBIAS_SEL_W
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_DBIAS_R
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_DBIAS_W
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_R
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_DBIAS_W
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_R
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_LOGIC_XPD_W
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_R
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_MEM_DBIAS_W
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_R
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_SLP_MEM_XPD_W
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_XPD_R
• pmu::hp_active_hp_regulator0::HP_ACTIVE_HP_REGULATOR_XPD_W
• pmu::hp_active_hp_regulator0::HP_DBIAS_VOL_R
• pmu::hp_active_hp_regulator0::LP_DBIAS_VOL_R
• pmu::hp_active_hp_regulator0::R
• pmu::hp_active_hp_regulator0::W
• pmu::hp_active_hp_regulator1::HP_ACTIVE_HP_REGULATOR_DRV_B_R
• pmu::hp_active_hp_regulator1::HP_ACTIVE_HP_REGULATOR_DRV_B_W
• pmu::hp_active_hp_regulator1::R
• pmu::hp_active_hp_regulator1::W
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_DIG_CPU_STALL_R
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_DIG_CPU_STALL_W
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_DIG_PAD_SLP_SEL_R
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_DIG_PAD_SLP_SEL_W
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_DIG_PAUSE_WDT_R
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_DIG_PAUSE_WDT_W
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_HP_PAD_HOLD_ALL_R
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_HP_PAD_HOLD_ALL_W
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_LP_PAD_HOLD_ALL_R
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_LP_PAD_HOLD_ALL_W
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_UART_WAKEUP_EN_R
• pmu::hp_active_hp_sys_cntl::HP_ACTIVE_UART_WAKEUP_EN_W
• pmu::hp_active_hp_sys_cntl::R
• pmu::hp_active_hp_sys_cntl::W
• pmu::hp_active_icg_hp_apb::HP_ACTIVE_DIG_ICG_APB_EN_R
• pmu::hp_active_icg_hp_apb::HP_ACTIVE_DIG_ICG_APB_EN_W
• pmu::hp_active_icg_hp_apb::R
• pmu::hp_active_icg_hp_apb::W
• pmu::hp_active_icg_hp_func::HP_ACTIVE_DIG_ICG_FUNC_EN_R
• pmu::hp_active_icg_hp_func::HP_ACTIVE_DIG_ICG_FUNC_EN_W
• pmu::hp_active_icg_hp_func::R
• pmu::hp_active_icg_hp_func::W
• pmu::hp_active_icg_modem::HP_ACTIVE_DIG_ICG_MODEM_CODE_R
• pmu::hp_active_icg_modem::HP_ACTIVE_DIG_ICG_MODEM_CODE_W
• pmu::hp_active_icg_modem::R
• pmu::hp_active_icg_modem::W
• pmu::hp_active_sysclk::HP_ACTIVE_DIG_SYS_CLK_NO_DIV_R
• pmu::hp_active_sysclk::HP_ACTIVE_DIG_SYS_CLK_NO_DIV_W
• pmu::hp_active_sysclk::HP_ACTIVE_DIG_SYS_CLK_SEL_R
• pmu::hp_active_sysclk::HP_ACTIVE_DIG_SYS_CLK_SEL_W
• pmu::hp_active_sysclk::HP_ACTIVE_ICG_SLP_SEL_R
• pmu::hp_active_sysclk::HP_ACTIVE_ICG_SLP_SEL_W
• pmu::hp_active_sysclk::HP_ACTIVE_ICG_SYS_CLOCK_EN_R
• pmu::hp_active_sysclk::HP_ACTIVE_ICG_SYS_CLOCK_EN_W
• pmu::hp_active_sysclk::HP_ACTIVE_SYS_CLK_SLP_SEL_R
• pmu::hp_active_sysclk::HP_ACTIVE_SYS_CLK_SLP_SEL_W
• pmu::hp_active_sysclk::R
• pmu::hp_active_sysclk::W
• pmu::hp_active_xtal::HP_ACTIVE_XPD_XTAL_R
• pmu::hp_active_xtal::HP_ACTIVE_XPD_XTAL_W
• pmu::hp_active_xtal::R
• pmu::hp_active_xtal::W
• pmu::hp_ck_cntl::MODIFY_ICG_CNTL_WAIT_R
• pmu::hp_ck_cntl::MODIFY_ICG_CNTL_WAIT_W
• pmu::hp_ck_cntl::R
• pmu::hp_ck_cntl::SWITCH_ICG_CNTL_WAIT_R
• pmu::hp_ck_cntl::SWITCH_ICG_CNTL_WAIT_W
• pmu::hp_ck_cntl::W
• pmu::hp_ck_poweron::I2C_POR_WAIT_TARGET_R
• pmu::hp_ck_poweron::I2C_POR_WAIT_TARGET_W
• pmu::hp_ck_poweron::R
• pmu::hp_ck_poweron::W
• pmu::hp_lp_cpu_comm::HP_TRIGGER_LP_W
• pmu::hp_lp_cpu_comm::LP_TRIGGER_HP_W
• pmu::hp_lp_cpu_comm::W
• pmu::hp_modem_backup::HP_MODEM_RETENTION_MODE_R
• pmu::hp_modem_backup::HP_MODEM_RETENTION_MODE_W
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_CLK_SEL_R
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_CLK_SEL_W
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_EN_R
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_EN_W
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_R
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_W
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_MODE_R
• pmu::hp_modem_backup::HP_SLEEP2MODEM_BACKUP_MODE_W
• pmu::hp_modem_backup::HP_SLEEP2MODEM_RETENTION_EN_R
• pmu::hp_modem_backup::HP_SLEEP2MODEM_RETENTION_EN_W
• pmu::hp_modem_backup::R
• pmu::hp_modem_backup::W
• pmu::hp_modem_backup_clk::HP_MODEM_BACKUP_ICG_FUNC_EN_R
• pmu::hp_modem_backup_clk::HP_MODEM_BACKUP_ICG_FUNC_EN_W
• pmu::hp_modem_backup_clk::R
• pmu::hp_modem_backup_clk::W
• pmu::hp_modem_bias::HP_MODEM_DBG_ATTEN_R
• pmu::hp_modem_bias::HP_MODEM_DBG_ATTEN_W
• pmu::hp_modem_bias::HP_MODEM_PD_CUR_R
• pmu::hp_modem_bias::HP_MODEM_PD_CUR_W
• pmu::hp_modem_bias::HP_MODEM_XPD_BIAS_R
• pmu::hp_modem_bias::HP_MODEM_XPD_BIAS_W
• pmu::hp_modem_bias::R
• pmu::hp_modem_bias::SLEEP_R
• pmu::hp_modem_bias::SLEEP_W
• pmu::hp_modem_bias::W
• pmu::hp_modem_dig_power::HP_MODEM_HP_MEM_DSLP_R
• pmu::hp_modem_dig_power::HP_MODEM_HP_MEM_DSLP_W
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_AON_PD_EN_R
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_AON_PD_EN_W
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_CPU_PD_EN_R
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_CPU_PD_EN_W
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_MEM_PD_EN_R
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_MEM_PD_EN_W
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_WIFI_PD_EN_R
• pmu::hp_modem_dig_power::HP_MODEM_PD_HP_WIFI_PD_EN_W
• pmu::hp_modem_dig_power::HP_MODEM_PD_TOP_PD_EN_R
• pmu::hp_modem_dig_power::HP_MODEM_PD_TOP_PD_EN_W
• pmu::hp_modem_dig_power::HP_MODEM_VDD_SPI_PD_EN_R
• pmu::hp_modem_dig_power::HP_MODEM_VDD_SPI_PD_EN_W
• pmu::hp_modem_dig_power::R
• pmu::hp_modem_dig_power::W
• pmu::hp_modem_hp_ck_power::HP_MODEM_I2C_ISO_EN_R
• pmu::hp_modem_hp_ck_power::HP_MODEM_I2C_ISO_EN_W
• pmu::hp_modem_hp_ck_power::HP_MODEM_I2C_RETENTION_R
• pmu::hp_modem_hp_ck_power::HP_MODEM_I2C_RETENTION_W
• pmu::hp_modem_hp_ck_power::HP_MODEM_XPD_BBPLL_I2C_R
• pmu::hp_modem_hp_ck_power::HP_MODEM_XPD_BBPLL_I2C_W
• pmu::hp_modem_hp_ck_power::HP_MODEM_XPD_BBPLL_R
• pmu::hp_modem_hp_ck_power::HP_MODEM_XPD_BBPLL_W
• pmu::hp_modem_hp_ck_power::HP_MODEM_XPD_BB_I2C_R
• pmu::hp_modem_hp_ck_power::HP_MODEM_XPD_BB_I2C_W
• pmu::hp_modem_hp_ck_power::R
• pmu::hp_modem_hp_ck_power::W
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_DBIAS_R
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_DBIAS_W
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_R
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_LOGIC_DBIAS_W
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_R
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_LOGIC_XPD_W
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_R
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_MEM_DBIAS_W
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_R
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_SLP_MEM_XPD_W
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_XPD_R
• pmu::hp_modem_hp_regulator0::HP_MODEM_HP_REGULATOR_XPD_W
• pmu::hp_modem_hp_regulator0::R
• pmu::hp_modem_hp_regulator0::W
• pmu::hp_modem_hp_regulator1::HP_MODEM_HP_REGULATOR_DRV_B_R
• pmu::hp_modem_hp_regulator1::HP_MODEM_HP_REGULATOR_DRV_B_W
• pmu::hp_modem_hp_regulator1::R
• pmu::hp_modem_hp_regulator1::W
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_DIG_CPU_STALL_R
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_DIG_CPU_STALL_W
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_DIG_PAD_SLP_SEL_R
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_DIG_PAD_SLP_SEL_W
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_DIG_PAUSE_WDT_R
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_DIG_PAUSE_WDT_W
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_HP_PAD_HOLD_ALL_R
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_HP_PAD_HOLD_ALL_W
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_LP_PAD_HOLD_ALL_R
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_LP_PAD_HOLD_ALL_W
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_UART_WAKEUP_EN_R
• pmu::hp_modem_hp_sys_cntl::HP_MODEM_UART_WAKEUP_EN_W
• pmu::hp_modem_hp_sys_cntl::R
• pmu::hp_modem_hp_sys_cntl::W
• pmu::hp_modem_icg_hp_apb::HP_MODEM_DIG_ICG_APB_EN_R
• pmu::hp_modem_icg_hp_apb::HP_MODEM_DIG_ICG_APB_EN_W
• pmu::hp_modem_icg_hp_apb::R
• pmu::hp_modem_icg_hp_apb::W
• pmu::hp_modem_icg_hp_func::HP_MODEM_DIG_ICG_FUNC_EN_R
• pmu::hp_modem_icg_hp_func::HP_MODEM_DIG_ICG_FUNC_EN_W
• pmu::hp_modem_icg_hp_func::R
• pmu::hp_modem_icg_hp_func::W
• pmu::hp_modem_icg_modem::HP_MODEM_DIG_ICG_MODEM_CODE_R
• pmu::hp_modem_icg_modem::HP_MODEM_DIG_ICG_MODEM_CODE_W
• pmu::hp_modem_icg_modem::R
• pmu::hp_modem_icg_modem::W
• pmu::hp_modem_sysclk::HP_MODEM_DIG_SYS_CLK_NO_DIV_R
• pmu::hp_modem_sysclk::HP_MODEM_DIG_SYS_CLK_NO_DIV_W
• pmu::hp_modem_sysclk::HP_MODEM_DIG_SYS_CLK_SEL_R
• pmu::hp_modem_sysclk::HP_MODEM_DIG_SYS_CLK_SEL_W
• pmu::hp_modem_sysclk::HP_MODEM_ICG_SLP_SEL_R
• pmu::hp_modem_sysclk::HP_MODEM_ICG_SLP_SEL_W
• pmu::hp_modem_sysclk::HP_MODEM_ICG_SYS_CLOCK_EN_R
• pmu::hp_modem_sysclk::HP_MODEM_ICG_SYS_CLOCK_EN_W
• pmu::hp_modem_sysclk::HP_MODEM_SYS_CLK_SLP_SEL_R
• pmu::hp_modem_sysclk::HP_MODEM_SYS_CLK_SLP_SEL_W
• pmu::hp_modem_sysclk::R
• pmu::hp_modem_sysclk::W
• pmu::hp_modem_xtal::HP_MODEM_XPD_XTAL_R
• pmu::hp_modem_xtal::HP_MODEM_XPD_XTAL_W
• pmu::hp_modem_xtal::R
• pmu::hp_modem_xtal::W
• pmu::hp_regulator_cfg::DIG_REGULATOR_EN_CAL_R
• pmu::hp_regulator_cfg::DIG_REGULATOR_EN_CAL_W
• pmu::hp_regulator_cfg::R
• pmu::hp_regulator_cfg::W
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_R
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_W
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_EN_R
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_EN_W
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_R
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_W
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_MODE_R
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_BACKUP_MODE_W
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_RETENTION_EN_R
• pmu::hp_sleep_backup::HP_ACTIVE2SLEEP_RETENTION_EN_W
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_CLK_SEL_R
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_CLK_SEL_W
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_EN_R
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_EN_W
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_R
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_MODEM_CLK_CODE_W
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_MODE_R
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_BACKUP_MODE_W
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_RETENTION_EN_R
• pmu::hp_sleep_backup::HP_MODEM2SLEEP_RETENTION_EN_W
• pmu::hp_sleep_backup::HP_SLEEP_RETENTION_MODE_R
• pmu::hp_sleep_backup::HP_SLEEP_RETENTION_MODE_W
• pmu::hp_sleep_backup::R
• pmu::hp_sleep_backup::W
• pmu::hp_sleep_backup_clk::HP_SLEEP_BACKUP_ICG_FUNC_EN_R
• pmu::hp_sleep_backup_clk::HP_SLEEP_BACKUP_ICG_FUNC_EN_W
• pmu::hp_sleep_backup_clk::R
• pmu::hp_sleep_backup_clk::W
• pmu::hp_sleep_bias::HP_SLEEP_DBG_ATTEN_R
• pmu::hp_sleep_bias::HP_SLEEP_DBG_ATTEN_W
• pmu::hp_sleep_bias::HP_SLEEP_PD_CUR_R
• pmu::hp_sleep_bias::HP_SLEEP_PD_CUR_W
• pmu::hp_sleep_bias::HP_SLEEP_XPD_BIAS_R
• pmu::hp_sleep_bias::HP_SLEEP_XPD_BIAS_W
• pmu::hp_sleep_bias::R
• pmu::hp_sleep_bias::SLEEP_R
• pmu::hp_sleep_bias::SLEEP_W
• pmu::hp_sleep_bias::W
• pmu::hp_sleep_dig_power::HP_SLEEP_HP_MEM_DSLP_R
• pmu::hp_sleep_dig_power::HP_SLEEP_HP_MEM_DSLP_W
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_AON_PD_EN_R
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_AON_PD_EN_W
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_CPU_PD_EN_R
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_CPU_PD_EN_W
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_MEM_PD_EN_R
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_MEM_PD_EN_W
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_WIFI_PD_EN_R
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_HP_WIFI_PD_EN_W
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_TOP_PD_EN_R
• pmu::hp_sleep_dig_power::HP_SLEEP_PD_TOP_PD_EN_W
• pmu::hp_sleep_dig_power::HP_SLEEP_VDD_SPI_PD_EN_R
• pmu::hp_sleep_dig_power::HP_SLEEP_VDD_SPI_PD_EN_W
• pmu::hp_sleep_dig_power::R
• pmu::hp_sleep_dig_power::W
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_I2C_ISO_EN_R
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_I2C_ISO_EN_W
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_I2C_RETENTION_R
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_I2C_RETENTION_W
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_XPD_BBPLL_I2C_R
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_XPD_BBPLL_I2C_W
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_XPD_BBPLL_R
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_XPD_BBPLL_W
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_XPD_BB_I2C_R
• pmu::hp_sleep_hp_ck_power::HP_SLEEP_XPD_BB_I2C_W
• pmu::hp_sleep_hp_ck_power::R
• pmu::hp_sleep_hp_ck_power::W
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_DBIAS_R
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_DBIAS_W
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_R
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_LOGIC_DBIAS_W
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_R
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_LOGIC_XPD_W
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_R
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_MEM_DBIAS_W
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_R
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_SLP_MEM_XPD_W
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_XPD_R
• pmu::hp_sleep_hp_regulator0::HP_SLEEP_HP_REGULATOR_XPD_W
• pmu::hp_sleep_hp_regulator0::R
• pmu::hp_sleep_hp_regulator0::W
• pmu::hp_sleep_hp_regulator1::HP_SLEEP_HP_REGULATOR_DRV_B_R
• pmu::hp_sleep_hp_regulator1::HP_SLEEP_HP_REGULATOR_DRV_B_W
• pmu::hp_sleep_hp_regulator1::R
• pmu::hp_sleep_hp_regulator1::W
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_DIG_CPU_STALL_R
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_DIG_CPU_STALL_W
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_DIG_PAD_SLP_SEL_R
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_DIG_PAD_SLP_SEL_W
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_DIG_PAUSE_WDT_R
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_DIG_PAUSE_WDT_W
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_HP_PAD_HOLD_ALL_R
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_HP_PAD_HOLD_ALL_W
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_LP_PAD_HOLD_ALL_R
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_LP_PAD_HOLD_ALL_W
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_UART_WAKEUP_EN_R
• pmu::hp_sleep_hp_sys_cntl::HP_SLEEP_UART_WAKEUP_EN_W
• pmu::hp_sleep_hp_sys_cntl::R
• pmu::hp_sleep_hp_sys_cntl::W
• pmu::hp_sleep_icg_hp_apb::HP_SLEEP_DIG_ICG_APB_EN_R
• pmu::hp_sleep_icg_hp_apb::HP_SLEEP_DIG_ICG_APB_EN_W
• pmu::hp_sleep_icg_hp_apb::R
• pmu::hp_sleep_icg_hp_apb::W
• pmu::hp_sleep_icg_hp_func::HP_SLEEP_DIG_ICG_FUNC_EN_R
• pmu::hp_sleep_icg_hp_func::HP_SLEEP_DIG_ICG_FUNC_EN_W
• pmu::hp_sleep_icg_hp_func::R
• pmu::hp_sleep_icg_hp_func::W
• pmu::hp_sleep_icg_modem::HP_SLEEP_DIG_ICG_MODEM_CODE_R
• pmu::hp_sleep_icg_modem::HP_SLEEP_DIG_ICG_MODEM_CODE_W
• pmu::hp_sleep_icg_modem::R
• pmu::hp_sleep_icg_modem::W
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_PD_OSC_CLK_R
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_PD_OSC_CLK_W
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_XPD_FOSC_CLK_R
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_XPD_FOSC_CLK_W
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_XPD_RC32K_R
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_XPD_RC32K_W
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_XPD_XTAL32K_R
• pmu::hp_sleep_lp_ck_power::HP_SLEEP_XPD_XTAL32K_W
• pmu::hp_sleep_lp_ck_power::R
• pmu::hp_sleep_lp_ck_power::W
• pmu::hp_sleep_lp_dcdc_reserve::HP_SLEEP_LP_DCDC_RESERVE_W
• pmu::hp_sleep_lp_dcdc_reserve::W
• pmu::hp_sleep_lp_dig_power::HP_SLEEP_LP_MEM_DSLP_R
• pmu::hp_sleep_lp_dig_power::HP_SLEEP_LP_MEM_DSLP_W
• pmu::hp_sleep_lp_dig_power::HP_SLEEP_PD_LP_PERI_PD_EN_R
• pmu::hp_sleep_lp_dig_power::HP_SLEEP_PD_LP_PERI_PD_EN_W
• pmu::hp_sleep_lp_dig_power::R
• pmu::hp_sleep_lp_dig_power::W
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_DBIAS_R
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_DBIAS_W
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_SLP_DBIAS_R
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_SLP_DBIAS_W
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_SLP_XPD_R
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_SLP_XPD_W
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_XPD_R
• pmu::hp_sleep_lp_regulator0::HP_SLEEP_LP_REGULATOR_XPD_W
• pmu::hp_sleep_lp_regulator0::R
• pmu::hp_sleep_lp_regulator0::W
• pmu::hp_sleep_lp_regulator1::HP_SLEEP_LP_REGULATOR_DRV_B_R
• pmu::hp_sleep_lp_regulator1::HP_SLEEP_LP_REGULATOR_DRV_B_W
• pmu::hp_sleep_lp_regulator1::R
• pmu::hp_sleep_lp_regulator1::W
• pmu::hp_sleep_sysclk::HP_SLEEP_DIG_SYS_CLK_NO_DIV_R
• pmu::hp_sleep_sysclk::HP_SLEEP_DIG_SYS_CLK_NO_DIV_W
• pmu::hp_sleep_sysclk::HP_SLEEP_DIG_SYS_CLK_SEL_R
• pmu::hp_sleep_sysclk::HP_SLEEP_DIG_SYS_CLK_SEL_W
• pmu::hp_sleep_sysclk::HP_SLEEP_ICG_SLP_SEL_R
• pmu::hp_sleep_sysclk::HP_SLEEP_ICG_SLP_SEL_W
• pmu::hp_sleep_sysclk::HP_SLEEP_ICG_SYS_CLOCK_EN_R
• pmu::hp_sleep_sysclk::HP_SLEEP_ICG_SYS_CLOCK_EN_W
• pmu::hp_sleep_sysclk::HP_SLEEP_SYS_CLK_SLP_SEL_R
• pmu::hp_sleep_sysclk::HP_SLEEP_SYS_CLK_SLP_SEL_W
• pmu::hp_sleep_sysclk::R
• pmu::hp_sleep_sysclk::W
• pmu::hp_sleep_xtal::HP_SLEEP_XPD_XTAL_R
• pmu::hp_sleep_xtal::HP_SLEEP_XPD_XTAL_W
• pmu::hp_sleep_xtal::R
• pmu::hp_sleep_xtal::W
• pmu::imm_hp_apb_icg::UPDATE_DIG_ICG_APB_EN_W
• pmu::imm_hp_apb_icg::W
• pmu::imm_hp_ck_power::R
• pmu::imm_hp_ck_power::TIE_HIGH_GLOBAL_BBPLL_ICG_W
• pmu::imm_hp_ck_power::TIE_HIGH_GLOBAL_XTAL_ICG_W
• pmu::imm_hp_ck_power::TIE_HIGH_I2C_RETENTION_W
• pmu::imm_hp_ck_power::TIE_HIGH_XPD_BBPLL_I2C_W
• pmu::imm_hp_ck_power::TIE_HIGH_XPD_BBPLL_W
• pmu::imm_hp_ck_power::TIE_HIGH_XPD_BB_I2C_W
• pmu::imm_hp_ck_power::TIE_HIGH_XPD_XTAL_W
• pmu::imm_hp_ck_power::TIE_LOW_GLOBAL_BBPLL_ICG_W
• pmu::imm_hp_ck_power::TIE_LOW_GLOBAL_XTAL_ICG_W
• pmu::imm_hp_ck_power::TIE_LOW_I2C_RETENTION_W
• pmu::imm_hp_ck_power::TIE_LOW_XPD_BBPLL_I2C_W
• pmu::imm_hp_ck_power::TIE_LOW_XPD_BBPLL_W
• pmu::imm_hp_ck_power::TIE_LOW_XPD_BB_I2C_W
• pmu::imm_hp_ck_power::TIE_LOW_XPD_XTAL_W
• pmu::imm_hp_ck_power::W
• pmu::imm_hp_func_icg::UPDATE_DIG_ICG_FUNC_EN_W
• pmu::imm_hp_func_icg::W
• pmu::imm_i2c_iso::TIE_HIGH_I2C_ISO_EN_W
• pmu::imm_i2c_iso::TIE_LOW_I2C_ISO_EN_W
• pmu::imm_i2c_iso::W
• pmu::imm_lp_icg::TIE_HIGH_LP_ROOTCLK_SEL_W
• pmu::imm_lp_icg::TIE_LOW_LP_ROOTCLK_SEL_W
• pmu::imm_lp_icg::W
• pmu::imm_modem_icg::UPDATE_DIG_ICG_MODEM_EN_W
• pmu::imm_modem_icg::W
• pmu::imm_pad_hold_all::TIE_HIGH_HP_PAD_HOLD_ALL_W
• pmu::imm_pad_hold_all::TIE_HIGH_LP_PAD_HOLD_ALL_W
• pmu::imm_pad_hold_all::TIE_LOW_HP_PAD_HOLD_ALL_W
• pmu::imm_pad_hold_all::TIE_LOW_LP_PAD_HOLD_ALL_W
• pmu::imm_pad_hold_all::W
• pmu::imm_sleep_sysclk::TIE_HIGH_ICG_SLP_SEL_W
• pmu::imm_sleep_sysclk::TIE_LOW_ICG_SLP_SEL_W
• pmu::imm_sleep_sysclk::UPDATE_DIG_ICG_SWITCH_W
• pmu::imm_sleep_sysclk::UPDATE_DIG_SYS_CLK_SEL_W
• pmu::imm_sleep_sysclk::W
• pmu::int_clr::LP_CPU_EXC_W
• pmu::int_clr::SDIO_IDLE_W
• pmu::int_clr::SOC_SLEEP_REJECT_W
• pmu::int_clr::SOC_WAKEUP_W
• pmu::int_clr::SW_W
• pmu::int_clr::W
• pmu::int_ena::LP_CPU_EXC_R
• pmu::int_ena::LP_CPU_EXC_W
• pmu::int_ena::R
• pmu::int_ena::SDIO_IDLE_R
• pmu::int_ena::SDIO_IDLE_W
• pmu::int_ena::SOC_SLEEP_REJECT_R
• pmu::int_ena::SOC_SLEEP_REJECT_W
• pmu::int_ena::SOC_WAKEUP_R
• pmu::int_ena::SOC_WAKEUP_W
• pmu::int_ena::SW_R
• pmu::int_ena::SW_W
• pmu::int_ena::W
• pmu::int_raw::LP_CPU_EXC_R
• pmu::int_raw::LP_CPU_EXC_W
• pmu::int_raw::R
• pmu::int_raw::SDIO_IDLE_R
• pmu::int_raw::SDIO_IDLE_W
• pmu::int_raw::SOC_SLEEP_REJECT_R
• pmu::int_raw::SOC_SLEEP_REJECT_W
• pmu::int_raw::SOC_WAKEUP_R
• pmu::int_raw::SOC_WAKEUP_W
• pmu::int_raw::SW_R
• pmu::int_raw::SW_W
• pmu::int_raw::W
• pmu::int_st::LP_CPU_EXC_R
• pmu::int_st::R
• pmu::int_st::SDIO_IDLE_R
• pmu::int_st::SOC_SLEEP_REJECT_R
• pmu::int_st::SOC_WAKEUP_R
• pmu::int_st::SW_R
• pmu::lp_cpu_pwr0::LP_CPU_FORCE_STALL_R
• pmu::lp_cpu_pwr0::LP_CPU_FORCE_STALL_W
• pmu::lp_cpu_pwr0::LP_CPU_SLP_BYPASS_INTR_EN_R
• pmu::lp_cpu_pwr0::LP_CPU_SLP_BYPASS_INTR_EN_W
• pmu::lp_cpu_pwr0::LP_CPU_SLP_RESET_EN_R
• pmu::lp_cpu_pwr0::LP_CPU_SLP_RESET_EN_W
• pmu::lp_cpu_pwr0::LP_CPU_SLP_STALL_EN_R
• pmu::lp_cpu_pwr0::LP_CPU_SLP_STALL_EN_W
• pmu::lp_cpu_pwr0::LP_CPU_SLP_STALL_FLAG_EN_R
• pmu::lp_cpu_pwr0::LP_CPU_SLP_STALL_FLAG_EN_W
• pmu::lp_cpu_pwr0::LP_CPU_SLP_STALL_WAIT_R
• pmu::lp_cpu_pwr0::LP_CPU_SLP_STALL_WAIT_W
• pmu::lp_cpu_pwr0::LP_CPU_SLP_WAITI_FLAG_EN_R
• pmu::lp_cpu_pwr0::LP_CPU_SLP_WAITI_FLAG_EN_W
• pmu::lp_cpu_pwr0::LP_CPU_STALL_RDY_R
• pmu::lp_cpu_pwr0::LP_CPU_WAITI_RDY_R
• pmu::lp_cpu_pwr0::R
• pmu::lp_cpu_pwr0::W
• pmu::lp_cpu_pwr1::LP_CPU_SLEEP_REQ_W
• pmu::lp_cpu_pwr1::LP_CPU_WAKEUP_EN_R
• pmu::lp_cpu_pwr1::LP_CPU_WAKEUP_EN_W
• pmu::lp_cpu_pwr1::R
• pmu::lp_cpu_pwr1::W
• pmu::lp_int_clr::ACTIVE_SWITCH_SLEEP_END_W
• pmu::lp_int_clr::ACTIVE_SWITCH_SLEEP_START_W
• pmu::lp_int_clr::HP_SW_TRIGGER_W
• pmu::lp_int_clr::LP_CPU_WAKEUP_W
• pmu::lp_int_clr::MODEM_SWITCH_ACTIVE_END_W
• pmu::lp_int_clr::MODEM_SWITCH_ACTIVE_START_W
• pmu::lp_int_clr::MODEM_SWITCH_SLEEP_END_W
• pmu::lp_int_clr::MODEM_SWITCH_SLEEP_START_W
• pmu::lp_int_clr::SLEEP_SWITCH_ACTIVE_END_W
• pmu::lp_int_clr::SLEEP_SWITCH_ACTIVE_START_W
• pmu::lp_int_clr::SLEEP_SWITCH_MODEM_END_W
• pmu::lp_int_clr::SLEEP_SWITCH_MODEM_START_W
• pmu::lp_int_clr::W
• pmu::lp_int_ena::ACTIVE_SWITCH_SLEEP_END_R
• pmu::lp_int_ena::ACTIVE_SWITCH_SLEEP_END_W
• pmu::lp_int_ena::ACTIVE_SWITCH_SLEEP_START_R
• pmu::lp_int_ena::ACTIVE_SWITCH_SLEEP_START_W
• pmu::lp_int_ena::HP_SW_TRIGGER_R
• pmu::lp_int_ena::HP_SW_TRIGGER_W
• pmu::lp_int_ena::LP_CPU_WAKEUP_R
• pmu::lp_int_ena::LP_CPU_WAKEUP_W
• pmu::lp_int_ena::MODEM_SWITCH_ACTIVE_END_R
• pmu::lp_int_ena::MODEM_SWITCH_ACTIVE_END_W
• pmu::lp_int_ena::MODEM_SWITCH_ACTIVE_START_R
• pmu::lp_int_ena::MODEM_SWITCH_ACTIVE_START_W
• pmu::lp_int_ena::MODEM_SWITCH_SLEEP_END_R
• pmu::lp_int_ena::MODEM_SWITCH_SLEEP_END_W
• pmu::lp_int_ena::MODEM_SWITCH_SLEEP_START_R
• pmu::lp_int_ena::MODEM_SWITCH_SLEEP_START_W
• pmu::lp_int_ena::R
• pmu::lp_int_ena::SLEEP_SWITCH_ACTIVE_END_R
• pmu::lp_int_ena::SLEEP_SWITCH_ACTIVE_END_W
• pmu::lp_int_ena::SLEEP_SWITCH_ACTIVE_START_R
• pmu::lp_int_ena::SLEEP_SWITCH_ACTIVE_START_W
• pmu::lp_int_ena::SLEEP_SWITCH_MODEM_END_R
• pmu::lp_int_ena::SLEEP_SWITCH_MODEM_END_W
• pmu::lp_int_ena::SLEEP_SWITCH_MODEM_START_R
• pmu::lp_int_ena::SLEEP_SWITCH_MODEM_START_W
• pmu::lp_int_ena::W
• pmu::lp_int_raw::ACTIVE_SWITCH_SLEEP_END_R
• pmu::lp_int_raw::ACTIVE_SWITCH_SLEEP_END_W
• pmu::lp_int_raw::ACTIVE_SWITCH_SLEEP_START_R
• pmu::lp_int_raw::ACTIVE_SWITCH_SLEEP_START_W
• pmu::lp_int_raw::HP_SW_TRIGGER_R
• pmu::lp_int_raw::HP_SW_TRIGGER_W
• pmu::lp_int_raw::LP_CPU_WAKEUP_R
• pmu::lp_int_raw::LP_CPU_WAKEUP_W
• pmu::lp_int_raw::MODEM_SWITCH_ACTIVE_END_R
• pmu::lp_int_raw::MODEM_SWITCH_ACTIVE_END_W
• pmu::lp_int_raw::MODEM_SWITCH_ACTIVE_START_R
• pmu::lp_int_raw::MODEM_SWITCH_ACTIVE_START_W
• pmu::lp_int_raw::MODEM_SWITCH_SLEEP_END_R
• pmu::lp_int_raw::MODEM_SWITCH_SLEEP_END_W
• pmu::lp_int_raw::MODEM_SWITCH_SLEEP_START_R
• pmu::lp_int_raw::MODEM_SWITCH_SLEEP_START_W
• pmu::lp_int_raw::R
• pmu::lp_int_raw::SLEEP_SWITCH_ACTIVE_END_R
• pmu::lp_int_raw::SLEEP_SWITCH_ACTIVE_END_W
• pmu::lp_int_raw::SLEEP_SWITCH_ACTIVE_START_R
• pmu::lp_int_raw::SLEEP_SWITCH_ACTIVE_START_W
• pmu::lp_int_raw::SLEEP_SWITCH_MODEM_END_R
• pmu::lp_int_raw::SLEEP_SWITCH_MODEM_END_W
• pmu::lp_int_raw::SLEEP_SWITCH_MODEM_START_R
• pmu::lp_int_raw::SLEEP_SWITCH_MODEM_START_W
• pmu::lp_int_raw::W
• pmu::lp_int_st::ACTIVE_SWITCH_SLEEP_END_R
• pmu::lp_int_st::ACTIVE_SWITCH_SLEEP_START_R
• pmu::lp_int_st::HP_SW_TRIGGER_R
• pmu::lp_int_st::LP_CPU_WAKEUP_R
• pmu::lp_int_st::MODEM_SWITCH_ACTIVE_END_R
• pmu::lp_int_st::MODEM_SWITCH_ACTIVE_START_R
• pmu::lp_int_st::MODEM_SWITCH_SLEEP_END_R
• pmu::lp_int_st::MODEM_SWITCH_SLEEP_START_R
• pmu::lp_int_st::R
• pmu::lp_int_st::SLEEP_SWITCH_ACTIVE_END_R
• pmu::lp_int_st::SLEEP_SWITCH_ACTIVE_START_R
• pmu::lp_int_st::SLEEP_SWITCH_MODEM_END_R
• pmu::lp_int_st::SLEEP_SWITCH_MODEM_START_R
• pmu::lp_sleep_bias::LP_SLEEP_DBG_ATTEN_R
• pmu::lp_sleep_bias::LP_SLEEP_DBG_ATTEN_W
• pmu::lp_sleep_bias::LP_SLEEP_PD_CUR_R
• pmu::lp_sleep_bias::LP_SLEEP_PD_CUR_W
• pmu::lp_sleep_bias::LP_SLEEP_XPD_BIAS_R
• pmu::lp_sleep_bias::LP_SLEEP_XPD_BIAS_W
• pmu::lp_sleep_bias::R
• pmu::lp_sleep_bias::SLEEP_R
• pmu::lp_sleep_bias::SLEEP_W
• pmu::lp_sleep_bias::W
• pmu::lp_sleep_lp_bias_reserve::LP_SLEEP_LP_BIAS_RESERVE_W
• pmu::lp_sleep_lp_bias_reserve::W
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_PD_OSC_CLK_R
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_PD_OSC_CLK_W
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_XPD_FOSC_CLK_R
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_XPD_FOSC_CLK_W
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_XPD_RC32K_R
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_XPD_RC32K_W
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_XPD_XTAL32K_R
• pmu::lp_sleep_lp_ck_power::LP_SLEEP_XPD_XTAL32K_W
• pmu::lp_sleep_lp_ck_power::R
• pmu::lp_sleep_lp_ck_power::W
• pmu::lp_sleep_lp_dig_power::LP_SLEEP_LP_MEM_DSLP_R
• pmu::lp_sleep_lp_dig_power::LP_SLEEP_LP_MEM_DSLP_W
• pmu::lp_sleep_lp_dig_power::LP_SLEEP_PD_LP_PERI_PD_EN_R
• pmu::lp_sleep_lp_dig_power::LP_SLEEP_PD_LP_PERI_PD_EN_W
• pmu::lp_sleep_lp_dig_power::R
• pmu::lp_sleep_lp_dig_power::W
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_DBIAS_R
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_DBIAS_W
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_SLP_DBIAS_R
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_SLP_DBIAS_W
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_SLP_XPD_R
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_SLP_XPD_W
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_XPD_R
• pmu::lp_sleep_lp_regulator0::LP_SLEEP_LP_REGULATOR_XPD_W
• pmu::lp_sleep_lp_regulator0::R
• pmu::lp_sleep_lp_regulator0::W
• pmu::lp_sleep_lp_regulator1::LP_SLEEP_LP_REGULATOR_DRV_B_R
• pmu::lp_sleep_lp_regulator1::LP_SLEEP_LP_REGULATOR_DRV_B_W
• pmu::lp_sleep_lp_regulator1::R
• pmu::lp_sleep_lp_regulator1::W
• pmu::lp_sleep_xtal::LP_SLEEP_XPD_XTAL_R
• pmu::lp_sleep_xtal::LP_SLEEP_XPD_XTAL_W
• pmu::lp_sleep_xtal::R
• pmu::lp_sleep_xtal::W
• pmu::main_state::MAIN_CUR_ST_STATE_R
• pmu::main_state::MAIN_LAST_ST_STATE_R
• pmu::main_state::MAIN_TAR_ST_STATE_R
• pmu::main_state::R
• pmu::por_status::POR_DONE_R
• pmu::por_status::R
• pmu::power_ck_wait_cntl::R
• pmu::power_ck_wait_cntl::W
• pmu::power_ck_wait_cntl::WAIT_PLL_STABLE_R
• pmu::power_ck_wait_cntl::WAIT_PLL_STABLE_W
• pmu::power_ck_wait_cntl::WAIT_XTL_STABLE_R
• pmu::power_ck_wait_cntl::WAIT_XTL_STABLE_W
• pmu::power_hp_pad::FORCE_HP_PAD_ISO_ALL_R
• pmu::power_hp_pad::FORCE_HP_PAD_ISO_ALL_W
• pmu::power_hp_pad::FORCE_HP_PAD_NO_ISO_ALL_R
• pmu::power_hp_pad::FORCE_HP_PAD_NO_ISO_ALL_W
• pmu::power_hp_pad::R
• pmu::power_hp_pad::W
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_ISO_R
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_ISO_W
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_NO_ISO_R
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_NO_ISO_W
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_NO_RESET_R
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_NO_RESET_W
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_PD_R
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_PD_W
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_PU_R
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_PU_W
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_RESET_R
• pmu::power_pd_hpaon_cntl::FORCE_HP_AON_RESET_W
• pmu::power_pd_hpaon_cntl::PD_HP_AON_MASK_R
• pmu::power_pd_hpaon_cntl::PD_HP_AON_MASK_W
• pmu::power_pd_hpaon_cntl::PD_HP_AON_PD_MASK_R
• pmu::power_pd_hpaon_cntl::PD_HP_AON_PD_MASK_W
• pmu::power_pd_hpaon_cntl::R
• pmu::power_pd_hpaon_cntl::W
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_ISO_R
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_ISO_W
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_NO_ISO_R
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_NO_ISO_W
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_NO_RESET_R
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_NO_RESET_W
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_PD_R
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_PD_W
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_PU_R
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_PU_W
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_RESET_R
• pmu::power_pd_hpcpu_cntl::FORCE_HP_CPU_RESET_W
• pmu::power_pd_hpcpu_cntl::PD_HP_CPU_MASK_R
• pmu::power_pd_hpcpu_cntl::PD_HP_CPU_MASK_W
• pmu::power_pd_hpcpu_cntl::PD_HP_CPU_PD_MASK_R
• pmu::power_pd_hpcpu_cntl::PD_HP_CPU_PD_MASK_W
• pmu::power_pd_hpcpu_cntl::R
• pmu::power_pd_hpcpu_cntl::W
• pmu::power_pd_hpperi_reserve::HP_PERI_RESERVE_W
• pmu::power_pd_hpperi_reserve::W
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_ISO_R
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_ISO_W
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_NO_ISO_R
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_NO_ISO_W
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_NO_RESET_R
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_NO_RESET_W
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_PD_R
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_PD_W
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_PU_R
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_PU_W
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_RESET_R
• pmu::power_pd_hpwifi_cntl::FORCE_HP_WIFI_RESET_W
• pmu::power_pd_hpwifi_cntl::PD_HP_WIFI_MASK_R
• pmu::power_pd_hpwifi_cntl::PD_HP_WIFI_MASK_W
• pmu::power_pd_hpwifi_cntl::PD_HP_WIFI_PD_MASK_R
• pmu::power_pd_hpwifi_cntl::PD_HP_WIFI_PD_MASK_W
• pmu::power_pd_hpwifi_cntl::R
• pmu::power_pd_hpwifi_cntl::W
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_ISO_R
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_ISO_W
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_NO_ISO_R
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_NO_ISO_W
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_NO_RESET_R
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_NO_RESET_W
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_PD_R
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_PD_W
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_PU_R
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_PU_W
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_RESET_R
• pmu::power_pd_lpperi_cntl::FORCE_LP_PERI_RESET_W
• pmu::power_pd_lpperi_cntl::R
• pmu::power_pd_lpperi_cntl::W
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_ISO_R
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_ISO_W
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_NO_ISO_R
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_NO_ISO_W
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_PD_R
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_PD_W
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_PU_R
• pmu::power_pd_mem_cntl::FORCE_HP_MEM_PU_W
• pmu::power_pd_mem_cntl::R
• pmu::power_pd_mem_cntl::W
• pmu::power_pd_mem_mask::PD_HP_MEM0_MASK_R
• pmu::power_pd_mem_mask::PD_HP_MEM0_MASK_W
• pmu::power_pd_mem_mask::PD_HP_MEM0_PD_MASK_R
• pmu::power_pd_mem_mask::PD_HP_MEM0_PD_MASK_W
• pmu::power_pd_mem_mask::PD_HP_MEM1_MASK_R
• pmu::power_pd_mem_mask::PD_HP_MEM1_MASK_W
• pmu::power_pd_mem_mask::PD_HP_MEM1_PD_MASK_R
• pmu::power_pd_mem_mask::PD_HP_MEM1_PD_MASK_W
• pmu::power_pd_mem_mask::PD_HP_MEM2_MASK_R
• pmu::power_pd_mem_mask::PD_HP_MEM2_MASK_W
• pmu::power_pd_mem_mask::PD_HP_MEM2_PD_MASK_R
• pmu::power_pd_mem_mask::PD_HP_MEM2_PD_MASK_W
• pmu::power_pd_mem_mask::R
• pmu::power_pd_mem_mask::W
• pmu::power_pd_top_cntl::FORCE_TOP_ISO_R
• pmu::power_pd_top_cntl::FORCE_TOP_ISO_W
• pmu::power_pd_top_cntl::FORCE_TOP_NO_ISO_R
• pmu::power_pd_top_cntl::FORCE_TOP_NO_ISO_W
• pmu::power_pd_top_cntl::FORCE_TOP_NO_RESET_R
• pmu::power_pd_top_cntl::FORCE_TOP_NO_RESET_W
• pmu::power_pd_top_cntl::FORCE_TOP_PD_R
• pmu::power_pd_top_cntl::FORCE_TOP_PD_W
• pmu::power_pd_top_cntl::FORCE_TOP_PU_R
• pmu::power_pd_top_cntl::FORCE_TOP_PU_W
• pmu::power_pd_top_cntl::FORCE_TOP_RESET_R
• pmu::power_pd_top_cntl::FORCE_TOP_RESET_W
• pmu::power_pd_top_cntl::PD_TOP_MASK_R
• pmu::power_pd_top_cntl::PD_TOP_MASK_W
• pmu::power_pd_top_cntl::PD_TOP_PD_MASK_R
• pmu::power_pd_top_cntl::PD_TOP_PD_MASK_W
• pmu::power_pd_top_cntl::R
• pmu::power_pd_top_cntl::W
• pmu::power_vdd_spi_cntl::R
• pmu::power_vdd_spi_cntl::VDD_SPI_PWR_SEL_SW_R
• pmu::power_vdd_spi_cntl::VDD_SPI_PWR_SEL_SW_W
• pmu::power_vdd_spi_cntl::VDD_SPI_PWR_SW_R
• pmu::power_vdd_spi_cntl::VDD_SPI_PWR_SW_W
• pmu::power_vdd_spi_cntl::VDD_SPI_PWR_WAIT_R
• pmu::power_vdd_spi_cntl::VDD_SPI_PWR_WAIT_W
• pmu::power_vdd_spi_cntl::W
• pmu::power_wait_timer0::DG_HP_POWERDOWN_TIMER_R
• pmu::power_wait_timer0::DG_HP_POWERDOWN_TIMER_W
• pmu::power_wait_timer0::DG_HP_POWERUP_TIMER_R
• pmu::power_wait_timer0::DG_HP_POWERUP_TIMER_W
• pmu::power_wait_timer0::DG_HP_WAIT_TIMER_R
• pmu::power_wait_timer0::DG_HP_WAIT_TIMER_W
• pmu::power_wait_timer0::R
• pmu::power_wait_timer0::W
• pmu::power_wait_timer1::DG_LP_POWERDOWN_TIMER_R
• pmu::power_wait_timer1::DG_LP_POWERDOWN_TIMER_W
• pmu::power_wait_timer1::DG_LP_POWERUP_TIMER_R
• pmu::power_wait_timer1::DG_LP_POWERUP_TIMER_W
• pmu::power_wait_timer1::DG_LP_WAIT_TIMER_R
• pmu::power_wait_timer1::DG_LP_WAIT_TIMER_W
• pmu::power_wait_timer1::R
• pmu::power_wait_timer1::W
• pmu::pwr_state::BACKUP_ST_STATE_R
• pmu::pwr_state::HP_PWR_ST_STATE_R
• pmu::pwr_state::LP_PWR_ST_STATE_R
• pmu::pwr_state::R
• pmu::rf_pwc::PERIF_I2C_RSTB_R
• pmu::rf_pwc::PERIF_I2C_RSTB_W
• pmu::rf_pwc::R
• pmu::rf_pwc::W
• pmu::rf_pwc::XPD_CKGEN_I2C_R
• pmu::rf_pwc::XPD_CKGEN_I2C_W
• pmu::rf_pwc::XPD_PERIF_I2C_R
• pmu::rf_pwc::XPD_PERIF_I2C_W
• pmu::rf_pwc::XPD_PLL_I2C_R
• pmu::rf_pwc::XPD_PLL_I2C_W
• pmu::rf_pwc::XPD_RFRX_PBUS_R
• pmu::rf_pwc::XPD_RFRX_PBUS_W
• pmu::rf_pwc::XPD_TXRF_I2C_R
• pmu::rf_pwc::XPD_TXRF_I2C_W
• pmu::slp_wakeup_cntl0::SLEEP_REQ_W
• pmu::slp_wakeup_cntl0::W
• pmu::slp_wakeup_cntl1::R
• pmu::slp_wakeup_cntl1::SLEEP_REJECT_ENA_R
• pmu::slp_wakeup_cntl1::SLEEP_REJECT_ENA_W
• pmu::slp_wakeup_cntl1::SLP_REJECT_EN_R
• pmu::slp_wakeup_cntl1::SLP_REJECT_EN_W
• pmu::slp_wakeup_cntl1::W
• pmu::slp_wakeup_cntl2::R
• pmu::slp_wakeup_cntl2::W
• pmu::slp_wakeup_cntl2::WAKEUP_ENA_R
• pmu::slp_wakeup_cntl2::WAKEUP_ENA_W
• pmu::slp_wakeup_cntl3::HP_MIN_SLP_VAL_R
• pmu::slp_wakeup_cntl3::HP_MIN_SLP_VAL_W
• pmu::slp_wakeup_cntl3::LP_MIN_SLP_VAL_R
• pmu::slp_wakeup_cntl3::LP_MIN_SLP_VAL_W
• pmu::slp_wakeup_cntl3::R
• pmu::slp_wakeup_cntl3::SLEEP_PRT_SEL_R
• pmu::slp_wakeup_cntl3::SLEEP_PRT_SEL_W
• pmu::slp_wakeup_cntl3::W
• pmu::slp_wakeup_cntl4::SLP_REJECT_CAUSE_CLR_W
• pmu::slp_wakeup_cntl4::W
• pmu::slp_wakeup_cntl5::LP_ANA_WAIT_TARGET_R
• pmu::slp_wakeup_cntl5::LP_ANA_WAIT_TARGET_W
• pmu::slp_wakeup_cntl5::MODEM_WAIT_TARGET_R
• pmu::slp_wakeup_cntl5::MODEM_WAIT_TARGET_W
• pmu::slp_wakeup_cntl5::R
• pmu::slp_wakeup_cntl5::W
• pmu::slp_wakeup_cntl6::R
• pmu::slp_wakeup_cntl6::SOC_WAKEUP_WAIT_CFG_R
• pmu::slp_wakeup_cntl6::SOC_WAKEUP_WAIT_CFG_W
• pmu::slp_wakeup_cntl6::SOC_WAKEUP_WAIT_R
• pmu::slp_wakeup_cntl6::SOC_WAKEUP_WAIT_W
• pmu::slp_wakeup_cntl6::W
• pmu::slp_wakeup_cntl7::ANA_WAIT_TARGET_R
• pmu::slp_wakeup_cntl7::ANA_WAIT_TARGET_W
• pmu::slp_wakeup_cntl7::R
• pmu::slp_wakeup_cntl7::W
• pmu::slp_wakeup_status0::R
• pmu::slp_wakeup_status0::WAKEUP_CAUSE_R
• pmu::slp_wakeup_status1::R
• pmu::slp_wakeup_status1::REJECT_CAUSE_R
• pmu::vdd_spi_status::R
• pmu::vdd_spi_status::STABLE_VDD_SPI_PWR_DRV_R
• rmt::CHCARRIER_DUTY
• rmt::CHDATA
• rmt::CH_RX_CARRIER_RM
• rmt::CH_RX_CONF0
• rmt::CH_RX_CONF1
• rmt::CH_RX_LIM
• rmt::CH_RX_STATUS
• rmt::CH_TX_CONF0
• rmt::CH_TX_LIM
• rmt::CH_TX_STATUS
• rmt::DATE
• rmt::INT_CLR
• rmt::INT_ENA
• rmt::INT_RAW
• rmt::INT_ST
• rmt::REF_CNT_RST
• rmt::SYS_CONF
• rmt::TX_SIM
• rmt::ch_rx_carrier_rm::CARRIER_HIGH_THRES_R
• rmt::ch_rx_carrier_rm::CARRIER_HIGH_THRES_W
• rmt::ch_rx_carrier_rm::CARRIER_LOW_THRES_R
• rmt::ch_rx_carrier_rm::CARRIER_LOW_THRES_W
• rmt::ch_rx_carrier_rm::R
• rmt::ch_rx_carrier_rm::W
• rmt::ch_rx_conf0::CARRIER_EN_R
• rmt::ch_rx_conf0::CARRIER_EN_W
• rmt::ch_rx_conf0::CARRIER_OUT_LV_R
• rmt::ch_rx_conf0::CARRIER_OUT_LV_W
• rmt::ch_rx_conf0::DIV_CNT_R
• rmt::ch_rx_conf0::DIV_CNT_W
• rmt::ch_rx_conf0::IDLE_THRES_R
• rmt::ch_rx_conf0::IDLE_THRES_W
• rmt::ch_rx_conf0::MEM_SIZE_R
• rmt::ch_rx_conf0::MEM_SIZE_W
• rmt::ch_rx_conf0::R
• rmt::ch_rx_conf0::W
• rmt::ch_rx_conf1::AFIFO_RST_W
• rmt::ch_rx_conf1::APB_MEM_RST_W
• rmt::ch_rx_conf1::CONF_UPDATE_W
• rmt::ch_rx_conf1::MEM_OWNER_R
• rmt::ch_rx_conf1::MEM_OWNER_W
• rmt::ch_rx_conf1::MEM_RX_WRAP_EN_R
• rmt::ch_rx_conf1::MEM_RX_WRAP_EN_W
• rmt::ch_rx_conf1::MEM_WR_RST_W
• rmt::ch_rx_conf1::R
• rmt::ch_rx_conf1::RX_EN_R
• rmt::ch_rx_conf1::RX_EN_W
• rmt::ch_rx_conf1::RX_FILTER_EN_R
• rmt::ch_rx_conf1::RX_FILTER_EN_W
• rmt::ch_rx_conf1::RX_FILTER_THRES_R
• rmt::ch_rx_conf1::RX_FILTER_THRES_W
• rmt::ch_rx_conf1::W
• rmt::ch_rx_lim::R
• rmt::ch_rx_lim::RMT_RX_LIM_R
• rmt::ch_rx_lim::RMT_RX_LIM_W
• rmt::ch_rx_lim::W
• rmt::ch_rx_status::APB_MEM_RADDR_R
• rmt::ch_rx_status::APB_MEM_RD_ERR_R
• rmt::ch_rx_status::MEM_FULL_R
• rmt::ch_rx_status::MEM_OWNER_ERR_R
• rmt::ch_rx_status::MEM_WADDR_EX_R
• rmt::ch_rx_status::R
• rmt::ch_rx_status::STATE_R
• rmt::ch_tx_conf0::AFIFO_RST_W
• rmt::ch_tx_conf0::APB_MEM_RST_W
• rmt::ch_tx_conf0::CARRIER_EFF_EN_R
• rmt::ch_tx_conf0::CARRIER_EFF_EN_W
• rmt::ch_tx_conf0::CARRIER_EN_R
• rmt::ch_tx_conf0::CARRIER_EN_W
• rmt::ch_tx_conf0::CARRIER_OUT_LV_R
• rmt::ch_tx_conf0::CARRIER_OUT_LV_W
• rmt::ch_tx_conf0::CONF_UPDATE_W
• rmt::ch_tx_conf0::DIV_CNT_R
• rmt::ch_tx_conf0::DIV_CNT_W
• rmt::ch_tx_conf0::IDLE_OUT_EN_R
• rmt::ch_tx_conf0::IDLE_OUT_EN_W
• rmt::ch_tx_conf0::IDLE_OUT_LV_R
• rmt::ch_tx_conf0::IDLE_OUT_LV_W
• rmt::ch_tx_conf0::MEM_RD_RST_W
• rmt::ch_tx_conf0::MEM_SIZE_R
• rmt::ch_tx_conf0::MEM_SIZE_W
• rmt::ch_tx_conf0::MEM_TX_WRAP_EN_R
• rmt::ch_tx_conf0::MEM_TX_WRAP_EN_W
• rmt::ch_tx_conf0::R
• rmt::ch_tx_conf0::TX_CONTI_MODE_R
• rmt::ch_tx_conf0::TX_CONTI_MODE_W
• rmt::ch_tx_conf0::TX_START_W
• rmt::ch_tx_conf0::TX_STOP_R
• rmt::ch_tx_conf0::TX_STOP_W
• rmt::ch_tx_conf0::W
• rmt::ch_tx_lim::LOOP_COUNT_RESET_W
• rmt::ch_tx_lim::LOOP_STOP_EN_R
• rmt::ch_tx_lim::LOOP_STOP_EN_W
• rmt::ch_tx_lim::R
• rmt::ch_tx_lim::TX_LIM_R
• rmt::ch_tx_lim::TX_LIM_W
• rmt::ch_tx_lim::TX_LOOP_CNT_EN_R
• rmt::ch_tx_lim::TX_LOOP_CNT_EN_W
• rmt::ch_tx_lim::TX_LOOP_NUM_R
• rmt::ch_tx_lim::TX_LOOP_NUM_W
• rmt::ch_tx_lim::W
• rmt::ch_tx_status::APB_MEM_RADDR_R
• rmt::ch_tx_status::APB_MEM_RD_ERR_R
• rmt::ch_tx_status::APB_MEM_WADDR_R
• rmt::ch_tx_status::APB_MEM_WR_ERR_R
• rmt::ch_tx_status::MEM_EMPTY_R
• rmt::ch_tx_status::MEM_RADDR_EX_R
• rmt::ch_tx_status::R
• rmt::ch_tx_status::STATE_R
• rmt::chcarrier_duty::CARRIER_HIGH_R
• rmt::chcarrier_duty::CARRIER_HIGH_W
• rmt::chcarrier_duty::CARRIER_LOW_R
• rmt::chcarrier_duty::CARRIER_LOW_W
• rmt::chcarrier_duty::R
• rmt::chcarrier_duty::W
• rmt::chdata::DATA_R
• rmt::chdata::DATA_W
• rmt::chdata::R
• rmt::chdata::W
• rmt::date::R
• rmt::date::RMT_DATE_R
• rmt::date::RMT_DATE_W
• rmt::date::W
• rmt::int_clr::CH_RX_END_W
• rmt::int_clr::CH_RX_ERR_W
• rmt::int_clr::CH_RX_THR_EVENT_W
• rmt::int_clr::CH_TX_END_W
• rmt::int_clr::CH_TX_ERR_W
• rmt::int_clr::CH_TX_LOOP_W
• rmt::int_clr::CH_TX_THR_EVENT_W
• rmt::int_clr::W
• rmt::int_ena::CH_RX_END_R
• rmt::int_ena::CH_RX_END_W
• rmt::int_ena::CH_RX_ERR_R
• rmt::int_ena::CH_RX_ERR_W
• rmt::int_ena::CH_RX_THR_EVENT_R
• rmt::int_ena::CH_RX_THR_EVENT_W
• rmt::int_ena::CH_TX_END_R
• rmt::int_ena::CH_TX_END_W
• rmt::int_ena::CH_TX_ERR_R
• rmt::int_ena::CH_TX_ERR_W
• rmt::int_ena::CH_TX_THR_EVENT_R
• rmt::int_ena::CH_TX_THR_EVENT_W
• rmt::int_ena::CH_X_LOOP_R
• rmt::int_ena::CH_X_LOOP_W
• rmt::int_ena::R
• rmt::int_ena::W
• rmt::int_raw::CH_RX_END_R
• rmt::int_raw::CH_RX_END_W
• rmt::int_raw::CH_RX_ERR_R
• rmt::int_raw::CH_RX_ERR_W
• rmt::int_raw::CH_RX_THR_EVENT_R
• rmt::int_raw::CH_RX_THR_EVENT_W
• rmt::int_raw::CH_TX_END_R
• rmt::int_raw::CH_TX_END_W
• rmt::int_raw::CH_TX_ERR_R
• rmt::int_raw::CH_TX_ERR_W
• rmt::int_raw::CH_TX_LOOP_R
• rmt::int_raw::CH_TX_LOOP_W
• rmt::int_raw::CH_TX_THR_EVENT_R
• rmt::int_raw::CH_TX_THR_EVENT_W
• rmt::int_raw::R
• rmt::int_raw::W
• rmt::int_st::CH_RX_END_R
• rmt::int_st::CH_RX_ERR_R
• rmt::int_st::CH_RX_THR_EVENT_R
• rmt::int_st::CH_TX_END_R
• rmt::int_st::CH_TX_ERR_R
• rmt::int_st::CH_TX_THR_EVENT_R
• rmt::int_st::CH_X_LOOP_R
• rmt::int_st::R
• rmt::ref_cnt_rst::RX_REF_CNT_RST_CH2_W
• rmt::ref_cnt_rst::RX_REF_CNT_RST_CH3_W
• rmt::ref_cnt_rst::TX_REF_CNT_RST_CH1_W
• rmt::ref_cnt_rst::TX_REF_CNT_RST_W
• rmt::ref_cnt_rst::W
• rmt::sys_conf::APB_FIFO_MASK_R
• rmt::sys_conf::APB_FIFO_MASK_W
• rmt::sys_conf::CLK_EN_R
• rmt::sys_conf::CLK_EN_W
• rmt::sys_conf::MEM_CLK_FORCE_ON_R
• rmt::sys_conf::MEM_CLK_FORCE_ON_W
• rmt::sys_conf::MEM_FORCE_PD_R
• rmt::sys_conf::MEM_FORCE_PD_W
• rmt::sys_conf::MEM_FORCE_PU_R
• rmt::sys_conf::MEM_FORCE_PU_W
• rmt::sys_conf::R
• rmt::sys_conf::W
• rmt::tx_sim::CH0_R
• rmt::tx_sim::CH0_W
• rmt::tx_sim::CH1_R
• rmt::tx_sim::CH1_W
• rmt::tx_sim::EN_R
• rmt::tx_sim::EN_W
• rmt::tx_sim::R
• rmt::tx_sim::W
• rng::DATA
• rng::data::R
• rsa::CONSTANT_TIME
• rsa::DATE
• rsa::INT_CLR
• rsa::INT_ENA
• rsa::MODE
• rsa::M_MEM
• rsa::M_PRIME
• rsa::QUERY_CLEAN
• rsa::QUERY_IDLE
• rsa::SEARCH_ENABLE
• rsa::SEARCH_POS
• rsa::SET_START_MODEXP
• rsa::SET_START_MODMULT
• rsa::SET_START_MULT
• rsa::X_MEM
• rsa::Y_MEM
• rsa::Z_MEM
• rsa::constant_time::CONSTANT_TIME_R
• rsa::constant_time::CONSTANT_TIME_W
• rsa::constant_time::R
• rsa::constant_time::W
• rsa::date::DATE_R
• rsa::date::DATE_W
• rsa::date::R
• rsa::date::W
• rsa::int_clr::INT_CLR_R
• rsa::int_clr::INT_CLR_W
• rsa::int_clr::R
• rsa::int_clr::W
• rsa::int_ena::INT_ENA_R
• rsa::int_ena::INT_ENA_W
• rsa::int_ena::R
• rsa::int_ena::W
• rsa::m_mem::R
• rsa::m_mem::W
• rsa::m_prime::M_PRIME_R
• rsa::m_prime::M_PRIME_W
• rsa::m_prime::R
• rsa::m_prime::W
• rsa::mode::MODE_R
• rsa::mode::MODE_W
• rsa::mode::R
• rsa::mode::W
• rsa::query_clean::QUERY_CLEAN_R
• rsa::query_clean::R
• rsa::query_idle::QUERY_IDLE_R
• rsa::query_idle::R
• rsa::search_enable::R
• rsa::search_enable::SEARCH_ENABLE_R
• rsa::search_enable::SEARCH_ENABLE_W
• rsa::search_enable::W
• rsa::search_pos::R
• rsa::search_pos::SEARCH_POS_R
• rsa::search_pos::SEARCH_POS_W
• rsa::search_pos::W
• rsa::set_start_modexp::SET_START_MODEXP_W
• rsa::set_start_modexp::W
• rsa::set_start_modmult::SET_START_MODMULT_W
• rsa::set_start_modmult::W
• rsa::set_start_mult::SET_START_MULT_W
• rsa::set_start_mult::W
• rsa::x_mem::R
• rsa::x_mem::W
• rsa::y_mem::R
• rsa::y_mem::W
• rsa::z_mem::R
• rsa::z_mem::W
• sha::BUSY
• sha::CLEAR_IRQ
• sha::CONTINUE
• sha::DATE
• sha::DMA_BLOCK_NUM
• sha::DMA_CONTINUE
• sha::DMA_START
• sha::H_MEM
• sha::IRQ_ENA
• sha::MODE
• sha::M_MEM
• sha::START
• sha::T_LENGTH
• sha::T_STRING
• sha::busy::R
• sha::busy::STATE_R
• sha::clear_irq::CLEAR_INTERRUPT_W
• sha::clear_irq::W
• sha::continue_::CONTINUE_W
• sha::continue_::W
• sha::date::DATE_R
• sha::date::DATE_W
• sha::date::R
• sha::date::W
• sha::dma_block_num::DMA_BLOCK_NUM_R
• sha::dma_block_num::DMA_BLOCK_NUM_W
• sha::dma_block_num::R
• sha::dma_block_num::W
• sha::dma_continue::DMA_CONTINUE_W
• sha::dma_continue::W
• sha::dma_start::DMA_START_W
• sha::dma_start::W
• sha::h_mem::R
• sha::h_mem::W
• sha::irq_ena::INTERRUPT_ENA_R
• sha::irq_ena::INTERRUPT_ENA_W
• sha::irq_ena::R
• sha::irq_ena::W
• sha::m_mem::R
• sha::m_mem::W
• sha::mode::MODE_R
• sha::mode::MODE_W
• sha::mode::R
• sha::mode::W
• sha::start::START_W
• sha::start::W
• sha::t_length::R
• sha::t_length::T_LENGTH_R
• sha::t_length::T_LENGTH_W
• sha::t_length::W
• sha::t_string::R
• sha::t_string::T_STRING_R
• sha::t_string::T_STRING_W
• sha::t_string::W
• slc::SLC0INT_CLR
• slc::SLC0INT_ENA
• slc::SLC0INT_RAW
• slc::SLC0INT_ST
• slc::SLC0RX_LINK
• slc::SLC0RX_LINK_ADDR
• slc::SLC0TOKEN1
• slc::SLC0TX_LINK
• slc::SLC0TX_LINK_ADDR
• slc::SLC0_LENGTH
• slc::SLC0_LEN_CONF
• slc::SLC0_RX_SHAREMEM_END
• slc::SLC0_RX_SHAREMEM_START
• slc::SLC0_TX_SHAREMEM_END
• slc::SLC0_TX_SHAREMEM_START
• slc::SLC1INT_CLR
• slc::SLC1INT_ENA1
• slc::SLC1INT_RAW
• slc::SLC1INT_ST1
• slc::SLC1RX_LINK
• slc::SLC1RX_LINK_ADDR
• slc::SLC1TOKEN1
• slc::SLC1TX_LINK
• slc::SLC1TX_LINK_ADDR
• slc::SLC1_RX_SHAREMEM_END
• slc::SLC1_RX_SHAREMEM_START
• slc::SLC1_TX_SHAREMEM_END
• slc::SLC1_TX_SHAREMEM_START
• slc::SLCCONF0
• slc::SLCCONF1
• slc::SLCINTVEC_TOHOST
• slc::SLC_BURST_LEN
• slc::SLC_RX_DSCR_CONF
• slc::slc0_len_conf::SDIO_SLC0_LEN_INC_MORE_W
• slc::slc0_len_conf::SDIO_SLC0_LEN_INC_W
• slc::slc0_len_conf::SDIO_SLC0_LEN_WDATA_W
• slc::slc0_len_conf::SDIO_SLC0_LEN_WR_W
• slc::slc0_len_conf::W
• slc::slc0_length::R
• slc::slc0_length::SDIO_SLC0_LEN_R
• slc::slc0_rx_sharemem_end::R
• slc::slc0_rx_sharemem_end::SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_R
• slc::slc0_rx_sharemem_end::SDIO_SDIO_SLC0_RX_SHAREMEM_END_ADDR_W
• slc::slc0_rx_sharemem_end::W
• slc::slc0_rx_sharemem_start::R
• slc::slc0_rx_sharemem_start::SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_R
• slc::slc0_rx_sharemem_start::SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_W
• slc::slc0_rx_sharemem_start::W
• slc::slc0_tx_sharemem_end::R
• slc::slc0_tx_sharemem_end::SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_R
• slc::slc0_tx_sharemem_end::SDIO_SDIO_SLC0_TX_SHAREMEM_END_ADDR_W
• slc::slc0_tx_sharemem_end::W
• slc::slc0_tx_sharemem_start::R
• slc::slc0_tx_sharemem_start::SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_R
• slc::slc0_tx_sharemem_start::SDIO_SDIO_SLC0_TX_SHAREMEM_START_ADDR_W
• slc::slc0_tx_sharemem_start::W
• slc::slc0int_clr::SDIO_SLC0_RX_CLRART_INT_CLR_W
• slc::slc0int_clr::SDIO_SLC0_RX_DONE_INT_CLR_W
• slc::slc0int_clr::SDIO_SLC0_RX_DSCR_ERR_INT_CLR_W
• slc::slc0int_clr::SDIO_SLC0_RX_EOF_INT_CLR_W
• slc::slc0int_clr::SDIO_SLC0_RX_UDF_INT_CLR_W
• slc::slc0int_clr::SDIO_SLC0_TX_CLRART_INT_CLR_W
• slc::slc0int_clr::SDIO_SLC0_TX_DONE_INT_CLR_W
• slc::slc0int_clr::SDIO_SLC0_TX_DSCR_ERR_INT_CLR_W
• slc::slc0int_clr::SDIO_SLC0_TX_OVF_INT_CLR_W
• slc::slc0int_clr::SDIO_SLC0_TX_SUC_EOF_INT_CLR_W
• slc::slc0int_clr::SDIO_SLC_FRHOST_BIT_INT_CLR_W
• slc::slc0int_clr::W
• slc::slc0int_ena::R
• slc::slc0int_ena::SDIO_SLC0_RX_DONE_INT_ENA_R
• slc::slc0int_ena::SDIO_SLC0_RX_DONE_INT_ENA_W
• slc::slc0int_ena::SDIO_SLC0_RX_DSCR_ERR_INT_ENA_R
• slc::slc0int_ena::SDIO_SLC0_RX_DSCR_ERR_INT_ENA_W
• slc::slc0int_ena::SDIO_SLC0_RX_ENAART_INT_ENA_R
• slc::slc0int_ena::SDIO_SLC0_RX_ENAART_INT_ENA_W
• slc::slc0int_ena::SDIO_SLC0_RX_EOF_INT_ENA_R
• slc::slc0int_ena::SDIO_SLC0_RX_EOF_INT_ENA_W
• slc::slc0int_ena::SDIO_SLC0_RX_UDF_INT_ENA_R
• slc::slc0int_ena::SDIO_SLC0_RX_UDF_INT_ENA_W
• slc::slc0int_ena::SDIO_SLC0_TX_DONE_INT_ENA_R
• slc::slc0int_ena::SDIO_SLC0_TX_DONE_INT_ENA_W
• slc::slc0int_ena::SDIO_SLC0_TX_DSCR_ERR_INT_ENA_R
• slc::slc0int_ena::SDIO_SLC0_TX_DSCR_ERR_INT_ENA_W
• slc::slc0int_ena::SDIO_SLC0_TX_ENAART_INT_ENA_R
• slc::slc0int_ena::SDIO_SLC0_TX_ENAART_INT_ENA_W
• slc::slc0int_ena::SDIO_SLC0_TX_OVF_INT_ENA_R
• slc::slc0int_ena::SDIO_SLC0_TX_OVF_INT_ENA_W
• slc::slc0int_ena::SDIO_SLC0_TX_SUC_EOF_INT_ENA_R
• slc::slc0int_ena::SDIO_SLC0_TX_SUC_EOF_INT_ENA_W
• slc::slc0int_ena::SDIO_SLC_FRHOST_BIT_INT_ENA_R
• slc::slc0int_ena::SDIO_SLC_FRHOST_BIT_INT_ENA_W
• slc::slc0int_ena::W
• slc::slc0int_raw::R
• slc::slc0int_raw::SDIO_SLC0_RX_DONE_INT_RAW_R
• slc::slc0int_raw::SDIO_SLC0_RX_DONE_INT_RAW_W
• slc::slc0int_raw::SDIO_SLC0_RX_DSCR_ERR_INT_RAW_R
• slc::slc0int_raw::SDIO_SLC0_RX_DSCR_ERR_INT_RAW_W
• slc::slc0int_raw::SDIO_SLC0_RX_EOF_INT_RAW_R
• slc::slc0int_raw::SDIO_SLC0_RX_EOF_INT_RAW_W
• slc::slc0int_raw::SDIO_SLC0_RX_START_INT_RAW_R
• slc::slc0int_raw::SDIO_SLC0_RX_START_INT_RAW_W
• slc::slc0int_raw::SDIO_SLC0_RX_UDF_INT_RAW_R
• slc::slc0int_raw::SDIO_SLC0_RX_UDF_INT_RAW_W
• slc::slc0int_raw::SDIO_SLC0_TX_DONE_INT_RAW_R
• slc::slc0int_raw::SDIO_SLC0_TX_DONE_INT_RAW_W
• slc::slc0int_raw::SDIO_SLC0_TX_DSCR_ERR_INT_RAW_R
• slc::slc0int_raw::SDIO_SLC0_TX_DSCR_ERR_INT_RAW_W
• slc::slc0int_raw::SDIO_SLC0_TX_OVF_INT_RAW_R
• slc::slc0int_raw::SDIO_SLC0_TX_OVF_INT_RAW_W
• slc::slc0int_raw::SDIO_SLC0_TX_START_INT_RAW_R
• slc::slc0int_raw::SDIO_SLC0_TX_START_INT_RAW_W
• slc::slc0int_raw::SDIO_SLC0_TX_SUC_EOF_INT_RAW_R
• slc::slc0int_raw::SDIO_SLC0_TX_SUC_EOF_INT_RAW_W
• slc::slc0int_raw::SDIO_SLC_FRHOST_BIT_INT_RAW_R
• slc::slc0int_raw::SDIO_SLC_FRHOST_BIT_INT_RAW_W
• slc::slc0int_raw::W
• slc::slc0int_st::R
• slc::slc0int_st::SDIO_SLC0_RX_DONE_INT_ST_R
• slc::slc0int_st::SDIO_SLC0_RX_DSCR_ERR_INT_ST_R
• slc::slc0int_st::SDIO_SLC0_RX_EOF_INT_ST_R
• slc::slc0int_st::SDIO_SLC0_RX_START_INT_ST_R
• slc::slc0int_st::SDIO_SLC0_RX_UDF_INT_ST_R
• slc::slc0int_st::SDIO_SLC0_TX_DONE_INT_ST_R
• slc::slc0int_st::SDIO_SLC0_TX_DSCR_ERR_INT_ST_R
• slc::slc0int_st::SDIO_SLC0_TX_OVF_INT_ST_R
• slc::slc0int_st::SDIO_SLC0_TX_START_INT_ST_R
• slc::slc0int_st::SDIO_SLC0_TX_SUC_EOF_INT_ST_R
• slc::slc0int_st::SDIO_SLC_FRHOST_BIT_INT_ST_R
• slc::slc0rx_link::R
• slc::slc0rx_link::SDIO_SLC0_RXLINK_PARK_R
• slc::slc0rx_link::SDIO_SLC0_RXLINK_PARK_W
• slc::slc0rx_link::SDIO_SLC0_RXLINK_RESTART_R
• slc::slc0rx_link::SDIO_SLC0_RXLINK_RESTART_W
• slc::slc0rx_link::SDIO_SLC0_RXLINK_START_R
• slc::slc0rx_link::SDIO_SLC0_RXLINK_START_W
• slc::slc0rx_link::SDIO_SLC0_RXLINK_STOP_R
• slc::slc0rx_link::SDIO_SLC0_RXLINK_STOP_W
• slc::slc0rx_link::W
• slc::slc0rx_link_addr::R
• slc::slc0rx_link_addr::SDIO_SLC0_RXLINK_ADDR_R
• slc::slc0rx_link_addr::SDIO_SLC0_RXLINK_ADDR_W
• slc::slc0rx_link_addr::W
• slc::slc0token1::R
• slc::slc0token1::SDIO_SLC0_TOKEN1_INC_MORE_W
• slc::slc0token1::SDIO_SLC0_TOKEN1_INC_W
• slc::slc0token1::SDIO_SLC0_TOKEN1_R
• slc::slc0token1::SDIO_SLC0_TOKEN1_WDATA_W
• slc::slc0token1::SDIO_SLC0_TOKEN1_WR_W
• slc::slc0token1::W
• slc::slc0tx_link::R
• slc::slc0tx_link::SDIO_SLC0_TXLINK_PARK_R
• slc::slc0tx_link::SDIO_SLC0_TXLINK_PARK_W
• slc::slc0tx_link::SDIO_SLC0_TXLINK_RESTART_R
• slc::slc0tx_link::SDIO_SLC0_TXLINK_RESTART_W
• slc::slc0tx_link::SDIO_SLC0_TXLINK_START_R
• slc::slc0tx_link::SDIO_SLC0_TXLINK_START_W
• slc::slc0tx_link::SDIO_SLC0_TXLINK_STOP_R
• slc::slc0tx_link::SDIO_SLC0_TXLINK_STOP_W
• slc::slc0tx_link::W
• slc::slc0tx_link_addr::R
• slc::slc0tx_link_addr::SDIO_SLC0_TXLINK_ADDR_R
• slc::slc0tx_link_addr::SDIO_SLC0_TXLINK_ADDR_W
• slc::slc0tx_link_addr::W
• slc::slc1_rx_sharemem_end::R
• slc::slc1_rx_sharemem_end::SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_R
• slc::slc1_rx_sharemem_end::SDIO_SDIO_SLC1_RX_SHAREMEM_END_ADDR_W
• slc::slc1_rx_sharemem_end::W
• slc::slc1_rx_sharemem_start::R
• slc::slc1_rx_sharemem_start::SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_R
• slc::slc1_rx_sharemem_start::SDIO_SDIO_SLC1_RX_SHAREMEM_START_ADDR_W
• slc::slc1_rx_sharemem_start::W
• slc::slc1_tx_sharemem_end::R
• slc::slc1_tx_sharemem_end::SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_R
• slc::slc1_tx_sharemem_end::SDIO_SDIO_SLC1_TX_SHAREMEM_END_ADDR_W
• slc::slc1_tx_sharemem_end::W
• slc::slc1_tx_sharemem_start::R
• slc::slc1_tx_sharemem_start::SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_R
• slc::slc1_tx_sharemem_start::SDIO_SDIO_SLC0_RX_SHAREMEM_START_ADDR_W
• slc::slc1_tx_sharemem_start::W
• slc::slc1int_clr::SDIO_SLC1_RX_CLRART_INT_CLR_W
• slc::slc1int_clr::SDIO_SLC1_RX_DONE_INT_CLR_W
• slc::slc1int_clr::SDIO_SLC1_RX_DSCR_ERR_INT_CLR_W
• slc::slc1int_clr::SDIO_SLC1_RX_EOF_INT_CLR_W
• slc::slc1int_clr::SDIO_SLC1_RX_UDF_INT_CLR_W
• slc::slc1int_clr::SDIO_SLC1_TX_CLRART_INT_CLR_W
• slc::slc1int_clr::SDIO_SLC1_TX_DONE_INT_CLR_W
• slc::slc1int_clr::SDIO_SLC1_TX_DSCR_ERR_INT_CLR_W
• slc::slc1int_clr::SDIO_SLC1_TX_OVF_INT_CLR_W
• slc::slc1int_clr::SDIO_SLC1_TX_SUC_EOF_INT_CLR_W
• slc::slc1int_clr::SDIO_SLC_FRHOST_BIT_INT_CLR_W
• slc::slc1int_clr::W
• slc::slc1int_ena1::R
• slc::slc1int_ena1::SDIO_SLC1_RX_DONE_INT_ENA1_R
• slc::slc1int_ena1::SDIO_SLC1_RX_DONE_INT_ENA1_W
• slc::slc1int_ena1::SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_R
• slc::slc1int_ena1::SDIO_SLC1_RX_DSCR_ERR_INT_ENA1_W
• slc::slc1int_ena1::SDIO_SLC1_RX_ENAART_INT_ENA1_R
• slc::slc1int_ena1::SDIO_SLC1_RX_ENAART_INT_ENA1_W
• slc::slc1int_ena1::SDIO_SLC1_RX_EOF_INT_ENA1_R
• slc::slc1int_ena1::SDIO_SLC1_RX_EOF_INT_ENA1_W
• slc::slc1int_ena1::SDIO_SLC1_RX_UDF_INT_ENA1_R
• slc::slc1int_ena1::SDIO_SLC1_RX_UDF_INT_ENA1_W
• slc::slc1int_ena1::SDIO_SLC1_TX_DONE_INT_ENA1_R
• slc::slc1int_ena1::SDIO_SLC1_TX_DONE_INT_ENA1_W
• slc::slc1int_ena1::SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_R
• slc::slc1int_ena1::SDIO_SLC1_TX_DSCR_ERR_INT_ENA1_W
• slc::slc1int_ena1::SDIO_SLC1_TX_ENAART_INT_ENA1_R
• slc::slc1int_ena1::SDIO_SLC1_TX_ENAART_INT_ENA1_W
• slc::slc1int_ena1::SDIO_SLC1_TX_OVF_INT_ENA1_R
• slc::slc1int_ena1::SDIO_SLC1_TX_OVF_INT_ENA1_W
• slc::slc1int_ena1::SDIO_SLC1_TX_SUC_EOF_INT_ENA1_R
• slc::slc1int_ena1::SDIO_SLC1_TX_SUC_EOF_INT_ENA1_W
• slc::slc1int_ena1::SDIO_SLC_FRHOST_BIT_INT_ENA1_R
• slc::slc1int_ena1::SDIO_SLC_FRHOST_BIT_INT_ENA1_W
• slc::slc1int_ena1::W
• slc::slc1int_raw::R
• slc::slc1int_raw::SDIO_SLC1_RX_DONE_INT_RAW_R
• slc::slc1int_raw::SDIO_SLC1_RX_DONE_INT_RAW_W
• slc::slc1int_raw::SDIO_SLC1_RX_DSCR_ERR_INT_RAW_R
• slc::slc1int_raw::SDIO_SLC1_RX_DSCR_ERR_INT_RAW_W
• slc::slc1int_raw::SDIO_SLC1_RX_EOF_INT_RAW_R
• slc::slc1int_raw::SDIO_SLC1_RX_EOF_INT_RAW_W
• slc::slc1int_raw::SDIO_SLC1_RX_START_INT_RAW_R
• slc::slc1int_raw::SDIO_SLC1_RX_START_INT_RAW_W
• slc::slc1int_raw::SDIO_SLC1_RX_UDF_INT_RAW_R
• slc::slc1int_raw::SDIO_SLC1_RX_UDF_INT_RAW_W
• slc::slc1int_raw::SDIO_SLC1_TX_DONE_INT_RAW_R
• slc::slc1int_raw::SDIO_SLC1_TX_DONE_INT_RAW_W
• slc::slc1int_raw::SDIO_SLC1_TX_DSCR_ERR_INT_RAW_R
• slc::slc1int_raw::SDIO_SLC1_TX_DSCR_ERR_INT_RAW_W
• slc::slc1int_raw::SDIO_SLC1_TX_OVF_INT_RAW_R
• slc::slc1int_raw::SDIO_SLC1_TX_OVF_INT_RAW_W
• slc::slc1int_raw::SDIO_SLC1_TX_START_INT_RAW_R
• slc::slc1int_raw::SDIO_SLC1_TX_START_INT_RAW_W
• slc::slc1int_raw::SDIO_SLC1_TX_SUC_EOF_INT_RAW_R
• slc::slc1int_raw::SDIO_SLC1_TX_SUC_EOF_INT_RAW_W
• slc::slc1int_raw::SDIO_SLC_FRHOST_BIT_INT_RAW_R
• slc::slc1int_raw::SDIO_SLC_FRHOST_BIT_INT_RAW_W
• slc::slc1int_raw::W
• slc::slc1int_st1::R
• slc::slc1int_st1::SDIO_SLC1_RX_DONE_INT_ST1_R
• slc::slc1int_st1::SDIO_SLC1_RX_DSCR_ERR_INT_ST1_R
• slc::slc1int_st1::SDIO_SLC1_RX_EOF_INT_ST1_R
• slc::slc1int_st1::SDIO_SLC1_RX_START_INT_ST1_R
• slc::slc1int_st1::SDIO_SLC1_RX_UDF_INT_ST1_R
• slc::slc1int_st1::SDIO_SLC1_TX_DONE_INT_ST1_R
• slc::slc1int_st1::SDIO_SLC1_TX_DSCR_ERR_INT_ST1_R
• slc::slc1int_st1::SDIO_SLC1_TX_OVF_INT_ST1_R
• slc::slc1int_st1::SDIO_SLC1_TX_START_INT_ST1_R
• slc::slc1int_st1::SDIO_SLC1_TX_SUC_EOF_INT_ST1_R
• slc::slc1int_st1::SDIO_SLC_FRHOST_BIT_INT_ST1_R
• slc::slc1rx_link::R
• slc::slc1rx_link::SDIO_SLC1_RXLINK_PARK_R
• slc::slc1rx_link::SDIO_SLC1_RXLINK_PARK_W
• slc::slc1rx_link::SDIO_SLC1_RXLINK_RESTART_R
• slc::slc1rx_link::SDIO_SLC1_RXLINK_RESTART_W
• slc::slc1rx_link::SDIO_SLC1_RXLINK_START_R
• slc::slc1rx_link::SDIO_SLC1_RXLINK_START_W
• slc::slc1rx_link::SDIO_SLC1_RXLINK_STOP_R
• slc::slc1rx_link::SDIO_SLC1_RXLINK_STOP_W
• slc::slc1rx_link::W
• slc::slc1rx_link_addr::R
• slc::slc1rx_link_addr::SDIO_SLC1_RXLINK_ADDR_R
• slc::slc1rx_link_addr::SDIO_SLC1_RXLINK_ADDR_W
• slc::slc1rx_link_addr::W
• slc::slc1token1::R
• slc::slc1token1::SDIO_SLC0_TOKEN1_INC_MORE_W
• slc::slc1token1::SDIO_SLC0_TOKEN1_INC_W
• slc::slc1token1::SDIO_SLC0_TOKEN1_R
• slc::slc1token1::SDIO_SLC0_TOKEN1_WR_W
• slc::slc1token1::SDIO_SLC1_TOKEN1_WDATA_W
• slc::slc1token1::W
• slc::slc1tx_link::R
• slc::slc1tx_link::SDIO_SLC1_TXLINK_PARK_R
• slc::slc1tx_link::SDIO_SLC1_TXLINK_PARK_W
• slc::slc1tx_link::SDIO_SLC1_TXLINK_RESTART_R
• slc::slc1tx_link::SDIO_SLC1_TXLINK_RESTART_W
• slc::slc1tx_link::SDIO_SLC1_TXLINK_START_R
• slc::slc1tx_link::SDIO_SLC1_TXLINK_START_W
• slc::slc1tx_link::SDIO_SLC1_TXLINK_STOP_R
• slc::slc1tx_link::SDIO_SLC1_TXLINK_STOP_W
• slc::slc1tx_link::W
• slc::slc1tx_link_addr::R
• slc::slc1tx_link_addr::SDIO_SLC1_TXLINK_ADDR_R
• slc::slc1tx_link_addr::SDIO_SLC1_TXLINK_ADDR_W
• slc::slc1tx_link_addr::W
• slc::slc_burst_len::R
• slc::slc_burst_len::SDIO_SLC0_RXDATA_BURST_LEN_R
• slc::slc_burst_len::SDIO_SLC0_RXDATA_BURST_LEN_W
• slc::slc_burst_len::SDIO_SLC0_TXDATA_BURST_LEN_R
• slc::slc_burst_len::SDIO_SLC0_TXDATA_BURST_LEN_W
• slc::slc_burst_len::SDIO_SLC1_RXDATA_BURST_LEN_R
• slc::slc_burst_len::SDIO_SLC1_RXDATA_BURST_LEN_W
• slc::slc_burst_len::SDIO_SLC1_TXDATA_BURST_LEN_R
• slc::slc_burst_len::SDIO_SLC1_TXDATA_BURST_LEN_W
• slc::slc_burst_len::W
• slc::slc_rx_dscr_conf::R
• slc::slc_rx_dscr_conf::SDIO_SLC0_TOKEN_NO_REPLACE_R
• slc::slc_rx_dscr_conf::SDIO_SLC0_TOKEN_NO_REPLACE_W
• slc::slc_rx_dscr_conf::W
• slc::slcconf0::R
• slc::slcconf0::SDIO_SLC0_RXDATA_BURST_EN_R
• slc::slcconf0::SDIO_SLC0_RXDATA_BURST_EN_W
• slc::slcconf0::SDIO_SLC0_RXDSCR_BURST_EN_R
• slc::slcconf0::SDIO_SLC0_RXDSCR_BURST_EN_W
• slc::slcconf0::SDIO_SLC0_RX_AUTO_WRBACK_R
• slc::slcconf0::SDIO_SLC0_RX_AUTO_WRBACK_W
• slc::slcconf0::SDIO_SLC0_RX_LOOP_TEST_R
• slc::slcconf0::SDIO_SLC0_RX_LOOP_TEST_W
• slc::slcconf0::SDIO_SLC0_RX_NO_RESTART_CLR_R
• slc::slcconf0::SDIO_SLC0_RX_NO_RESTART_CLR_W
• slc::slcconf0::SDIO_SLC0_RX_RST_R
• slc::slcconf0::SDIO_SLC0_RX_RST_W
• slc::slcconf0::SDIO_SLC0_TOKEN_AUTO_CLR_R
• slc::slcconf0::SDIO_SLC0_TOKEN_AUTO_CLR_W
• slc::slcconf0::SDIO_SLC0_TXDATA_BURST_EN_R
• slc::slcconf0::SDIO_SLC0_TXDATA_BURST_EN_W
• slc::slcconf0::SDIO_SLC0_TXDSCR_BURST_EN_R
• slc::slcconf0::SDIO_SLC0_TXDSCR_BURST_EN_W
• slc::slcconf0::SDIO_SLC0_TX_LOOP_TEST_R
• slc::slcconf0::SDIO_SLC0_TX_LOOP_TEST_W
• slc::slcconf0::SDIO_SLC0_TX_RST_R
• slc::slcconf0::SDIO_SLC0_TX_RST_W
• slc::slcconf0::SDIO_SLC1_RXDATA_BURST_EN_R
• slc::slcconf0::SDIO_SLC1_RXDATA_BURST_EN_W
• slc::slcconf0::SDIO_SLC1_RXDSCR_BURST_EN_R
• slc::slcconf0::SDIO_SLC1_RXDSCR_BURST_EN_W
• slc::slcconf0::SDIO_SLC1_RX_AUTO_WRBACK_R
• slc::slcconf0::SDIO_SLC1_RX_AUTO_WRBACK_W
• slc::slcconf0::SDIO_SLC1_RX_LOOP_TEST_R
• slc::slcconf0::SDIO_SLC1_RX_LOOP_TEST_W
• slc::slcconf0::SDIO_SLC1_RX_NO_RESTART_CLR_R
• slc::slcconf0::SDIO_SLC1_RX_NO_RESTART_CLR_W
• slc::slcconf0::SDIO_SLC1_RX_RST_R
• slc::slcconf0::SDIO_SLC1_RX_RST_W
• slc::slcconf0::SDIO_SLC1_TOKEN_AUTO_CLR_R
• slc::slcconf0::SDIO_SLC1_TOKEN_AUTO_CLR_W
• slc::slcconf0::SDIO_SLC1_TXDATA_BURST_EN_R
• slc::slcconf0::SDIO_SLC1_TXDATA_BURST_EN_W
• slc::slcconf0::SDIO_SLC1_TXDSCR_BURST_EN_R
• slc::slcconf0::SDIO_SLC1_TXDSCR_BURST_EN_W
• slc::slcconf0::SDIO_SLC1_TX_LOOP_TEST_R
• slc::slcconf0::SDIO_SLC1_TX_LOOP_TEST_W
• slc::slcconf0::SDIO_SLC1_TX_RST_R
• slc::slcconf0::SDIO_SLC1_TX_RST_W
• slc::slcconf0::W
• slc::slcconf1::R
• slc::slcconf1::SDIO_HOST_INT_LEVEL_SEL_R
• slc::slcconf1::SDIO_HOST_INT_LEVEL_SEL_W
• slc::slcconf1::SDIO_SDIO_CMD_HOLD_EN_R
• slc::slcconf1::SDIO_SDIO_CMD_HOLD_EN_W
• slc::slcconf1::SDIO_SLC0_LEN_AUTO_CLR_R
• slc::slcconf1::SDIO_SLC0_LEN_AUTO_CLR_W
• slc::slcconf1::SDIO_SLC0_RX_STITCH_EN_R
• slc::slcconf1::SDIO_SLC0_RX_STITCH_EN_W
• slc::slcconf1::SDIO_SLC0_TX_STITCH_EN_R
• slc::slcconf1::SDIO_SLC0_TX_STITCH_EN_W
• slc::slcconf1::SDIO_SLC1_RX_STITCH_EN_R
• slc::slcconf1::SDIO_SLC1_RX_STITCH_EN_W
• slc::slcconf1::SDIO_SLC1_TX_STITCH_EN_R
• slc::slcconf1::SDIO_SLC1_TX_STITCH_EN_W
• slc::slcconf1::W
• slc::slcintvec_tohost::SDIO_SLC0_TOHOST_INTVEC_W
• slc::slcintvec_tohost::SDIO_SLC1_TOHOST_INTVEC_W
• slc::slcintvec_tohost::W
• slchost::CHECK_SUM0
• slchost::CHECK_SUM1
• slchost::CONF
• slchost::CONF_W0
• slchost::CONF_W1
• slchost::CONF_W10
• slchost::CONF_W11
• slchost::CONF_W12
• slchost::CONF_W13
• slchost::CONF_W14
• slchost::CONF_W15
• slchost::CONF_W2
• slchost::CONF_W3
• slchost::CONF_W4
• slchost::CONF_W5
• slchost::CONF_W6
• slchost::CONF_W7
• slchost::CONF_W8
• slchost::CONF_W9
• slchost::FUNC2_0
• slchost::FUNC2_1
• slchost::FUNC2_2
• slchost::GPIO_IN0
• slchost::GPIO_IN1
• slchost::GPIO_STATUS0
• slchost::GPIO_STATUS1
• slchost::INF_ST
• slchost::PKT_LEN
• slchost::PKT_LEN0
• slchost::PKT_LEN1
• slchost::PKT_LEN2
• slchost::RDCLR0
• slchost::RDCLR1
• slchost::SLC0HOST_FUNC1_INT_ENA
• slchost::SLC0HOST_FUNC2_INT_ENA
• slchost::SLC0HOST_INT_CLR
• slchost::SLC0HOST_INT_ENA
• slchost::SLC0HOST_INT_ENA1
• slchost::SLC0HOST_INT_RAW
• slchost::SLC0HOST_INT_ST
• slchost::SLC0HOST_LEN_WD
• slchost::SLC0HOST_RX_INFOR
• slchost::SLC0HOST_TOKEN_RDATA
• slchost::SLC0HOST_TOKEN_WDATA
• slchost::SLC0_HOST_PF
• slchost::SLC1HOST_FUNC1_INT_ENA
• slchost::SLC1HOST_FUNC2_INT_ENA
• slchost::SLC1HOST_INT_CLR
• slchost::SLC1HOST_INT_ENA
• slchost::SLC1HOST_INT_ENA1
• slchost::SLC1HOST_INT_RAW
• slchost::SLC1HOST_INT_ST
• slchost::SLC1HOST_RX_INFOR
• slchost::SLC1HOST_TOKEN_RDATA
• slchost::SLC1HOST_TOKEN_WDATA
• slchost::SLC1_HOST_PF
• slchost::SLCHOSTDATE
• slchost::SLCHOSTID
• slchost::SLC_APBWIN_CONF
• slchost::SLC_APBWIN_RDATA
• slchost::SLC_APBWIN_WDATA
• slchost::STATE_W0
• slchost::STATE_W1
• slchost::TOKEN_CON
• slchost::WIN_CMD
• slchost::check_sum0::R
• slchost::check_sum0::SLCHOST_CHECK_SUM0_R
• slchost::check_sum1::R
• slchost::check_sum1::SLCHOST_CHECK_SUM1_R
• slchost::conf::FRC_NEG_SAMP_R
• slchost::conf::FRC_NEG_SAMP_W
• slchost::conf::FRC_POS_SAMP_R
• slchost::conf::FRC_POS_SAMP_W
• slchost::conf::FRC_QUICK_IN_R
• slchost::conf::FRC_QUICK_IN_W
• slchost::conf::FRC_SDIO11_R
• slchost::conf::FRC_SDIO11_W
• slchost::conf::FRC_SDIO20_R
• slchost::conf::FRC_SDIO20_W
• slchost::conf::HSPEED_CON_EN_R
• slchost::conf::HSPEED_CON_EN_W
• slchost::conf::R
• slchost::conf::SDIO20_INT_DELAY_R
• slchost::conf::SDIO20_INT_DELAY_W
• slchost::conf::SDIO_PAD_PULLUP_R
• slchost::conf::SDIO_PAD_PULLUP_W
• slchost::conf::W
• slchost::conf_w0::R
• slchost::conf_w0::SLCHOST_CONF0_R
• slchost::conf_w0::SLCHOST_CONF0_W
• slchost::conf_w0::SLCHOST_CONF1_R
• slchost::conf_w0::SLCHOST_CONF1_W
• slchost::conf_w0::SLCHOST_CONF2_R
• slchost::conf_w0::SLCHOST_CONF2_W
• slchost::conf_w0::SLCHOST_CONF3_R
• slchost::conf_w0::SLCHOST_CONF3_W
• slchost::conf_w0::W
• slchost::conf_w10::R
• slchost::conf_w10::SLCHOST_CONF40_R
• slchost::conf_w10::SLCHOST_CONF40_W
• slchost::conf_w10::SLCHOST_CONF41_R
• slchost::conf_w10::SLCHOST_CONF41_W
• slchost::conf_w10::SLCHOST_CONF42_R
• slchost::conf_w10::SLCHOST_CONF42_W
• slchost::conf_w10::SLCHOST_CONF43_R
• slchost::conf_w10::SLCHOST_CONF43_W
• slchost::conf_w10::W
• slchost::conf_w11::R
• slchost::conf_w11::SLCHOST_CONF44_R
• slchost::conf_w11::SLCHOST_CONF44_W
• slchost::conf_w11::SLCHOST_CONF45_R
• slchost::conf_w11::SLCHOST_CONF45_W
• slchost::conf_w11::SLCHOST_CONF46_R
• slchost::conf_w11::SLCHOST_CONF46_W
• slchost::conf_w11::SLCHOST_CONF47_R
• slchost::conf_w11::SLCHOST_CONF47_W
• slchost::conf_w11::W
• slchost::conf_w12::R
• slchost::conf_w12::SLCHOST_CONF48_R
• slchost::conf_w12::SLCHOST_CONF48_W
• slchost::conf_w12::SLCHOST_CONF49_R
• slchost::conf_w12::SLCHOST_CONF49_W
• slchost::conf_w12::SLCHOST_CONF50_R
• slchost::conf_w12::SLCHOST_CONF50_W
• slchost::conf_w12::SLCHOST_CONF51_R
• slchost::conf_w12::SLCHOST_CONF51_W
• slchost::conf_w12::W
• slchost::conf_w13::R
• slchost::conf_w13::SLCHOST_CONF52_R
• slchost::conf_w13::SLCHOST_CONF52_W
• slchost::conf_w13::SLCHOST_CONF53_R
• slchost::conf_w13::SLCHOST_CONF53_W
• slchost::conf_w13::SLCHOST_CONF54_R
• slchost::conf_w13::SLCHOST_CONF54_W
• slchost::conf_w13::SLCHOST_CONF55_R
• slchost::conf_w13::SLCHOST_CONF55_W
• slchost::conf_w13::W
• slchost::conf_w14::R
• slchost::conf_w14::SLCHOST_CONF56_R
• slchost::conf_w14::SLCHOST_CONF56_W
• slchost::conf_w14::SLCHOST_CONF57_R
• slchost::conf_w14::SLCHOST_CONF57_W
• slchost::conf_w14::SLCHOST_CONF58_R
• slchost::conf_w14::SLCHOST_CONF58_W
• slchost::conf_w14::SLCHOST_CONF59_R
• slchost::conf_w14::SLCHOST_CONF59_W
• slchost::conf_w14::W
• slchost::conf_w15::R
• slchost::conf_w15::SLCHOST_CONF60_R
• slchost::conf_w15::SLCHOST_CONF60_W
• slchost::conf_w15::SLCHOST_CONF61_R
• slchost::conf_w15::SLCHOST_CONF61_W
• slchost::conf_w15::SLCHOST_CONF62_R
• slchost::conf_w15::SLCHOST_CONF62_W
• slchost::conf_w15::SLCHOST_CONF63_R
• slchost::conf_w15::SLCHOST_CONF63_W
• slchost::conf_w15::W
• slchost::conf_w1::R
• slchost::conf_w1::SLCHOST_CONF4_R
• slchost::conf_w1::SLCHOST_CONF4_W
• slchost::conf_w1::SLCHOST_CONF5_R
• slchost::conf_w1::SLCHOST_CONF5_W
• slchost::conf_w1::SLCHOST_CONF6_R
• slchost::conf_w1::SLCHOST_CONF6_W
• slchost::conf_w1::SLCHOST_CONF7_R
• slchost::conf_w1::SLCHOST_CONF7_W
• slchost::conf_w1::W
• slchost::conf_w2::R
• slchost::conf_w2::SLCHOST_CONF10_R
• slchost::conf_w2::SLCHOST_CONF10_W
• slchost::conf_w2::SLCHOST_CONF11_R
• slchost::conf_w2::SLCHOST_CONF11_W
• slchost::conf_w2::SLCHOST_CONF8_R
• slchost::conf_w2::SLCHOST_CONF8_W
• slchost::conf_w2::SLCHOST_CONF9_R
• slchost::conf_w2::SLCHOST_CONF9_W
• slchost::conf_w2::W
• slchost::conf_w3::R
• slchost::conf_w3::SLCHOST_CONF12_R
• slchost::conf_w3::SLCHOST_CONF12_W
• slchost::conf_w3::SLCHOST_CONF13_R
• slchost::conf_w3::SLCHOST_CONF13_W
• slchost::conf_w3::SLCHOST_CONF14_R
• slchost::conf_w3::SLCHOST_CONF14_W
• slchost::conf_w3::SLCHOST_CONF15_R
• slchost::conf_w3::SLCHOST_CONF15_W
• slchost::conf_w3::W
• slchost::conf_w4::R
• slchost::conf_w4::SLCHOST_CONF16_R
• slchost::conf_w4::SLCHOST_CONF16_W
• slchost::conf_w4::SLCHOST_CONF17_R
• slchost::conf_w4::SLCHOST_CONF17_W
• slchost::conf_w4::SLCHOST_CONF18_R
• slchost::conf_w4::SLCHOST_CONF18_W
• slchost::conf_w4::SLCHOST_CONF19_R
• slchost::conf_w4::SLCHOST_CONF19_W
• slchost::conf_w4::W
• slchost::conf_w5::R
• slchost::conf_w5::SLCHOST_CONF20_R
• slchost::conf_w5::SLCHOST_CONF20_W
• slchost::conf_w5::SLCHOST_CONF21_R
• slchost::conf_w5::SLCHOST_CONF21_W
• slchost::conf_w5::SLCHOST_CONF22_R
• slchost::conf_w5::SLCHOST_CONF22_W
• slchost::conf_w5::SLCHOST_CONF23_R
• slchost::conf_w5::SLCHOST_CONF23_W
• slchost::conf_w5::W
• slchost::conf_w6::R
• slchost::conf_w6::SLCHOST_CONF24_R
• slchost::conf_w6::SLCHOST_CONF24_W
• slchost::conf_w6::SLCHOST_CONF25_R
• slchost::conf_w6::SLCHOST_CONF25_W
• slchost::conf_w6::SLCHOST_CONF26_R
• slchost::conf_w6::SLCHOST_CONF26_W
• slchost::conf_w6::SLCHOST_CONF27_R
• slchost::conf_w6::SLCHOST_CONF27_W
• slchost::conf_w6::W
• slchost::conf_w7::R
• slchost::conf_w7::SLCHOST_CONF28_R
• slchost::conf_w7::SLCHOST_CONF28_W
• slchost::conf_w7::SLCHOST_CONF29_R
• slchost::conf_w7::SLCHOST_CONF29_W
• slchost::conf_w7::SLCHOST_CONF30_R
• slchost::conf_w7::SLCHOST_CONF30_W
• slchost::conf_w7::SLCHOST_CONF31_R
• slchost::conf_w7::SLCHOST_CONF31_W
• slchost::conf_w7::W
• slchost::conf_w8::R
• slchost::conf_w8::SLCHOST_CONF32_R
• slchost::conf_w8::SLCHOST_CONF32_W
• slchost::conf_w8::SLCHOST_CONF33_R
• slchost::conf_w8::SLCHOST_CONF33_W
• slchost::conf_w8::SLCHOST_CONF34_R
• slchost::conf_w8::SLCHOST_CONF34_W
• slchost::conf_w8::SLCHOST_CONF35_R
• slchost::conf_w8::SLCHOST_CONF35_W
• slchost::conf_w8::W
• slchost::conf_w9::R
• slchost::conf_w9::SLCHOST_CONF36_R
• slchost::conf_w9::SLCHOST_CONF36_W
• slchost::conf_w9::SLCHOST_CONF37_R
• slchost::conf_w9::SLCHOST_CONF37_W
• slchost::conf_w9::SLCHOST_CONF38_R
• slchost::conf_w9::SLCHOST_CONF38_W
• slchost::conf_w9::SLCHOST_CONF39_R
• slchost::conf_w9::SLCHOST_CONF39_W
• slchost::conf_w9::W
• slchost::func2_0::R
• slchost::func2_0::SLC_FUNC2_INT_R
• slchost::func2_0::SLC_FUNC2_INT_W
• slchost::func2_0::W
• slchost::func2_1::R
• slchost::func2_1::SLC_FUNC2_INT_EN_R
• slchost::func2_1::SLC_FUNC2_INT_EN_W
• slchost::func2_1::W
• slchost::func2_2::R
• slchost::func2_2::SLC_FUNC1_MDSTAT_R
• slchost::func2_2::SLC_FUNC1_MDSTAT_W
• slchost::func2_2::W
• slchost::gpio_in0::GPIO_SDIO_IN0_R
• slchost::gpio_in0::R
• slchost::gpio_in1::GPIO_SDIO_IN1_R
• slchost::gpio_in1::R
• slchost::gpio_status0::GPIO_SDIO_INT0_R
• slchost::gpio_status0::R
• slchost::gpio_status1::GPIO_SDIO_INT1_R
• slchost::gpio_status1::R
• slchost::inf_st::CLK_MODE_R
• slchost::inf_st::CLK_MODE_SW_R
• slchost::inf_st::CLK_MODE_SW_W
• slchost::inf_st::CLK_MODE_W
• slchost::inf_st::DLL_ON_R
• slchost::inf_st::DLL_ON_SW_R
• slchost::inf_st::DLL_ON_SW_W
• slchost::inf_st::DLL_ON_W
• slchost::inf_st::R
• slchost::inf_st::SDIO20_MODE_R
• slchost::inf_st::SDIO_NEG_SAMP_R
• slchost::inf_st::SDIO_QUICK_IN_R
• slchost::inf_st::W
• slchost::pkt_len0::HOSTSLCHOST_SLC0_LEN0_CHECK_R
• slchost::pkt_len0::HOSTSLCHOST_SLC0_LEN0_R
• slchost::pkt_len0::R
• slchost::pkt_len1::HOSTSLCHOST_SLC0_LEN1_CHECK_R
• slchost::pkt_len1::HOSTSLCHOST_SLC0_LEN1_R
• slchost::pkt_len1::R
• slchost::pkt_len2::HOSTSLCHOST_SLC0_LEN2_CHECK_R
• slchost::pkt_len2::HOSTSLCHOST_SLC0_LEN2_R
• slchost::pkt_len2::R
• slchost::pkt_len::HOSTSLCHOST_SLC0_LEN_CHECK_R
• slchost::pkt_len::HOSTSLCHOST_SLC0_LEN_R
• slchost::pkt_len::R
• slchost::rdclr0::R
• slchost::rdclr0::SLCHOST_SLC0_BIT6_CLRADDR_R
• slchost::rdclr0::SLCHOST_SLC0_BIT6_CLRADDR_W
• slchost::rdclr0::SLCHOST_SLC0_BIT7_CLRADDR_R
• slchost::rdclr0::SLCHOST_SLC0_BIT7_CLRADDR_W
• slchost::rdclr0::W
• slchost::rdclr1::R
• slchost::rdclr1::SLCHOST_SLC1_BIT6_CLRADDR_R
• slchost::rdclr1::SLCHOST_SLC1_BIT6_CLRADDR_W
• slchost::rdclr1::SLCHOST_SLC1_BIT7_CLRADDR_R
• slchost::rdclr1::SLCHOST_SLC1_BIT7_CLRADDR_W
• slchost::rdclr1::W
• slchost::slc0_host_pf::R
• slchost::slc0_host_pf::SLC0_PF_DATA_R
• slchost::slc0host_func1_int_ena::FN1_GPIO_SDIO_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_GPIO_SDIO_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0HOST_RX_EOF_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0HOST_RX_EOF_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0HOST_RX_SOF_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0HOST_RX_SOF_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0HOST_RX_START_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0HOST_RX_START_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0HOST_TX_START_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0HOST_TX_START_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_EXT_BIT0_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_EXT_BIT0_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_EXT_BIT1_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_EXT_BIT1_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_EXT_BIT2_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_EXT_BIT2_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_EXT_BIT3_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_EXT_BIT3_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_HOST_RD_RETRY_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_HOST_RD_RETRY_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_RX_NEW_PACKET_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_RX_NEW_PACKET_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_RX_PF_VALID_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_RX_PF_VALID_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_RX_UDF_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_RX_UDF_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT0_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT0_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT1_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT1_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT2_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT2_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT3_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT3_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT4_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT4_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT5_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT5_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT6_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT6_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT7_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOHOST_BIT7_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOKEN0_0TO1_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOKEN0_0TO1_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOKEN0_1TO0_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOKEN0_1TO0_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOKEN1_0TO1_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOKEN1_0TO1_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOKEN1_1TO0_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_TOKEN1_1TO0_INT_ENA_W
• slchost::slc0host_func1_int_ena::FN1_SLC0_TX_OVF_INT_ENA_R
• slchost::slc0host_func1_int_ena::FN1_SLC0_TX_OVF_INT_ENA_W
• slchost::slc0host_func1_int_ena::R
• slchost::slc0host_func1_int_ena::W
• slchost::slc0host_func2_int_ena::FN2_GPIO_SDIO_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_GPIO_SDIO_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0HOST_RX_EOF_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0HOST_RX_EOF_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0HOST_RX_SOF_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0HOST_RX_SOF_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0HOST_RX_START_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0HOST_RX_START_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0HOST_TX_START_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0HOST_TX_START_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_EXT_BIT0_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_EXT_BIT0_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_EXT_BIT1_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_EXT_BIT1_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_EXT_BIT2_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_EXT_BIT2_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_EXT_BIT3_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_EXT_BIT3_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_HOST_RD_RETRY_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_HOST_RD_RETRY_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_RX_NEW_PACKET_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_RX_NEW_PACKET_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_RX_PF_VALID_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_RX_PF_VALID_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_RX_UDF_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_RX_UDF_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT0_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT0_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT1_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT1_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT2_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT2_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT3_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT3_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT4_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT4_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT5_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT5_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT6_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT6_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT7_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOHOST_BIT7_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOKEN0_0TO1_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOKEN0_0TO1_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOKEN0_1TO0_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOKEN0_1TO0_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOKEN1_0TO1_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOKEN1_0TO1_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOKEN1_1TO0_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_TOKEN1_1TO0_INT_ENA_W
• slchost::slc0host_func2_int_ena::FN2_SLC0_TX_OVF_INT_ENA_R
• slchost::slc0host_func2_int_ena::FN2_SLC0_TX_OVF_INT_ENA_W
• slchost::slc0host_func2_int_ena::R
• slchost::slc0host_func2_int_ena::W
• slchost::slc0host_int_clr::GPIO_SDIO_INT_CLR_W
• slchost::slc0host_int_clr::SLC0HOST_RX_EOF_INT_CLR_W
• slchost::slc0host_int_clr::SLC0HOST_RX_SOF_INT_CLR_W
• slchost::slc0host_int_clr::SLC0HOST_RX_START_INT_CLR_W
• slchost::slc0host_int_clr::SLC0HOST_TX_START_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_EXT_BIT0_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_EXT_BIT1_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_EXT_BIT2_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_EXT_BIT3_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_HOST_RD_RETRY_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_RX_NEW_PACKET_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_RX_PF_VALID_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_RX_UDF_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_TOHOST_BIT0_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_TOHOST_BIT1_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_TOHOST_BIT2_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_TOHOST_BIT3_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_TOHOST_BIT4_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_TOHOST_BIT5_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_TOHOST_BIT6_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_TOHOST_BIT7_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_TOKEN0_0TO1_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_TOKEN0_1TO0_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_TOKEN1_0TO1_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_TOKEN1_1TO0_INT_CLR_W
• slchost::slc0host_int_clr::SLC0_TX_OVF_INT_CLR_W
• slchost::slc0host_int_clr::W
• slchost::slc0host_int_ena1::GPIO_SDIO_INT_ENA1_R
• slchost::slc0host_int_ena1::GPIO_SDIO_INT_ENA1_W
• slchost::slc0host_int_ena1::R
• slchost::slc0host_int_ena1::SLC0HOST_RX_EOF_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0HOST_RX_EOF_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0HOST_RX_SOF_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0HOST_RX_SOF_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0HOST_RX_START_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0HOST_RX_START_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0HOST_TX_START_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0HOST_TX_START_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_EXT_BIT0_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_EXT_BIT0_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_EXT_BIT1_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_EXT_BIT1_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_EXT_BIT2_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_EXT_BIT2_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_EXT_BIT3_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_EXT_BIT3_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_HOST_RD_RETRY_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_HOST_RD_RETRY_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_RX_NEW_PACKET_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_RX_NEW_PACKET_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_RX_PF_VALID_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_RX_PF_VALID_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_RX_UDF_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_RX_UDF_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT0_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT0_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT1_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT1_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT2_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT2_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT3_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT3_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT4_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT4_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT5_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT5_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT6_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT6_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT7_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_TOHOST_BIT7_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_TOKEN0_0TO1_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_TOKEN0_0TO1_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_TOKEN0_1TO0_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_TOKEN0_1TO0_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_TOKEN1_0TO1_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_TOKEN1_0TO1_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_TOKEN1_1TO0_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_TOKEN1_1TO0_INT_ENA1_W
• slchost::slc0host_int_ena1::SLC0_TX_OVF_INT_ENA1_R
• slchost::slc0host_int_ena1::SLC0_TX_OVF_INT_ENA1_W
• slchost::slc0host_int_ena1::W
• slchost::slc0host_int_ena::GPIO_SDIO_INT_ENA_R
• slchost::slc0host_int_ena::GPIO_SDIO_INT_ENA_W
• slchost::slc0host_int_ena::R
• slchost::slc0host_int_ena::SLC0HOST_RX_EOF_INT_ENA_R
• slchost::slc0host_int_ena::SLC0HOST_RX_EOF_INT_ENA_W
• slchost::slc0host_int_ena::SLC0HOST_RX_SOF_INT_ENA_R
• slchost::slc0host_int_ena::SLC0HOST_RX_SOF_INT_ENA_W
• slchost::slc0host_int_ena::SLC0HOST_RX_START_INT_ENA_R
• slchost::slc0host_int_ena::SLC0HOST_RX_START_INT_ENA_W
• slchost::slc0host_int_ena::SLC0HOST_TX_START_INT_ENA_R
• slchost::slc0host_int_ena::SLC0HOST_TX_START_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_EXT_BIT0_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_EXT_BIT0_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_EXT_BIT1_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_EXT_BIT1_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_EXT_BIT2_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_EXT_BIT2_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_EXT_BIT3_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_EXT_BIT3_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_HOST_RD_RETRY_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_HOST_RD_RETRY_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_RX_NEW_PACKET_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_RX_NEW_PACKET_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_RX_PF_VALID_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_RX_PF_VALID_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_RX_UDF_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_RX_UDF_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT0_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT0_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT1_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT1_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT2_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT2_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT3_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT3_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT4_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT4_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT5_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT5_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT6_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT6_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT7_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_TOHOST_BIT7_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_TOKEN0_0TO1_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_TOKEN0_0TO1_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_TOKEN0_1TO0_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_TOKEN0_1TO0_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_TOKEN1_0TO1_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_TOKEN1_0TO1_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_TOKEN1_1TO0_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_TOKEN1_1TO0_INT_ENA_W
• slchost::slc0host_int_ena::SLC0_TX_OVF_INT_ENA_R
• slchost::slc0host_int_ena::SLC0_TX_OVF_INT_ENA_W
• slchost::slc0host_int_ena::W
• slchost::slc0host_int_raw::GPIO_SDIO_INT_RAW_R
• slchost::slc0host_int_raw::GPIO_SDIO_INT_RAW_W
• slchost::slc0host_int_raw::R
• slchost::slc0host_int_raw::SLC0HOST_RX_EOF_INT_RAW_R
• slchost::slc0host_int_raw::SLC0HOST_RX_EOF_INT_RAW_W
• slchost::slc0host_int_raw::SLC0HOST_RX_SOF_INT_RAW_R
• slchost::slc0host_int_raw::SLC0HOST_RX_SOF_INT_RAW_W
• slchost::slc0host_int_raw::SLC0HOST_RX_START_INT_RAW_R
• slchost::slc0host_int_raw::SLC0HOST_RX_START_INT_RAW_W
• slchost::slc0host_int_raw::SLC0HOST_TX_START_INT_RAW_R
• slchost::slc0host_int_raw::SLC0HOST_TX_START_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_EXT_BIT0_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_EXT_BIT0_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_EXT_BIT1_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_EXT_BIT1_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_EXT_BIT2_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_EXT_BIT2_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_EXT_BIT3_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_EXT_BIT3_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_HOST_RD_RETRY_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_HOST_RD_RETRY_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_RX_NEW_PACKET_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_RX_NEW_PACKET_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_RX_PF_VALID_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_RX_PF_VALID_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_RX_UDF_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_RX_UDF_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT0_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT0_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT1_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT1_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT2_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT2_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT3_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT3_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT4_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT4_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT5_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT5_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT6_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT6_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT7_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_TOHOST_BIT7_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_TOKEN0_0TO1_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_TOKEN0_0TO1_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_TOKEN0_1TO0_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_TOKEN0_1TO0_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_TOKEN1_0TO1_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_TOKEN1_0TO1_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_TOKEN1_1TO0_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_TOKEN1_1TO0_INT_RAW_W
• slchost::slc0host_int_raw::SLC0_TX_OVF_INT_RAW_R
• slchost::slc0host_int_raw::SLC0_TX_OVF_INT_RAW_W
• slchost::slc0host_int_raw::W
• slchost::slc0host_int_st::GPIO_SDIO_INT_ST_R
• slchost::slc0host_int_st::R
• slchost::slc0host_int_st::SLC0HOST_RX_EOF_INT_ST_R
• slchost::slc0host_int_st::SLC0HOST_RX_SOF_INT_ST_R
• slchost::slc0host_int_st::SLC0HOST_RX_START_INT_ST_R
• slchost::slc0host_int_st::SLC0HOST_TX_START_INT_ST_R
• slchost::slc0host_int_st::SLC0_EXT_BIT0_INT_ST_R
• slchost::slc0host_int_st::SLC0_EXT_BIT1_INT_ST_R
• slchost::slc0host_int_st::SLC0_EXT_BIT2_INT_ST_R
• slchost::slc0host_int_st::SLC0_EXT_BIT3_INT_ST_R
• slchost::slc0host_int_st::SLC0_HOST_RD_RETRY_INT_ST_R
• slchost::slc0host_int_st::SLC0_RX_NEW_PACKET_INT_ST_R
• slchost::slc0host_int_st::SLC0_RX_PF_VALID_INT_ST_R
• slchost::slc0host_int_st::SLC0_RX_UDF_INT_ST_R
• slchost::slc0host_int_st::SLC0_TOHOST_BIT0_INT_ST_R
• slchost::slc0host_int_st::SLC0_TOHOST_BIT1_INT_ST_R
• slchost::slc0host_int_st::SLC0_TOHOST_BIT2_INT_ST_R
• slchost::slc0host_int_st::SLC0_TOHOST_BIT3_INT_ST_R
• slchost::slc0host_int_st::SLC0_TOHOST_BIT4_INT_ST_R
• slchost::slc0host_int_st::SLC0_TOHOST_BIT5_INT_ST_R
• slchost::slc0host_int_st::SLC0_TOHOST_BIT6_INT_ST_R
• slchost::slc0host_int_st::SLC0_TOHOST_BIT7_INT_ST_R
• slchost::slc0host_int_st::SLC0_TOKEN0_0TO1_INT_ST_R
• slchost::slc0host_int_st::SLC0_TOKEN0_1TO0_INT_ST_R
• slchost::slc0host_int_st::SLC0_TOKEN1_0TO1_INT_ST_R
• slchost::slc0host_int_st::SLC0_TOKEN1_1TO0_INT_ST_R
• slchost::slc0host_int_st::SLC0_TX_OVF_INT_ST_R
• slchost::slc0host_len_wd::R
• slchost::slc0host_len_wd::SLC0HOST_LEN_WD_R
• slchost::slc0host_len_wd::SLC0HOST_LEN_WD_W
• slchost::slc0host_len_wd::W
• slchost::slc0host_rx_infor::R
• slchost::slc0host_rx_infor::SLC0HOST_RX_INFOR_R
• slchost::slc0host_rx_infor::SLC0HOST_RX_INFOR_W
• slchost::slc0host_rx_infor::W
• slchost::slc0host_token_rdata::HOSTSLCHOST_SLC0_TOKEN1_R
• slchost::slc0host_token_rdata::R
• slchost::slc0host_token_rdata::SLC0_RX_PF_EOF_R
• slchost::slc0host_token_rdata::SLC0_RX_PF_VALID_R
• slchost::slc0host_token_rdata::SLC0_TOKEN0_R
• slchost::slc0host_token_wdata::R
• slchost::slc0host_token_wdata::SLC0HOST_TOKEN0_WD_R
• slchost::slc0host_token_wdata::SLC0HOST_TOKEN0_WD_W
• slchost::slc0host_token_wdata::SLC0HOST_TOKEN1_WD_R
• slchost::slc0host_token_wdata::SLC0HOST_TOKEN1_WD_W
• slchost::slc0host_token_wdata::W
• slchost::slc1_host_pf::R
• slchost::slc1_host_pf::SLC1_PF_DATA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1HOST_RX_EOF_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1HOST_RX_EOF_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1HOST_RX_SOF_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1HOST_RX_SOF_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1HOST_RX_START_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1HOST_RX_START_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1HOST_TX_START_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1HOST_TX_START_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_BT_RX_NEW_PACKET_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_EXT_BIT0_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_EXT_BIT0_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_EXT_BIT1_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_EXT_BIT1_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_EXT_BIT2_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_EXT_BIT2_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_EXT_BIT3_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_EXT_BIT3_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_HOST_RD_RETRY_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_HOST_RD_RETRY_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_RX_PF_VALID_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_RX_PF_VALID_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_RX_UDF_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_RX_UDF_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT0_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT0_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT1_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT1_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT2_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT2_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT3_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT3_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT4_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT4_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT5_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT5_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT6_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT6_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT7_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOHOST_BIT7_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOKEN0_0TO1_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOKEN0_0TO1_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOKEN0_1TO0_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOKEN0_1TO0_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOKEN1_0TO1_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOKEN1_0TO1_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOKEN1_1TO0_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_TOKEN1_1TO0_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_TX_OVF_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_TX_OVF_INT_ENA_W
• slchost::slc1host_func1_int_ena::FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_R
• slchost::slc1host_func1_int_ena::FN1_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_W
• slchost::slc1host_func1_int_ena::R
• slchost::slc1host_func1_int_ena::W
• slchost::slc1host_func2_int_ena::FN2_SLC1HOST_RX_EOF_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1HOST_RX_EOF_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1HOST_RX_SOF_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1HOST_RX_SOF_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1HOST_RX_START_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1HOST_RX_START_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1HOST_TX_START_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1HOST_TX_START_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_BT_RX_NEW_PACKET_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_EXT_BIT0_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_EXT_BIT0_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_EXT_BIT1_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_EXT_BIT1_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_EXT_BIT2_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_EXT_BIT2_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_EXT_BIT3_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_EXT_BIT3_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_HOST_RD_RETRY_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_HOST_RD_RETRY_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_RX_PF_VALID_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_RX_PF_VALID_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_RX_UDF_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_RX_UDF_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT0_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT0_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT1_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT1_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT2_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT2_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT3_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT3_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT4_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT4_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT5_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT5_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT6_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT6_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT7_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOHOST_BIT7_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOKEN0_0TO1_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOKEN0_0TO1_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOKEN0_1TO0_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOKEN0_1TO0_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOKEN1_0TO1_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOKEN1_0TO1_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOKEN1_1TO0_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_TOKEN1_1TO0_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_TX_OVF_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_TX_OVF_INT_ENA_W
• slchost::slc1host_func2_int_ena::FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_R
• slchost::slc1host_func2_int_ena::FN2_SLC1_WIFI_RX_NEW_PACKET_INT_ENA_W
• slchost::slc1host_func2_int_ena::R
• slchost::slc1host_func2_int_ena::W
• slchost::slc1host_int_clr::SLC1HOST_RX_EOF_INT_CLR_W
• slchost::slc1host_int_clr::SLC1HOST_RX_SOF_INT_CLR_W
• slchost::slc1host_int_clr::SLC1HOST_RX_START_INT_CLR_W
• slchost::slc1host_int_clr::SLC1HOST_TX_START_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_BT_RX_NEW_PACKET_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_EXT_BIT0_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_EXT_BIT1_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_EXT_BIT2_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_EXT_BIT3_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_HOST_RD_RETRY_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_RX_PF_VALID_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_RX_UDF_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_TOHOST_BIT0_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_TOHOST_BIT1_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_TOHOST_BIT2_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_TOHOST_BIT3_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_TOHOST_BIT4_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_TOHOST_BIT5_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_TOHOST_BIT6_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_TOHOST_BIT7_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_TOKEN0_0TO1_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_TOKEN0_1TO0_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_TOKEN1_0TO1_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_TOKEN1_1TO0_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_TX_OVF_INT_CLR_W
• slchost::slc1host_int_clr::SLC1_WIFI_RX_NEW_PACKET_INT_CLR_W
• slchost::slc1host_int_clr::W
• slchost::slc1host_int_ena1::R
• slchost::slc1host_int_ena1::SLC1HOST_RX_EOF_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1HOST_RX_EOF_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1HOST_RX_SOF_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1HOST_RX_SOF_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1HOST_RX_START_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1HOST_RX_START_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1HOST_TX_START_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1HOST_TX_START_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_BT_RX_NEW_PACKET_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_BT_RX_NEW_PACKET_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_EXT_BIT0_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_EXT_BIT0_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_EXT_BIT1_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_EXT_BIT1_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_EXT_BIT2_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_EXT_BIT2_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_EXT_BIT3_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_EXT_BIT3_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_HOST_RD_RETRY_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_HOST_RD_RETRY_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_RX_PF_VALID_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_RX_PF_VALID_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_RX_UDF_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_RX_UDF_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT0_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT0_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT1_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT1_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT2_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT2_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT3_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT3_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT4_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT4_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT5_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT5_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT6_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT6_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT7_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_TOHOST_BIT7_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_TOKEN0_0TO1_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_TOKEN0_0TO1_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_TOKEN0_1TO0_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_TOKEN0_1TO0_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_TOKEN1_0TO1_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_TOKEN1_0TO1_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_TOKEN1_1TO0_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_TOKEN1_1TO0_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_TX_OVF_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_TX_OVF_INT_ENA1_W
• slchost::slc1host_int_ena1::SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_R
• slchost::slc1host_int_ena1::SLC1_WIFI_RX_NEW_PACKET_INT_ENA1_W
• slchost::slc1host_int_ena1::W
• slchost::slc1host_int_ena::R
• slchost::slc1host_int_ena::SLC1HOST_RX_EOF_INT_ENA_R
• slchost::slc1host_int_ena::SLC1HOST_RX_EOF_INT_ENA_W
• slchost::slc1host_int_ena::SLC1HOST_RX_SOF_INT_ENA_R
• slchost::slc1host_int_ena::SLC1HOST_RX_SOF_INT_ENA_W
• slchost::slc1host_int_ena::SLC1HOST_RX_START_INT_ENA_R
• slchost::slc1host_int_ena::SLC1HOST_RX_START_INT_ENA_W
• slchost::slc1host_int_ena::SLC1HOST_TX_START_INT_ENA_R
• slchost::slc1host_int_ena::SLC1HOST_TX_START_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_BT_RX_NEW_PACKET_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_BT_RX_NEW_PACKET_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_EXT_BIT0_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_EXT_BIT0_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_EXT_BIT1_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_EXT_BIT1_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_EXT_BIT2_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_EXT_BIT2_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_EXT_BIT3_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_EXT_BIT3_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_HOST_RD_RETRY_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_HOST_RD_RETRY_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_RX_PF_VALID_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_RX_PF_VALID_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_RX_UDF_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_RX_UDF_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT0_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT0_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT1_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT1_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT2_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT2_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT3_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT3_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT4_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT4_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT5_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT5_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT6_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT6_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT7_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_TOHOST_BIT7_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_TOKEN0_0TO1_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_TOKEN0_0TO1_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_TOKEN0_1TO0_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_TOKEN0_1TO0_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_TOKEN1_0TO1_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_TOKEN1_0TO1_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_TOKEN1_1TO0_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_TOKEN1_1TO0_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_TX_OVF_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_TX_OVF_INT_ENA_W
• slchost::slc1host_int_ena::SLC1_WIFI_RX_NEW_PACKET_INT_ENA_R
• slchost::slc1host_int_ena::SLC1_WIFI_RX_NEW_PACKET_INT_ENA_W
• slchost::slc1host_int_ena::W
• slchost::slc1host_int_raw::R
• slchost::slc1host_int_raw::SLC1HOST_RX_EOF_INT_RAW_R
• slchost::slc1host_int_raw::SLC1HOST_RX_EOF_INT_RAW_W
• slchost::slc1host_int_raw::SLC1HOST_RX_SOF_INT_RAW_R
• slchost::slc1host_int_raw::SLC1HOST_RX_SOF_INT_RAW_W
• slchost::slc1host_int_raw::SLC1HOST_RX_START_INT_RAW_R
• slchost::slc1host_int_raw::SLC1HOST_RX_START_INT_RAW_W
• slchost::slc1host_int_raw::SLC1HOST_TX_START_INT_RAW_R
• slchost::slc1host_int_raw::SLC1HOST_TX_START_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_BT_RX_NEW_PACKET_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_BT_RX_NEW_PACKET_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_EXT_BIT0_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_EXT_BIT0_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_EXT_BIT1_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_EXT_BIT1_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_EXT_BIT2_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_EXT_BIT2_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_EXT_BIT3_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_EXT_BIT3_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_HOST_RD_RETRY_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_HOST_RD_RETRY_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_RX_PF_VALID_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_RX_PF_VALID_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_RX_UDF_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_RX_UDF_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT0_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT0_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT1_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT1_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT2_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT2_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT3_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT3_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT4_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT4_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT5_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT5_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT6_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT6_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT7_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_TOHOST_BIT7_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_TOKEN0_0TO1_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_TOKEN0_0TO1_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_TOKEN0_1TO0_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_TOKEN0_1TO0_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_TOKEN1_0TO1_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_TOKEN1_0TO1_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_TOKEN1_1TO0_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_TOKEN1_1TO0_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_TX_OVF_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_TX_OVF_INT_RAW_W
• slchost::slc1host_int_raw::SLC1_WIFI_RX_NEW_PACKET_INT_RAW_R
• slchost::slc1host_int_raw::SLC1_WIFI_RX_NEW_PACKET_INT_RAW_W
• slchost::slc1host_int_raw::W
• slchost::slc1host_int_st::R
• slchost::slc1host_int_st::SLC1HOST_RX_EOF_INT_ST_R
• slchost::slc1host_int_st::SLC1HOST_RX_SOF_INT_ST_R
• slchost::slc1host_int_st::SLC1HOST_RX_START_INT_ST_R
• slchost::slc1host_int_st::SLC1HOST_TX_START_INT_ST_R
• slchost::slc1host_int_st::SLC1_BT_RX_NEW_PACKET_INT_ST_R
• slchost::slc1host_int_st::SLC1_EXT_BIT0_INT_ST_R
• slchost::slc1host_int_st::SLC1_EXT_BIT1_INT_ST_R
• slchost::slc1host_int_st::SLC1_EXT_BIT2_INT_ST_R
• slchost::slc1host_int_st::SLC1_EXT_BIT3_INT_ST_R
• slchost::slc1host_int_st::SLC1_HOST_RD_RETRY_INT_ST_R
• slchost::slc1host_int_st::SLC1_RX_PF_VALID_INT_ST_R
• slchost::slc1host_int_st::SLC1_RX_UDF_INT_ST_R
• slchost::slc1host_int_st::SLC1_TOHOST_BIT0_INT_ST_R
• slchost::slc1host_int_st::SLC1_TOHOST_BIT1_INT_ST_R
• slchost::slc1host_int_st::SLC1_TOHOST_BIT2_INT_ST_R
• slchost::slc1host_int_st::SLC1_TOHOST_BIT3_INT_ST_R
• slchost::slc1host_int_st::SLC1_TOHOST_BIT4_INT_ST_R
• slchost::slc1host_int_st::SLC1_TOHOST_BIT5_INT_ST_R
• slchost::slc1host_int_st::SLC1_TOHOST_BIT6_INT_ST_R
• slchost::slc1host_int_st::SLC1_TOHOST_BIT7_INT_ST_R
• slchost::slc1host_int_st::SLC1_TOKEN0_0TO1_INT_ST_R
• slchost::slc1host_int_st::SLC1_TOKEN0_1TO0_INT_ST_R
• slchost::slc1host_int_st::SLC1_TOKEN1_0TO1_INT_ST_R
• slchost::slc1host_int_st::SLC1_TOKEN1_1TO0_INT_ST_R
• slchost::slc1host_int_st::SLC1_TX_OVF_INT_ST_R
• slchost::slc1host_int_st::SLC1_WIFI_RX_NEW_PACKET_INT_ST_R
• slchost::slc1host_rx_infor::R
• slchost::slc1host_rx_infor::SLC1HOST_RX_INFOR_R
• slchost::slc1host_rx_infor::SLC1HOST_RX_INFOR_W
• slchost::slc1host_rx_infor::W
• slchost::slc1host_token_rdata::HOSTSLCHOST_SLC1_TOKEN1_R
• slchost::slc1host_token_rdata::R
• slchost::slc1host_token_rdata::SLC1_RX_PF_EOF_R
• slchost::slc1host_token_rdata::SLC1_RX_PF_VALID_R
• slchost::slc1host_token_rdata::SLC1_TOKEN0_R
• slchost::slc1host_token_wdata::R
• slchost::slc1host_token_wdata::SLC1HOST_TOKEN0_WD_R
• slchost::slc1host_token_wdata::SLC1HOST_TOKEN0_WD_W
• slchost::slc1host_token_wdata::SLC1HOST_TOKEN1_WD_R
• slchost::slc1host_token_wdata::SLC1HOST_TOKEN1_WD_W
• slchost::slc1host_token_wdata::W
• slchost::slc_apbwin_conf::R
• slchost::slc_apbwin_conf::SLC_APBWIN_ADDR_R
• slchost::slc_apbwin_conf::SLC_APBWIN_ADDR_W
• slchost::slc_apbwin_conf::SLC_APBWIN_START_R
• slchost::slc_apbwin_conf::SLC_APBWIN_START_W
• slchost::slc_apbwin_conf::SLC_APBWIN_WR_R
• slchost::slc_apbwin_conf::SLC_APBWIN_WR_W
• slchost::slc_apbwin_conf::W
• slchost::slc_apbwin_rdata::R
• slchost::slc_apbwin_rdata::SLC_APBWIN_RDATA_R
• slchost::slc_apbwin_wdata::R
• slchost::slc_apbwin_wdata::SLC_APBWIN_WDATA_R
• slchost::slc_apbwin_wdata::SLC_APBWIN_WDATA_W
• slchost::slc_apbwin_wdata::W
• slchost::slchostdate::R
• slchost::slchostdate::SLCHOST_DATE_R
• slchost::slchostdate::SLCHOST_DATE_W
• slchost::slchostdate::W
• slchost::slchostid::R
• slchost::slchostid::SLCHOST_ID_R
• slchost::slchostid::SLCHOST_ID_W
• slchost::slchostid::W
• slchost::state_w0::R
• slchost::state_w0::SLCHOST_STATE0_R
• slchost::state_w0::SLCHOST_STATE1_R
• slchost::state_w0::SLCHOST_STATE2_R
• slchost::state_w0::SLCHOST_STATE3_R
• slchost::state_w1::R
• slchost::state_w1::SLCHOST_STATE4_R
• slchost::state_w1::SLCHOST_STATE5_R
• slchost::state_w1::SLCHOST_STATE6_R
• slchost::state_w1::SLCHOST_STATE7_R
• slchost::token_con::SLC0HOST_LEN_WR_W
• slchost::token_con::SLC0HOST_TOKEN0_DEC_W
• slchost::token_con::SLC0HOST_TOKEN0_WR_W
• slchost::token_con::SLC0HOST_TOKEN1_DEC_W
• slchost::token_con::SLC0HOST_TOKEN1_WR_W
• slchost::token_con::SLC1HOST_TOKEN0_DEC_W
• slchost::token_con::SLC1HOST_TOKEN0_WR_W
• slchost::token_con::SLC1HOST_TOKEN1_DEC_W
• slchost::token_con::SLC1HOST_TOKEN1_WR_W
• slchost::token_con::W
• slchost::win_cmd::R
• slchost::win_cmd::SLCHOST_WIN_CMD_R
• slchost::win_cmd::SLCHOST_WIN_CMD_W
• slchost::win_cmd::W
• soc_etm::CH_ENA_AD0
• soc_etm::CH_ENA_AD0_CLR
• soc_etm::CH_ENA_AD0_SET
• soc_etm::CH_ENA_AD1
• soc_etm::CH_ENA_AD1_CLR
• soc_etm::CH_ENA_AD1_SET
• soc_etm::CLK_EN
• soc_etm::DATE
• soc_etm::ch::EVT_ID
• soc_etm::ch::TASK_ID
• soc_etm::ch::evt_id::EVT_ID_R
• soc_etm::ch::evt_id::EVT_ID_W
• soc_etm::ch::evt_id::R
• soc_etm::ch::evt_id::W
• soc_etm::ch::task_id::R
• soc_etm::ch::task_id::TASK_ID_R
• soc_etm::ch::task_id::TASK_ID_W
• soc_etm::ch::task_id::W
• soc_etm::ch_ena_ad0::CH_ENA_R
• soc_etm::ch_ena_ad0::CH_ENA_W
• soc_etm::ch_ena_ad0::R
• soc_etm::ch_ena_ad0::W
• soc_etm::ch_ena_ad0_clr::CH_CLR_W
• soc_etm::ch_ena_ad0_clr::W
• soc_etm::ch_ena_ad0_set::CH_SET_W
• soc_etm::ch_ena_ad0_set::W
• soc_etm::ch_ena_ad1::CH_ENA_R
• soc_etm::ch_ena_ad1::CH_ENA_W
• soc_etm::ch_ena_ad1::R
• soc_etm::ch_ena_ad1::W
• soc_etm::ch_ena_ad1_clr::CH_CLR_W
• soc_etm::ch_ena_ad1_clr::W
• soc_etm::ch_ena_ad1_set::CH_SET_W
• soc_etm::ch_ena_ad1_set::W
• soc_etm::clk_en::CLK_EN_R
• soc_etm::clk_en::CLK_EN_W
• soc_etm::clk_en::R
• soc_etm::clk_en::W
• soc_etm::date::DATE_R
• soc_etm::date::DATE_W
• soc_etm::date::R
• soc_etm::date::W
• spi0::AXI_ERR_ADDR
• spi0::CACHE_FCTRL
• spi0::CACHE_SCTRL
• spi0::CLOCK
• spi0::CLOCK_GATE
• spi0::CMD
• spi0::CTRL
• spi0::CTRL1
• spi0::CTRL2
• spi0::DATE
• spi0::DDR
• spi0::DIN_MODE
• spi0::DIN_NUM
• spi0::DOUT_MODE
• spi0::DPA_CTRL
• spi0::ECC_CTRL
• spi0::ECC_ERR_ADDR
• spi0::FSM
• spi0::INT_CLR
• spi0::INT_ENA
• spi0::INT_RAW
• spi0::INT_ST
• spi0::MISC
• spi0::MMU_ITEM_CONTENT
• spi0::MMU_ITEM_INDEX
• spi0::MMU_POWER_CTRL
• spi0::PMS_REJECT
• spi0::RD_STATUS
• spi0::REGISTERRND_ECO_HIGH
• spi0::REGISTERRND_ECO_LOW
• spi0::SPI_FMEM_PMS_ADDR
• spi0::SPI_FMEM_PMS_ATTR
• spi0::SPI_FMEM_PMS_SIZE
• spi0::SPI_SMEM_AC
• spi0::SPI_SMEM_DDR
• spi0::SPI_SMEM_DIN_MODE
• spi0::SPI_SMEM_DIN_NUM
• spi0::SPI_SMEM_DOUT_MODE
• spi0::SPI_SMEM_ECC_CTRL
• spi0::SPI_SMEM_PMS_ADDR
• spi0::SPI_SMEM_PMS_ATTR
• spi0::SPI_SMEM_PMS_SIZE
• spi0::SPI_SMEM_TIMING_CALI
• spi0::SRAM_CLK
• spi0::SRAM_CMD
• spi0::SRAM_DRD_CMD
• spi0::SRAM_DWR_CMD
• spi0::TIMING_CALI
• spi0::USER
• spi0::USER1
• spi0::USER2
• spi0::XTS_DATE
• spi0::XTS_DESTINATION
• spi0::XTS_DESTROY
• spi0::XTS_LINESIZE
• spi0::XTS_PHYSICAL_ADDRESS
• spi0::XTS_PLAIN_BASE
• spi0::XTS_RELEASE
• spi0::XTS_STATE
• spi0::XTS_TRIGGER
• spi0::axi_err_addr::ALL_FIFO_EMPTY_R
• spi0::axi_err_addr::AXI_ERR_ADDR_R
• spi0::axi_err_addr::R
• spi0::axi_err_addr::SPI_ALL_AXI_TRANS_AFIFO_EMPTY_R
• spi0::axi_err_addr::SPI_RADDR_AFIFO_REMPTY_R
• spi0::axi_err_addr::SPI_RDATA_AFIFO_REMPTY_R
• spi0::axi_err_addr::SPI_WBLEN_AFIFO_REMPTY_R
• spi0::axi_err_addr::SPI_WDATA_AFIFO_REMPTY_R
• spi0::cache_fctrl::AXI_REQ_EN_R
• spi0::cache_fctrl::AXI_REQ_EN_W
• spi0::cache_fctrl::CACHE_FLASH_USR_CMD_R
• spi0::cache_fctrl::CACHE_FLASH_USR_CMD_W
• spi0::cache_fctrl::CACHE_USR_ADDR_4BYTE_R
• spi0::cache_fctrl::CACHE_USR_ADDR_4BYTE_W
• spi0::cache_fctrl::FADDR_DUAL_R
• spi0::cache_fctrl::FADDR_DUAL_W
• spi0::cache_fctrl::FADDR_QUAD_R
• spi0::cache_fctrl::FADDR_QUAD_W
• spi0::cache_fctrl::FDIN_DUAL_R
• spi0::cache_fctrl::FDIN_DUAL_W
• spi0::cache_fctrl::FDIN_QUAD_R
• spi0::cache_fctrl::FDIN_QUAD_W
• spi0::cache_fctrl::FDOUT_DUAL_R
• spi0::cache_fctrl::FDOUT_DUAL_W
• spi0::cache_fctrl::FDOUT_QUAD_R
• spi0::cache_fctrl::FDOUT_QUAD_W
• spi0::cache_fctrl::R
• spi0::cache_fctrl::SPI_CLOSE_AXI_INF_EN_R
• spi0::cache_fctrl::SPI_CLOSE_AXI_INF_EN_W
• spi0::cache_fctrl::SPI_SAME_AW_AR_ADDR_CHK_EN_R
• spi0::cache_fctrl::W
• spi0::cache_sctrl::CACHE_SRAM_USR_RCMD_R
• spi0::cache_sctrl::CACHE_SRAM_USR_WCMD_R
• spi0::cache_sctrl::CACHE_USR_SADDR_4BYTE_R
• spi0::cache_sctrl::R
• spi0::cache_sctrl::SRAM_ADDR_BITLEN_R
• spi0::cache_sctrl::SRAM_OCT_R
• spi0::cache_sctrl::SRAM_RDUMMY_CYCLELEN_R
• spi0::cache_sctrl::SRAM_WDUMMY_CYCLELEN_R
• spi0::cache_sctrl::USR_RD_SRAM_DUMMY_R
• spi0::cache_sctrl::USR_SRAM_DIO_R
• spi0::cache_sctrl::USR_SRAM_QIO_R
• spi0::cache_sctrl::USR_WR_SRAM_DUMMY_R
• spi0::clock::CLKCNT_H_R
• spi0::clock::CLKCNT_H_W
• spi0::clock::CLKCNT_L_R
• spi0::clock::CLKCNT_L_W
• spi0::clock::CLKCNT_N_R
• spi0::clock::CLKCNT_N_W
• spi0::clock::CLK_EQU_SYSCLK_R
• spi0::clock::CLK_EQU_SYSCLK_W
• spi0::clock::R
• spi0::clock::W
• spi0::clock_gate::R
• spi0::clock_gate::SPI_CLK_EN_R
• spi0::clock_gate::SPI_CLK_EN_W
• spi0::clock_gate::W
• spi0::cmd::MST_ST_R
• spi0::cmd::R
• spi0::cmd::SLV_ST_R
• spi0::cmd::USR_R
• spi0::ctrl1::AR_SPLICE_EN_R
• spi0::ctrl1::AW_SPLICE_EN_R
• spi0::ctrl1::CLK_MODE_R
• spi0::ctrl1::CLK_MODE_W
• spi0::ctrl1::DUAL_RAM_EN_R
• spi0::ctrl1::FAST_WRITE_EN_R
• spi0::ctrl1::FAST_WRITE_EN_W
• spi0::ctrl1::R
• spi0::ctrl1::RAM0_EN_R
• spi0::ctrl1::RRESP_ECC_ERR_EN_R
• spi0::ctrl1::RRESP_ECC_ERR_EN_W
• spi0::ctrl1::RXFIFO_RST_W
• spi0::ctrl1::SPI_AR_SIZE0_1_SUPPORT_EN_R
• spi0::ctrl1::SPI_AR_SIZE0_1_SUPPORT_EN_W
• spi0::ctrl1::SPI_AW_SIZE0_1_SUPPORT_EN_R
• spi0::ctrl1::SPI_AW_SIZE0_1_SUPPORT_EN_W
• spi0::ctrl1::SPI_AXI_RDATA_BACK_FAST_R
• spi0::ctrl1::TXFIFO_RST_W
• spi0::ctrl1::W
• spi0::ctrl2::CS_HOLD_DELAY_R
• spi0::ctrl2::CS_HOLD_DELAY_W
• spi0::ctrl2::CS_HOLD_TIME_R
• spi0::ctrl2::CS_HOLD_TIME_W
• spi0::ctrl2::CS_SETUP_TIME_R
• spi0::ctrl2::CS_SETUP_TIME_W
• spi0::ctrl2::ECC_16TO18_BYTE_EN_R
• spi0::ctrl2::ECC_CS_HOLD_TIME_R
• spi0::ctrl2::ECC_SKIP_PAGE_CORNER_R
• spi0::ctrl2::R
• spi0::ctrl2::SPLIT_TRANS_EN_R
• spi0::ctrl2::SYNC_RESET_W
• spi0::ctrl2::W
• spi0::ctrl::DATA_IE_ALWAYS_ON_R
• spi0::ctrl::DATA_IE_ALWAYS_ON_W
• spi0::ctrl::DQS_IE_ALWAYS_ON_R
• spi0::ctrl::D_POL_R
• spi0::ctrl::D_POL_W
• spi0::ctrl::FADDR_OCT_R
• spi0::ctrl::FASTRD_MODE_R
• spi0::ctrl::FASTRD_MODE_W
• spi0::ctrl::FCMD_OCT_R
• spi0::ctrl::FCMD_QUAD_R
• spi0::ctrl::FCMD_QUAD_W
• spi0::ctrl::FDIN_OCT_R
• spi0::ctrl::FDOUT_OCT_R
• spi0::ctrl::FDUMMY_RIN_R
• spi0::ctrl::FDUMMY_RIN_W
• spi0::ctrl::FDUMMY_WOUT_R
• spi0::ctrl::FDUMMY_WOUT_W
• spi0::ctrl::FREAD_DIO_R
• spi0::ctrl::FREAD_DIO_W
• spi0::ctrl::FREAD_DUAL_R
• spi0::ctrl::FREAD_DUAL_W
• spi0::ctrl::FREAD_QIO_R
• spi0::ctrl::FREAD_QIO_W
• spi0::ctrl::FREAD_QUAD_R
• spi0::ctrl::FREAD_QUAD_W
• spi0::ctrl::Q_POL_R
• spi0::ctrl::Q_POL_W
• spi0::ctrl::R
• spi0::ctrl::W
• spi0::ctrl::WDUMMY_ALWAYS_OUT_R
• spi0::ctrl::WDUMMY_ALWAYS_OUT_W
• spi0::ctrl::WDUMMY_DQS_ALWAYS_OUT_R
• spi0::ctrl::WP_R
• spi0::ctrl::WP_W
• spi0::date::DATE_R
• spi0::date::DATE_W
• spi0::date::R
• spi0::date::W
• spi0::ddr::R
• spi0::ddr::SPI_FMEM_CLK_DIFF_EN_R
• spi0::ddr::SPI_FMEM_CLK_DIFF_INV_R
• spi0::ddr::SPI_FMEM_DDR_CMD_DIS_R
• spi0::ddr::SPI_FMEM_DDR_DQS_LOOP_R
• spi0::ddr::SPI_FMEM_DDR_EN_R
• spi0::ddr::SPI_FMEM_DDR_RDAT_SWP_R
• spi0::ddr::SPI_FMEM_DDR_WDAT_SWP_R
• spi0::ddr::SPI_FMEM_DQS_CA_IN_R
• spi0::ddr::SPI_FMEM_HYPERBUS_CA_R
• spi0::ddr::SPI_FMEM_HYPERBUS_DUMMY_2X_R
• spi0::ddr::SPI_FMEM_OCTA_RAM_ADDR_R
• spi0::ddr::SPI_FMEM_OUTMINBYTELEN_R
• spi0::ddr::SPI_FMEM_RX_DDR_MSK_EN_R
• spi0::ddr::SPI_FMEM_TX_DDR_MSK_EN_R
• spi0::ddr::SPI_FMEM_USR_DDR_DQS_THD_R
• spi0::ddr::SPI_FMEM_VAR_DUMMY_R
• spi0::din_mode::DIN0_MODE_R
• spi0::din_mode::DIN0_MODE_W
• spi0::din_mode::DIN1_MODE_R
• spi0::din_mode::DIN1_MODE_W
• spi0::din_mode::DIN2_MODE_R
• spi0::din_mode::DIN2_MODE_W
• spi0::din_mode::DIN3_MODE_R
• spi0::din_mode::DIN3_MODE_W
• spi0::din_mode::DIN4_MODE_R
• spi0::din_mode::DIN4_MODE_W
• spi0::din_mode::DIN5_MODE_R
• spi0::din_mode::DIN5_MODE_W
• spi0::din_mode::DIN6_MODE_R
• spi0::din_mode::DIN6_MODE_W
• spi0::din_mode::DIN7_MODE_R
• spi0::din_mode::DIN7_MODE_W
• spi0::din_mode::DINS_MODE_R
• spi0::din_mode::DINS_MODE_W
• spi0::din_mode::R
• spi0::din_mode::W
• spi0::din_num::DIN0_NUM_R
• spi0::din_num::DIN0_NUM_W
• spi0::din_num::DIN1_NUM_R
• spi0::din_num::DIN1_NUM_W
• spi0::din_num::DIN2_NUM_R
• spi0::din_num::DIN2_NUM_W
• spi0::din_num::DIN3_NUM_R
• spi0::din_num::DIN3_NUM_W
• spi0::din_num::DIN4_NUM_R
• spi0::din_num::DIN4_NUM_W
• spi0::din_num::DIN5_NUM_R
• spi0::din_num::DIN5_NUM_W
• spi0::din_num::DIN6_NUM_R
• spi0::din_num::DIN6_NUM_W
• spi0::din_num::DIN7_NUM_R
• spi0::din_num::DIN7_NUM_W
• spi0::din_num::DINS_NUM_R
• spi0::din_num::DINS_NUM_W
• spi0::din_num::R
• spi0::din_num::W
• spi0::dout_mode::DOUT0_MODE_R
• spi0::dout_mode::DOUT0_MODE_W
• spi0::dout_mode::DOUT1_MODE_R
• spi0::dout_mode::DOUT1_MODE_W
• spi0::dout_mode::DOUT2_MODE_R
• spi0::dout_mode::DOUT2_MODE_W
• spi0::dout_mode::DOUT3_MODE_R
• spi0::dout_mode::DOUT3_MODE_W
• spi0::dout_mode::DOUT4_MODE_R
• spi0::dout_mode::DOUT4_MODE_W
• spi0::dout_mode::DOUT5_MODE_R
• spi0::dout_mode::DOUT5_MODE_W
• spi0::dout_mode::DOUT6_MODE_R
• spi0::dout_mode::DOUT6_MODE_W
• spi0::dout_mode::DOUT7_MODE_R
• spi0::dout_mode::DOUT7_MODE_W
• spi0::dout_mode::DOUTS_MODE_R
• spi0::dout_mode::DOUTS_MODE_W
• spi0::dout_mode::R
• spi0::dout_mode::W
• spi0::dpa_ctrl::R
• spi0::dpa_ctrl::SPI_CRYPT_CALC_D_DPA_EN_R
• spi0::dpa_ctrl::SPI_CRYPT_CALC_D_DPA_EN_W
• spi0::dpa_ctrl::SPI_CRYPT_DPA_SELECT_REGISTER_R
• spi0::dpa_ctrl::SPI_CRYPT_DPA_SELECT_REGISTER_W
• spi0::dpa_ctrl::SPI_CRYPT_SECURITY_LEVEL_R
• spi0::dpa_ctrl::SPI_CRYPT_SECURITY_LEVEL_W
• spi0::dpa_ctrl::W
• spi0::ecc_ctrl::ECC_CONTINUE_RECORD_ERR_EN_R
• spi0::ecc_ctrl::ECC_ERR_BITS_R
• spi0::ecc_ctrl::R
• spi0::ecc_ctrl::SPI_FMEM_ECC_ADDR_EN_R
• spi0::ecc_ctrl::SPI_FMEM_ECC_ERR_INT_EN_R
• spi0::ecc_ctrl::SPI_FMEM_ECC_ERR_INT_NUM_R
• spi0::ecc_ctrl::SPI_FMEM_PAGE_SIZE_R
• spi0::ecc_ctrl::SPI_FMEM_PAGE_SIZE_W
• spi0::ecc_ctrl::USR_ECC_ADDR_EN_R
• spi0::ecc_ctrl::W
• spi0::ecc_err_addr::ECC_ERR_ADDR_R
• spi0::ecc_err_addr::ECC_ERR_CNT_R
• spi0::ecc_err_addr::R
• spi0::fsm::LOCK_DELAY_TIME_R
• spi0::fsm::LOCK_DELAY_TIME_W
• spi0::fsm::R
• spi0::fsm::W
• spi0::int_clr::AXI_RADDR_ERR_W
• spi0::int_clr::AXI_WADDR_ERR_R
• spi0::int_clr::AXI_WR_FLASH_ERR_R
• spi0::int_clr::ECC_ERR_R
• spi0::int_clr::MST_ST_END_W
• spi0::int_clr::PMS_REJECT_W
• spi0::int_clr::R
• spi0::int_clr::SLV_ST_END_W
• spi0::int_clr::W
• spi0::int_ena::AXI_RADDR_ERR_R
• spi0::int_ena::AXI_RADDR_ERR_W
• spi0::int_ena::AXI_WADDR_ERR_INT__ENA_R
• spi0::int_ena::AXI_WR_FLASH_ERR_R
• spi0::int_ena::ECC_ERR_R
• spi0::int_ena::MST_ST_END_R
• spi0::int_ena::MST_ST_END_W
• spi0::int_ena::PMS_REJECT_R
• spi0::int_ena::PMS_REJECT_W
• spi0::int_ena::R
• spi0::int_ena::SLV_ST_END_R
• spi0::int_ena::SLV_ST_END_W
• spi0::int_ena::W
• spi0::int_raw::AXI_RADDR_ERR_R
• spi0::int_raw::AXI_RADDR_ERR_W
• spi0::int_raw::AXI_WADDR_ERR_R
• spi0::int_raw::AXI_WR_FLASH_ERR_R
• spi0::int_raw::ECC_ERR_R
• spi0::int_raw::MST_ST_END_R
• spi0::int_raw::MST_ST_END_W
• spi0::int_raw::PMS_REJECT_R
• spi0::int_raw::PMS_REJECT_W
• spi0::int_raw::R
• spi0::int_raw::SLV_ST_END_R
• spi0::int_raw::SLV_ST_END_W
• spi0::int_raw::W
• spi0::int_st::AXI_RADDR_ERR_R
• spi0::int_st::AXI_WADDR_ERR_R
• spi0::int_st::AXI_WR_FLASH_ERR_R
• spi0::int_st::ECC_ERR_R
• spi0::int_st::MST_ST_END_R
• spi0::int_st::PMS_REJECT_R
• spi0::int_st::R
• spi0::int_st::SLV_ST_END_R
• spi0::misc::CK_IDLE_EDGE_R
• spi0::misc::CK_IDLE_EDGE_W
• spi0::misc::CS_KEEP_ACTIVE_R
• spi0::misc::CS_KEEP_ACTIVE_W
• spi0::misc::FSUB_PIN_R
• spi0::misc::R
• spi0::misc::SSUB_PIN_R
• spi0::misc::W
• spi0::mmu_item_content::R
• spi0::mmu_item_content::SPI_MMU_ITEM_CONTENT_R
• spi0::mmu_item_content::SPI_MMU_ITEM_CONTENT_W
• spi0::mmu_item_content::W
• spi0::mmu_item_index::R
• spi0::mmu_item_index::SPI_MMU_ITEM_INDEX_R
• spi0::mmu_item_index::SPI_MMU_ITEM_INDEX_W
• spi0::mmu_item_index::W
• spi0::mmu_power_ctrl::AUX_CTRL_R
• spi0::mmu_power_ctrl::R
• spi0::mmu_power_ctrl::RDN_ENA_R
• spi0::mmu_power_ctrl::RDN_RESULT_R
• spi0::mmu_power_ctrl::SPI_MMU_MEM_FORCE_ON_R
• spi0::mmu_power_ctrl::SPI_MMU_MEM_FORCE_ON_W
• spi0::mmu_power_ctrl::SPI_MMU_MEM_FORCE_PD_R
• spi0::mmu_power_ctrl::SPI_MMU_MEM_FORCE_PD_W
• spi0::mmu_power_ctrl::SPI_MMU_MEM_FORCE_PU_R
• spi0::mmu_power_ctrl::SPI_MMU_MEM_FORCE_PU_W
• spi0::mmu_power_ctrl::SPI_MMU_PAGE_SIZE_R
• spi0::mmu_power_ctrl::SPI_MMU_PAGE_SIZE_W
• spi0::mmu_power_ctrl::W
• spi0::pms_reject::PMS_IVD_R
• spi0::pms_reject::PMS_LD_R
• spi0::pms_reject::PMS_MULTI_HIT_R
• spi0::pms_reject::PMS_ST_R
• spi0::pms_reject::PM_EN_R
• spi0::pms_reject::PM_EN_W
• spi0::pms_reject::R
• spi0::pms_reject::REJECT_ADDR_R
• spi0::pms_reject::W
• spi0::rd_status::R
• spi0::rd_status::W
• spi0::rd_status::WB_MODE_R
• spi0::rd_status::WB_MODE_W
• spi0::registerrnd_eco_high::R
• spi0::registerrnd_eco_high::REGISTERRND_ECO_HIGH_R
• spi0::registerrnd_eco_low::R
• spi0::registerrnd_eco_low::REGISTERRND_ECO_LOW_R
• spi0::spi_fmem_pms_addr::R
• spi0::spi_fmem_pms_addr::S_R
• spi0::spi_fmem_pms_addr::S_W
• spi0::spi_fmem_pms_addr::W
• spi0::spi_fmem_pms_attr::R
• spi0::spi_fmem_pms_attr::SPI_FMEM_PMS_ECC_R
• spi0::spi_fmem_pms_attr::SPI_FMEM_PMS_ECC_W
• spi0::spi_fmem_pms_attr::SPI_FMEM_PMS_RD_ATTR_R
• spi0::spi_fmem_pms_attr::SPI_FMEM_PMS_RD_ATTR_W
• spi0::spi_fmem_pms_attr::SPI_FMEM_PMS_WR_ATTR_R
• spi0::spi_fmem_pms_attr::SPI_FMEM_PMS_WR_ATTR_W
• spi0::spi_fmem_pms_attr::W
• spi0::spi_fmem_pms_size::R
• spi0::spi_fmem_pms_size::SPI_FMEM_PMS_SIZE_R
• spi0::spi_fmem_pms_size::SPI_FMEM_PMS_SIZE_W
• spi0::spi_fmem_pms_size::W
• spi0::spi_smem_ac::R
• spi0::spi_smem_ac::SPI_SMEM_CS_HOLD_DELAY_R
• spi0::spi_smem_ac::SPI_SMEM_CS_HOLD_R
• spi0::spi_smem_ac::SPI_SMEM_CS_HOLD_TIME_R
• spi0::spi_smem_ac::SPI_SMEM_CS_SETUP_R
• spi0::spi_smem_ac::SPI_SMEM_CS_SETUP_TIME_R
• spi0::spi_smem_ac::SPI_SMEM_ECC_16TO18_BYTE_EN_R
• spi0::spi_smem_ac::SPI_SMEM_ECC_CS_HOLD_TIME_R
• spi0::spi_smem_ac::SPI_SMEM_ECC_SKIP_PAGE_CORNER_R
• spi0::spi_smem_ac::SPI_SMEM_SPLIT_TRANS_EN_R
• spi0::spi_smem_ddr::CMD_DIS_R
• spi0::spi_smem_ddr::DQS_LOOP_R
• spi0::spi_smem_ddr::EN_R
• spi0::spi_smem_ddr::R
• spi0::spi_smem_ddr::RDAT_SWP_R
• spi0::spi_smem_ddr::SPI_SMEM_CLK_DIFF_EN_R
• spi0::spi_smem_ddr::SPI_SMEM_CLK_DIFF_INV_R
• spi0::spi_smem_ddr::SPI_SMEM_DQS_CA_IN_R
• spi0::spi_smem_ddr::SPI_SMEM_HYPERBUS_CA_R
• spi0::spi_smem_ddr::SPI_SMEM_HYPERBUS_DUMMY_2X_R
• spi0::spi_smem_ddr::SPI_SMEM_OCTA_RAM_ADDR_R
• spi0::spi_smem_ddr::SPI_SMEM_OUTMINBYTELEN_R
• spi0::spi_smem_ddr::SPI_SMEM_RX_DDR_MSK_EN_R
• spi0::spi_smem_ddr::SPI_SMEM_TX_DDR_MSK_EN_R
• spi0::spi_smem_ddr::SPI_SMEM_USR_DDR_DQS_THD_R
• spi0::spi_smem_ddr::SPI_SMEM_VAR_DUMMY_R
• spi0::spi_smem_ddr::WDAT_SWP_R
• spi0::spi_smem_din_mode::R
• spi0::spi_smem_din_mode::SPI_SMEM_DIN0_MODE_R
• spi0::spi_smem_din_mode::SPI_SMEM_DIN1_MODE_R
• spi0::spi_smem_din_mode::SPI_SMEM_DIN2_MODE_R
• spi0::spi_smem_din_mode::SPI_SMEM_DIN3_MODE_R
• spi0::spi_smem_din_mode::SPI_SMEM_DIN4_MODE_R
• spi0::spi_smem_din_mode::SPI_SMEM_DIN5_MODE_R
• spi0::spi_smem_din_mode::SPI_SMEM_DIN6_MODE_R
• spi0::spi_smem_din_mode::SPI_SMEM_DIN7_MODE_R
• spi0::spi_smem_din_mode::SPI_SMEM_DINS_MODE_R
• spi0::spi_smem_din_num::R
• spi0::spi_smem_din_num::SPI_SMEM_DIN0_NUM_R
• spi0::spi_smem_din_num::SPI_SMEM_DIN1_NUM_R
• spi0::spi_smem_din_num::SPI_SMEM_DIN2_NUM_R
• spi0::spi_smem_din_num::SPI_SMEM_DIN3_NUM_R
• spi0::spi_smem_din_num::SPI_SMEM_DIN4_NUM_R
• spi0::spi_smem_din_num::SPI_SMEM_DIN5_NUM_R
• spi0::spi_smem_din_num::SPI_SMEM_DIN6_NUM_R
• spi0::spi_smem_din_num::SPI_SMEM_DIN7_NUM_R
• spi0::spi_smem_din_num::SPI_SMEM_DINS_NUM_R
• spi0::spi_smem_dout_mode::R
• spi0::spi_smem_dout_mode::SPI_SMEM_DOUT0_MODE_R
• spi0::spi_smem_dout_mode::SPI_SMEM_DOUT1_MODE_R
• spi0::spi_smem_dout_mode::SPI_SMEM_DOUT2_MODE_R
• spi0::spi_smem_dout_mode::SPI_SMEM_DOUT3_MODE_R
• spi0::spi_smem_dout_mode::SPI_SMEM_DOUT4_MODE_R
• spi0::spi_smem_dout_mode::SPI_SMEM_DOUT5_MODE_R
• spi0::spi_smem_dout_mode::SPI_SMEM_DOUT6_MODE_R
• spi0::spi_smem_dout_mode::SPI_SMEM_DOUT7_MODE_R
• spi0::spi_smem_dout_mode::SPI_SMEM_DOUTS_MODE_R
• spi0::spi_smem_ecc_ctrl::R
• spi0::spi_smem_ecc_ctrl::SPI_SMEM_ECC_ADDR_EN_R
• spi0::spi_smem_ecc_ctrl::SPI_SMEM_ECC_ERR_INT_EN_R
• spi0::spi_smem_ecc_ctrl::SPI_SMEM_PAGE_SIZE_R
• spi0::spi_smem_pms_addr::R
• spi0::spi_smem_pms_addr::S_R
• spi0::spi_smem_pms_addr::S_W
• spi0::spi_smem_pms_addr::W
• spi0::spi_smem_pms_attr::R
• spi0::spi_smem_pms_attr::SPI_SMEM_PMS_ECC_R
• spi0::spi_smem_pms_attr::SPI_SMEM_PMS_ECC_W
• spi0::spi_smem_pms_attr::SPI_SMEM_PMS_RD_ATTR_R
• spi0::spi_smem_pms_attr::SPI_SMEM_PMS_RD_ATTR_W
• spi0::spi_smem_pms_attr::SPI_SMEM_PMS_WR_ATTR_R
• spi0::spi_smem_pms_attr::SPI_SMEM_PMS_WR_ATTR_W
• spi0::spi_smem_pms_attr::W
• spi0::spi_smem_pms_size::R
• spi0::spi_smem_pms_size::SPI_SMEM_PMS_SIZE_R
• spi0::spi_smem_pms_size::SPI_SMEM_PMS_SIZE_W
• spi0::spi_smem_pms_size::W
• spi0::spi_smem_timing_cali::R
• spi0::spi_smem_timing_cali::SPI_SMEM_DLL_TIMING_CALI_R
• spi0::spi_smem_timing_cali::SPI_SMEM_EXTRA_DUMMY_CYCLELEN_R
• spi0::spi_smem_timing_cali::SPI_SMEM_TIMING_CALI_R
• spi0::spi_smem_timing_cali::SPI_SMEM_TIMING_CLK_ENA_R
• spi0::sram_clk::R
• spi0::sram_clk::SCLKCNT_H_R
• spi0::sram_clk::SCLKCNT_L_R
• spi0::sram_clk::SCLKCNT_N_R
• spi0::sram_clk::SCLK_EQU_SYSCLK_R
• spi0::sram_cmd::R
• spi0::sram_cmd::SADDR_DUAL_R
• spi0::sram_cmd::SADDR_OCT_R
• spi0::sram_cmd::SADDR_QUAD_R
• spi0::sram_cmd::SCLK_MODE_R
• spi0::sram_cmd::SCMD_OCT_R
• spi0::sram_cmd::SCMD_QUAD_R
• spi0::sram_cmd::SDIN_DUAL_R
• spi0::sram_cmd::SDIN_OCT_R
• spi0::sram_cmd::SDIN_QUAD_R
• spi0::sram_cmd::SDOUT_DUAL_R
• spi0::sram_cmd::SDOUT_OCT_R
• spi0::sram_cmd::SDOUT_QUAD_R
• spi0::sram_cmd::SDUMMY_RIN_R
• spi0::sram_cmd::SDUMMY_RIN_W
• spi0::sram_cmd::SDUMMY_WOUT_R
• spi0::sram_cmd::SPI_SMEM_DATA_IE_ALWAYS_ON_R
• spi0::sram_cmd::SPI_SMEM_DQS_IE_ALWAYS_ON_R
• spi0::sram_cmd::SPI_SMEM_WDUMMY_ALWAYS_OUT_R
• spi0::sram_cmd::SPI_SMEM_WDUMMY_DQS_ALWAYS_OUT_R
• spi0::sram_cmd::SWB_MODE_R
• spi0::sram_cmd::W
• spi0::sram_drd_cmd::CACHE_SRAM_USR_RD_CMD_BITLEN_R
• spi0::sram_drd_cmd::CACHE_SRAM_USR_RD_CMD_VALUE_R
• spi0::sram_drd_cmd::R
• spi0::sram_dwr_cmd::CACHE_SRAM_USR_WR_CMD_BITLEN_R
• spi0::sram_dwr_cmd::CACHE_SRAM_USR_WR_CMD_VALUE_R
• spi0::sram_dwr_cmd::R
• spi0::timing_cali::DLL_TIMING_CALI_R
• spi0::timing_cali::EXTRA_DUMMY_CYCLELEN_R
• spi0::timing_cali::EXTRA_DUMMY_CYCLELEN_W
• spi0::timing_cali::R
• spi0::timing_cali::TIMING_CALI_R
• spi0::timing_cali::TIMING_CALI_W
• spi0::timing_cali::TIMING_CLK_ENA_R
• spi0::timing_cali::TIMING_CLK_ENA_W
• spi0::timing_cali::UPDATE_W
• spi0::timing_cali::W
• spi0::user1::R
• spi0::user1::USR_ADDR_BITLEN_R
• spi0::user1::USR_ADDR_BITLEN_W
• spi0::user1::USR_DBYTELEN_R
• spi0::user1::USR_DUMMY_CYCLELEN_R
• spi0::user1::USR_DUMMY_CYCLELEN_W
• spi0::user1::W
• spi0::user2::R
• spi0::user2::USR_COMMAND_BITLEN_R
• spi0::user2::USR_COMMAND_BITLEN_W
• spi0::user2::USR_COMMAND_VALUE_R
• spi0::user2::USR_COMMAND_VALUE_W
• spi0::user2::W
• spi0::user::CK_OUT_EDGE_R
• spi0::user::CK_OUT_EDGE_W
• spi0::user::CS_HOLD_R
• spi0::user::CS_HOLD_W
• spi0::user::CS_SETUP_R
• spi0::user::CS_SETUP_W
• spi0::user::R
• spi0::user::USR_DUMMY_IDLE_R
• spi0::user::USR_DUMMY_IDLE_W
• spi0::user::USR_DUMMY_R
• spi0::user::USR_DUMMY_W
• spi0::user::W
• spi0::xts_date::R
• spi0::xts_date::SPI_XTS_DATE_R
• spi0::xts_date::SPI_XTS_DATE_W
• spi0::xts_date::W
• spi0::xts_destination::R
• spi0::xts_destination::SPI_XTS_DESTINATION_R
• spi0::xts_destination::SPI_XTS_DESTINATION_W
• spi0::xts_destination::W
• spi0::xts_destroy::SPI_XTS_DESTROY_W
• spi0::xts_destroy::W
• spi0::xts_linesize::R
• spi0::xts_linesize::SPI_XTS_LINESIZE_R
• spi0::xts_linesize::SPI_XTS_LINESIZE_W
• spi0::xts_linesize::W
• spi0::xts_physical_address::R
• spi0::xts_physical_address::SPI_XTS_PHYSICAL_ADDRESS_R
• spi0::xts_physical_address::SPI_XTS_PHYSICAL_ADDRESS_W
• spi0::xts_physical_address::W
• spi0::xts_plain_base::R
• spi0::xts_plain_base::SPI_XTS_PLAIN_R
• spi0::xts_plain_base::SPI_XTS_PLAIN_W
• spi0::xts_plain_base::W
• spi0::xts_release::SPI_XTS_RELEASE_W
• spi0::xts_release::W
• spi0::xts_state::R
• spi0::xts_state::SPI_XTS_STATE_R
• spi0::xts_trigger::SPI_XTS_TRIGGER_W
• spi0::xts_trigger::W
• spi1::ADDR
• spi1::CACHE_FCTRL
• spi1::CLOCK
• spi1::CLOCK_GATE
• spi1::CMD
• spi1::CTRL
• spi1::CTRL1
• spi1::CTRL2
• spi1::DATE
• spi1::DDR
• spi1::FLASH_SUS_CMD
• spi1::FLASH_SUS_CTRL
• spi1::FLASH_WAITI_CTRL
• spi1::INT_CLR
• spi1::INT_ENA
• spi1::INT_RAW
• spi1::INT_ST
• spi1::MISC
• spi1::MISO_DLEN
• spi1::MOSI_DLEN
• spi1::RD_STATUS
• spi1::SUS_STATUS
• spi1::TIMING_CALI
• spi1::TX_CRC
• spi1::USER
• spi1::USER1
• spi1::USER2
• spi1::W
• spi1::addr::R
• spi1::addr::USR_ADDR_VALUE_R
• spi1::addr::USR_ADDR_VALUE_W
• spi1::addr::W
• spi1::cache_fctrl::CACHE_USR_ADDR_4BYTE_R
• spi1::cache_fctrl::CACHE_USR_ADDR_4BYTE_W
• spi1::cache_fctrl::FADDR_DUAL_R
• spi1::cache_fctrl::FADDR_DUAL_W
• spi1::cache_fctrl::FADDR_QUAD_R
• spi1::cache_fctrl::FADDR_QUAD_W
• spi1::cache_fctrl::FDIN_DUAL_R
• spi1::cache_fctrl::FDIN_DUAL_W
• spi1::cache_fctrl::FDIN_QUAD_R
• spi1::cache_fctrl::FDIN_QUAD_W
• spi1::cache_fctrl::FDOUT_DUAL_R
• spi1::cache_fctrl::FDOUT_DUAL_W
• spi1::cache_fctrl::FDOUT_QUAD_R
• spi1::cache_fctrl::FDOUT_QUAD_W
• spi1::cache_fctrl::R
• spi1::cache_fctrl::W
• spi1::clock::CLKCNT_H_R
• spi1::clock::CLKCNT_H_W
• spi1::clock::CLKCNT_L_R
• spi1::clock::CLKCNT_L_W
• spi1::clock::CLKCNT_N_R
• spi1::clock::CLKCNT_N_W
• spi1::clock::CLK_EQU_SYSCLK_R
• spi1::clock::CLK_EQU_SYSCLK_W
• spi1::clock::R
• spi1::clock::W
• spi1::clock_gate::CLK_EN_R
• spi1::clock_gate::CLK_EN_W
• spi1::clock_gate::R
• spi1::clock_gate::W
• spi1::cmd::FLASH_BE_R
• spi1::cmd::FLASH_BE_W
• spi1::cmd::FLASH_CE_R
• spi1::cmd::FLASH_CE_W
• spi1::cmd::FLASH_DP_R
• spi1::cmd::FLASH_DP_W
• spi1::cmd::FLASH_HPM_R
• spi1::cmd::FLASH_HPM_W
• spi1::cmd::FLASH_PE_R
• spi1::cmd::FLASH_PE_W
• spi1::cmd::FLASH_PP_R
• spi1::cmd::FLASH_PP_W
• spi1::cmd::FLASH_RDID_R
• spi1::cmd::FLASH_RDID_W
• spi1::cmd::FLASH_RDSR_R
• spi1::cmd::FLASH_RDSR_W
• spi1::cmd::FLASH_READ_R
• spi1::cmd::FLASH_READ_W
• spi1::cmd::FLASH_RES_R
• spi1::cmd::FLASH_RES_W
• spi1::cmd::FLASH_SE_R
• spi1::cmd::FLASH_SE_W
• spi1::cmd::FLASH_WRDI_R
• spi1::cmd::FLASH_WRDI_W
• spi1::cmd::FLASH_WREN_R
• spi1::cmd::FLASH_WREN_W
• spi1::cmd::FLASH_WRSR_R
• spi1::cmd::FLASH_WRSR_W
• spi1::cmd::MST_ST_R
• spi1::cmd::R
• spi1::cmd::SLV_ST_R
• spi1::cmd::USR_R
• spi1::cmd::USR_W
• spi1::cmd::W
• spi1::ctrl1::CLK_MODE_R
• spi1::ctrl1::CLK_MODE_W
• spi1::ctrl1::CS_HOLD_DLY_RES_R
• spi1::ctrl1::CS_HOLD_DLY_RES_W
• spi1::ctrl1::R
• spi1::ctrl1::W
• spi1::ctrl2::SYNC_RESET_W
• spi1::ctrl2::W
• spi1::ctrl::D_POL_R
• spi1::ctrl::D_POL_W
• spi1::ctrl::FADDR_OCT_R
• spi1::ctrl::FASTRD_MODE_R
• spi1::ctrl::FASTRD_MODE_W
• spi1::ctrl::FCMD_OCT_R
• spi1::ctrl::FCMD_QUAD_R
• spi1::ctrl::FCMD_QUAD_W
• spi1::ctrl::FCS_CRC_EN_R
• spi1::ctrl::FDIN_OCT_R
• spi1::ctrl::FDOUT_OCT_R
• spi1::ctrl::FDUMMY_RIN_R
• spi1::ctrl::FDUMMY_RIN_W
• spi1::ctrl::FDUMMY_WOUT_R
• spi1::ctrl::FDUMMY_WOUT_W
• spi1::ctrl::FREAD_DIO_R
• spi1::ctrl::FREAD_DIO_W
• spi1::ctrl::FREAD_DUAL_R
• spi1::ctrl::FREAD_DUAL_W
• spi1::ctrl::FREAD_QIO_R
• spi1::ctrl::FREAD_QIO_W
• spi1::ctrl::FREAD_QUAD_R
• spi1::ctrl::FREAD_QUAD_W
• spi1::ctrl::Q_POL_R
• spi1::ctrl::Q_POL_W
• spi1::ctrl::R
• spi1::ctrl::RESANDRES_R
• spi1::ctrl::RESANDRES_W
• spi1::ctrl::TX_CRC_EN_R
• spi1::ctrl::W
• spi1::ctrl::WP_R
• spi1::ctrl::WP_W
• spi1::ctrl::WRSR_2B_R
• spi1::ctrl::WRSR_2B_W
• spi1::date::DATE_R
• spi1::date::DATE_W
• spi1::date::R
• spi1::date::W
• spi1::ddr::R
• spi1::ddr::SPI_FMEM_CLK_DIFF_EN_R
• spi1::ddr::SPI_FMEM_CLK_DIFF_INV_R
• spi1::ddr::SPI_FMEM_DDR_CMD_DIS_R
• spi1::ddr::SPI_FMEM_DDR_DQS_LOOP_R
• spi1::ddr::SPI_FMEM_DDR_EN_R
• spi1::ddr::SPI_FMEM_DDR_RDAT_SWP_R
• spi1::ddr::SPI_FMEM_DDR_WDAT_SWP_R
• spi1::ddr::SPI_FMEM_DQS_CA_IN_R
• spi1::ddr::SPI_FMEM_HYPERBUS_CA_R
• spi1::ddr::SPI_FMEM_HYPERBUS_DUMMY_2X_R
• spi1::ddr::SPI_FMEM_OCTA_RAM_ADDR_R
• spi1::ddr::SPI_FMEM_OUTMINBYTELEN_R
• spi1::ddr::SPI_FMEM_USR_DDR_DQS_THD_R
• spi1::ddr::SPI_FMEM_VAR_DUMMY_R
• spi1::flash_sus_cmd::FLASH_PES_COMMAND_R
• spi1::flash_sus_cmd::FLASH_PES_COMMAND_W
• spi1::flash_sus_cmd::R
• spi1::flash_sus_cmd::W
• spi1::flash_sus_cmd::WAIT_PESR_COMMAND_R
• spi1::flash_sus_cmd::WAIT_PESR_COMMAND_W
• spi1::flash_sus_ctrl::FLASH_PER_R
• spi1::flash_sus_ctrl::FLASH_PER_W
• spi1::flash_sus_ctrl::FLASH_PER_WAIT_EN_R
• spi1::flash_sus_ctrl::FLASH_PER_WAIT_EN_W
• spi1::flash_sus_ctrl::FLASH_PES_EN_R
• spi1::flash_sus_ctrl::FLASH_PES_EN_W
• spi1::flash_sus_ctrl::FLASH_PES_R
• spi1::flash_sus_ctrl::FLASH_PES_W
• spi1::flash_sus_ctrl::FLASH_PES_WAIT_EN_R
• spi1::flash_sus_ctrl::FLASH_PES_WAIT_EN_W
• spi1::flash_sus_ctrl::PER_END_EN_R
• spi1::flash_sus_ctrl::PER_END_EN_W
• spi1::flash_sus_ctrl::PESR_END_MSK_R
• spi1::flash_sus_ctrl::PESR_END_MSK_W
• spi1::flash_sus_ctrl::PES_END_EN_R
• spi1::flash_sus_ctrl::PES_END_EN_W
• spi1::flash_sus_ctrl::PES_PER_EN_R
• spi1::flash_sus_ctrl::PES_PER_EN_W
• spi1::flash_sus_ctrl::R
• spi1::flash_sus_ctrl::SPI_FMEM_RD_SUS_2B_R
• spi1::flash_sus_ctrl::SPI_FMEM_RD_SUS_2B_W
• spi1::flash_sus_ctrl::SUS_TIMEOUT_CNT_R
• spi1::flash_sus_ctrl::SUS_TIMEOUT_CNT_W
• spi1::flash_sus_ctrl::W
• spi1::flash_waiti_ctrl::R
• spi1::flash_waiti_ctrl::W
• spi1::flash_waiti_ctrl::WAITI_ADDR_CYCLELEN_R
• spi1::flash_waiti_ctrl::WAITI_ADDR_CYCLELEN_W
• spi1::flash_waiti_ctrl::WAITI_ADDR_EN_R
• spi1::flash_waiti_ctrl::WAITI_ADDR_EN_W
• spi1::flash_waiti_ctrl::WAITI_CMD_2B_R
• spi1::flash_waiti_ctrl::WAITI_CMD_2B_W
• spi1::flash_waiti_ctrl::WAITI_CMD_R
• spi1::flash_waiti_ctrl::WAITI_CMD_W
• spi1::flash_waiti_ctrl::WAITI_DUMMY_CYCLELEN_R
• spi1::flash_waiti_ctrl::WAITI_DUMMY_CYCLELEN_W
• spi1::flash_waiti_ctrl::WAITI_DUMMY_R
• spi1::flash_waiti_ctrl::WAITI_DUMMY_W
• spi1::flash_waiti_ctrl::WAITI_EN_R
• spi1::flash_waiti_ctrl::WAITI_EN_W
• spi1::int_clr::BROWN_OUT_W
• spi1::int_clr::MST_ST_END_W
• spi1::int_clr::PER_END_W
• spi1::int_clr::PES_END_W
• spi1::int_clr::SLV_ST_END_W
• spi1::int_clr::W
• spi1::int_clr::WPE_END_W
• spi1::int_ena::BROWN_OUT_R
• spi1::int_ena::BROWN_OUT_W
• spi1::int_ena::MST_ST_END_R
• spi1::int_ena::MST_ST_END_W
• spi1::int_ena::PER_END_R
• spi1::int_ena::PER_END_W
• spi1::int_ena::PES_END_R
• spi1::int_ena::PES_END_W
• spi1::int_ena::R
• spi1::int_ena::SLV_ST_END_R
• spi1::int_ena::SLV_ST_END_W
• spi1::int_ena::W
• spi1::int_ena::WPE_END_R
• spi1::int_ena::WPE_END_W
• spi1::int_raw::BROWN_OUT_R
• spi1::int_raw::BROWN_OUT_W
• spi1::int_raw::MST_ST_END_R
• spi1::int_raw::MST_ST_END_W
• spi1::int_raw::PER_END_R
• spi1::int_raw::PER_END_W
• spi1::int_raw::PES_END_R
• spi1::int_raw::PES_END_W
• spi1::int_raw::R
• spi1::int_raw::SLV_ST_END_R
• spi1::int_raw::SLV_ST_END_W
• spi1::int_raw::W
• spi1::int_raw::WPE_END_R
• spi1::int_raw::WPE_END_W
• spi1::int_st::BROWN_OUT_R
• spi1::int_st::MST_ST_END_R
• spi1::int_st::PER_END_R
• spi1::int_st::PES_END_R
• spi1::int_st::R
• spi1::int_st::SLV_ST_END_R
• spi1::int_st::WPE_END_R
• spi1::misc::CK_IDLE_EDGE_R
• spi1::misc::CK_IDLE_EDGE_W
• spi1::misc::CS0_DIS_R
• spi1::misc::CS0_DIS_W
• spi1::misc::CS1_DIS_R
• spi1::misc::CS1_DIS_W
• spi1::misc::CS_KEEP_ACTIVE_R
• spi1::misc::CS_KEEP_ACTIVE_W
• spi1::misc::R
• spi1::misc::W
• spi1::miso_dlen::R
• spi1::miso_dlen::USR_MISO_DBITLEN_R
• spi1::miso_dlen::USR_MISO_DBITLEN_W
• spi1::miso_dlen::W
• spi1::mosi_dlen::R
• spi1::mosi_dlen::USR_MOSI_DBITLEN_R
• spi1::mosi_dlen::USR_MOSI_DBITLEN_W
• spi1::mosi_dlen::W
• spi1::rd_status::R
• spi1::rd_status::STATUS_R
• spi1::rd_status::STATUS_W
• spi1::rd_status::W
• spi1::rd_status::WB_MODE_R
• spi1::rd_status::WB_MODE_W
• spi1::sus_status::FLASH_DP_DLY_128_R
• spi1::sus_status::FLASH_DP_DLY_128_W
• spi1::sus_status::FLASH_HPM_DLY_128_R
• spi1::sus_status::FLASH_HPM_DLY_128_W
• spi1::sus_status::FLASH_PER_COMMAND_R
• spi1::sus_status::FLASH_PER_COMMAND_W
• spi1::sus_status::FLASH_PER_DLY_128_R
• spi1::sus_status::FLASH_PER_DLY_128_W
• spi1::sus_status::FLASH_PESR_CMD_2B_R
• spi1::sus_status::FLASH_PESR_CMD_2B_W
• spi1::sus_status::FLASH_PES_DLY_128_R
• spi1::sus_status::FLASH_PES_DLY_128_W
• spi1::sus_status::FLASH_RES_DLY_128_R
• spi1::sus_status::FLASH_RES_DLY_128_W
• spi1::sus_status::FLASH_SUS_R
• spi1::sus_status::FLASH_SUS_W
• spi1::sus_status::R
• spi1::sus_status::SPI0_LOCK_EN_R
• spi1::sus_status::SPI0_LOCK_EN_W
• spi1::sus_status::W
• spi1::sus_status::WAIT_PESR_CMD_2B_R
• spi1::sus_status::WAIT_PESR_CMD_2B_W
• spi1::timing_cali::EXTRA_DUMMY_CYCLELEN_R
• spi1::timing_cali::EXTRA_DUMMY_CYCLELEN_W
• spi1::timing_cali::R
• spi1::timing_cali::TIMING_CALI_R
• spi1::timing_cali::TIMING_CALI_W
• spi1::timing_cali::W
• spi1::tx_crc::DATA_R
• spi1::tx_crc::R
• spi1::user1::R
• spi1::user1::USR_ADDR_BITLEN_R
• spi1::user1::USR_ADDR_BITLEN_W
• spi1::user1::USR_DUMMY_CYCLELEN_R
• spi1::user1::USR_DUMMY_CYCLELEN_W
• spi1::user1::W
• spi1::user2::R
• spi1::user2::USR_COMMAND_BITLEN_R
• spi1::user2::USR_COMMAND_BITLEN_W
• spi1::user2::USR_COMMAND_VALUE_R
• spi1::user2::USR_COMMAND_VALUE_W
• spi1::user2::W
• spi1::user::CK_OUT_EDGE_R
• spi1::user::CK_OUT_EDGE_W
• spi1::user::FWRITE_DIO_R
• spi1::user::FWRITE_DIO_W
• spi1::user::FWRITE_DUAL_R
• spi1::user::FWRITE_DUAL_W
• spi1::user::FWRITE_QIO_R
• spi1::user::FWRITE_QIO_W
• spi1::user::FWRITE_QUAD_R
• spi1::user::FWRITE_QUAD_W
• spi1::user::R
• spi1::user::USR_ADDR_R
• spi1::user::USR_ADDR_W
• spi1::user::USR_COMMAND_R
• spi1::user::USR_COMMAND_W
• spi1::user::USR_DUMMY_IDLE_R
• spi1::user::USR_DUMMY_IDLE_W
• spi1::user::USR_DUMMY_R
• spi1::user::USR_DUMMY_W
• spi1::user::USR_MISO_HIGHPART_R
• spi1::user::USR_MISO_R
• spi1::user::USR_MISO_W
• spi1::user::USR_MOSI_HIGHPART_R
• spi1::user::USR_MOSI_R
• spi1::user::USR_MOSI_W
• spi1::user::W
• spi1::w::BUF_R
• spi1::w::BUF_W
• spi1::w::R
• spi1::w::W
• spi2::ADDR
• spi2::CLK_GATE
• spi2::CLOCK
• spi2::CMD
• spi2::CTRL
• spi2::DATE
• spi2::DIN_MODE
• spi2::DIN_NUM
• spi2::DMA_CONF
• spi2::DMA_INT_CLR
• spi2::DMA_INT_ENA
• spi2::DMA_INT_RAW
• spi2::DMA_INT_SET
• spi2::DMA_INT_ST
• spi2::DOUT_MODE
• spi2::MISC
• spi2::MS_DLEN
• spi2::SLAVE
• spi2::SLAVE1
• spi2::USER
• spi2::USER1
• spi2::USER2
• spi2::W
• spi2::addr::R
• spi2::addr::USR_ADDR_VALUE_R
• spi2::addr::USR_ADDR_VALUE_W
• spi2::addr::W
• spi2::clk_gate::CLK_EN_R
• spi2::clk_gate::CLK_EN_W
• spi2::clk_gate::MST_CLK_ACTIVE_R
• spi2::clk_gate::MST_CLK_ACTIVE_W
• spi2::clk_gate::MST_CLK_SEL_R
• spi2::clk_gate::MST_CLK_SEL_W
• spi2::clk_gate::R
• spi2::clk_gate::W
• spi2::clock::CLKCNT_H_R
• spi2::clock::CLKCNT_H_W
• spi2::clock::CLKCNT_L_R
• spi2::clock::CLKCNT_L_W
• spi2::clock::CLKCNT_N_R
• spi2::clock::CLKCNT_N_W
• spi2::clock::CLKDIV_PRE_R
• spi2::clock::CLKDIV_PRE_W
• spi2::clock::CLK_EQU_SYSCLK_R
• spi2::clock::CLK_EQU_SYSCLK_W
• spi2::clock::R
• spi2::clock::W
• spi2::cmd::CONF_BITLEN_R
• spi2::cmd::CONF_BITLEN_W
• spi2::cmd::R
• spi2::cmd::UPDATE_R
• spi2::cmd::UPDATE_W
• spi2::cmd::USR_R
• spi2::cmd::USR_W
• spi2::cmd::W
• spi2::ctrl::DUMMY_OUT_R
• spi2::ctrl::DUMMY_OUT_W
• spi2::ctrl::D_POL_R
• spi2::ctrl::D_POL_W
• spi2::ctrl::FADDR_DUAL_R
• spi2::ctrl::FADDR_DUAL_W
• spi2::ctrl::FADDR_OCT_R
• spi2::ctrl::FADDR_QUAD_R
• spi2::ctrl::FADDR_QUAD_W
• spi2::ctrl::FCMD_DUAL_R
• spi2::ctrl::FCMD_DUAL_W
• spi2::ctrl::FCMD_OCT_R
• spi2::ctrl::FCMD_QUAD_R
• spi2::ctrl::FCMD_QUAD_W
• spi2::ctrl::FREAD_DUAL_R
• spi2::ctrl::FREAD_DUAL_W
• spi2::ctrl::FREAD_OCT_R
• spi2::ctrl::FREAD_QUAD_R
• spi2::ctrl::FREAD_QUAD_W
• spi2::ctrl::HOLD_POL_R
• spi2::ctrl::HOLD_POL_W
• spi2::ctrl::Q_POL_R
• spi2::ctrl::Q_POL_W
• spi2::ctrl::R
• spi2::ctrl::RD_BIT_ORDER_R
• spi2::ctrl::RD_BIT_ORDER_W
• spi2::ctrl::W
• spi2::ctrl::WP_POL_R
• spi2::ctrl::WP_POL_W
• spi2::ctrl::WR_BIT_ORDER_R
• spi2::ctrl::WR_BIT_ORDER_W
• spi2::date::DATE_R
• spi2::date::DATE_W
• spi2::date::R
• spi2::date::W
• spi2::din_mode::DIN0_MODE_R
• spi2::din_mode::DIN0_MODE_W
• spi2::din_mode::DIN1_MODE_R
• spi2::din_mode::DIN1_MODE_W
• spi2::din_mode::DIN2_MODE_R
• spi2::din_mode::DIN2_MODE_W
• spi2::din_mode::DIN3_MODE_R
• spi2::din_mode::DIN3_MODE_W
• spi2::din_mode::DIN4_MODE_R
• spi2::din_mode::DIN5_MODE_R
• spi2::din_mode::DIN6_MODE_R
• spi2::din_mode::DIN7_MODE_R
• spi2::din_mode::R
• spi2::din_mode::TIMING_HCLK_ACTIVE_R
• spi2::din_mode::TIMING_HCLK_ACTIVE_W
• spi2::din_mode::W
• spi2::din_num::DIN0_NUM_R
• spi2::din_num::DIN0_NUM_W
• spi2::din_num::DIN1_NUM_R
• spi2::din_num::DIN1_NUM_W
• spi2::din_num::DIN2_NUM_R
• spi2::din_num::DIN2_NUM_W
• spi2::din_num::DIN3_NUM_R
• spi2::din_num::DIN3_NUM_W
• spi2::din_num::DIN4_NUM_R
• spi2::din_num::DIN5_NUM_R
• spi2::din_num::DIN6_NUM_R
• spi2::din_num::DIN7_NUM_R
• spi2::din_num::R
• spi2::din_num::W
• spi2::dma_conf::BUF_AFIFO_RST_W
• spi2::dma_conf::DMA_AFIFO_RST_W
• spi2::dma_conf::DMA_INFIFO_FULL_R
• spi2::dma_conf::DMA_OUTFIFO_EMPTY_R
• spi2::dma_conf::DMA_RX_ENA_R
• spi2::dma_conf::DMA_RX_ENA_W
• spi2::dma_conf::DMA_SLV_SEG_TRANS_EN_R
• spi2::dma_conf::DMA_SLV_SEG_TRANS_EN_W
• spi2::dma_conf::DMA_TX_ENA_R
• spi2::dma_conf::DMA_TX_ENA_W
• spi2::dma_conf::R
• spi2::dma_conf::RX_AFIFO_RST_W
• spi2::dma_conf::RX_EOF_EN_R
• spi2::dma_conf::RX_EOF_EN_W
• spi2::dma_conf::SLV_RX_SEG_TRANS_CLR_EN_R
• spi2::dma_conf::SLV_RX_SEG_TRANS_CLR_EN_W
• spi2::dma_conf::SLV_TX_SEG_TRANS_CLR_EN_R
• spi2::dma_conf::SLV_TX_SEG_TRANS_CLR_EN_W
• spi2::dma_conf::W
• spi2::dma_int_clr::APP1_W
• spi2::dma_int_clr::APP2_W
• spi2::dma_int_clr::DMA_INFIFO_FULL_ERR_W
• spi2::dma_int_clr::DMA_OUTFIFO_EMPTY_ERR_W
• spi2::dma_int_clr::DMA_SEG_TRANS_DONE_W
• spi2::dma_int_clr::MST_RX_AFIFO_WFULL_ERR_W
• spi2::dma_int_clr::MST_TX_AFIFO_REMPTY_ERR_W
• spi2::dma_int_clr::SEG_MAGIC_ERR_W
• spi2::dma_int_clr::SLV_BUF_ADDR_ERR_W
• spi2::dma_int_clr::SLV_CMD7_W
• spi2::dma_int_clr::SLV_CMD8_W
• spi2::dma_int_clr::SLV_CMD9_W
• spi2::dma_int_clr::SLV_CMDA_W
• spi2::dma_int_clr::SLV_CMD_ERR_W
• spi2::dma_int_clr::SLV_EN_QPI_W
• spi2::dma_int_clr::SLV_EX_QPI_W
• spi2::dma_int_clr::SLV_RD_BUF_DONE_W
• spi2::dma_int_clr::SLV_RD_DMA_DONE_W
• spi2::dma_int_clr::SLV_WR_BUF_DONE_W
• spi2::dma_int_clr::SLV_WR_DMA_DONE_W
• spi2::dma_int_clr::TRANS_DONE_W
• spi2::dma_int_clr::W
• spi2::dma_int_ena::APP1_R
• spi2::dma_int_ena::APP1_W
• spi2::dma_int_ena::APP2_R
• spi2::dma_int_ena::APP2_W
• spi2::dma_int_ena::DMA_INFIFO_FULL_ERR_R
• spi2::dma_int_ena::DMA_INFIFO_FULL_ERR_W
• spi2::dma_int_ena::DMA_OUTFIFO_EMPTY_ERR_R
• spi2::dma_int_ena::DMA_OUTFIFO_EMPTY_ERR_W
• spi2::dma_int_ena::DMA_SEG_TRANS_DONE_R
• spi2::dma_int_ena::DMA_SEG_TRANS_DONE_W
• spi2::dma_int_ena::MST_RX_AFIFO_WFULL_ERR_R
• spi2::dma_int_ena::MST_RX_AFIFO_WFULL_ERR_W
• spi2::dma_int_ena::MST_TX_AFIFO_REMPTY_ERR_R
• spi2::dma_int_ena::MST_TX_AFIFO_REMPTY_ERR_W
• spi2::dma_int_ena::R
• spi2::dma_int_ena::SEG_MAGIC_ERR_R
• spi2::dma_int_ena::SEG_MAGIC_ERR_W
• spi2::dma_int_ena::SLV_BUF_ADDR_ERR_R
• spi2::dma_int_ena::SLV_BUF_ADDR_ERR_W
• spi2::dma_int_ena::SLV_CMD7_R
• spi2::dma_int_ena::SLV_CMD7_W
• spi2::dma_int_ena::SLV_CMD8_R
• spi2::dma_int_ena::SLV_CMD8_W
• spi2::dma_int_ena::SLV_CMD9_R
• spi2::dma_int_ena::SLV_CMD9_W
• spi2::dma_int_ena::SLV_CMDA_R
• spi2::dma_int_ena::SLV_CMDA_W
• spi2::dma_int_ena::SLV_CMD_ERR_R
• spi2::dma_int_ena::SLV_CMD_ERR_W
• spi2::dma_int_ena::SLV_EN_QPI_R
• spi2::dma_int_ena::SLV_EN_QPI_W
• spi2::dma_int_ena::SLV_EX_QPI_R
• spi2::dma_int_ena::SLV_EX_QPI_W
• spi2::dma_int_ena::SLV_RD_BUF_DONE_R
• spi2::dma_int_ena::SLV_RD_BUF_DONE_W
• spi2::dma_int_ena::SLV_RD_DMA_DONE_R
• spi2::dma_int_ena::SLV_RD_DMA_DONE_W
• spi2::dma_int_ena::SLV_WR_BUF_DONE_R
• spi2::dma_int_ena::SLV_WR_BUF_DONE_W
• spi2::dma_int_ena::SLV_WR_DMA_DONE_R
• spi2::dma_int_ena::SLV_WR_DMA_DONE_W
• spi2::dma_int_ena::TRANS_DONE_R
• spi2::dma_int_ena::TRANS_DONE_W
• spi2::dma_int_ena::W
• spi2::dma_int_raw::APP1_R
• spi2::dma_int_raw::APP1_W
• spi2::dma_int_raw::APP2_R
• spi2::dma_int_raw::APP2_W
• spi2::dma_int_raw::DMA_INFIFO_FULL_ERR_R
• spi2::dma_int_raw::DMA_INFIFO_FULL_ERR_W
• spi2::dma_int_raw::DMA_OUTFIFO_EMPTY_ERR_R
• spi2::dma_int_raw::DMA_OUTFIFO_EMPTY_ERR_W
• spi2::dma_int_raw::DMA_SEG_TRANS_DONE_R
• spi2::dma_int_raw::DMA_SEG_TRANS_DONE_W
• spi2::dma_int_raw::MST_RX_AFIFO_WFULL_ERR_R
• spi2::dma_int_raw::MST_RX_AFIFO_WFULL_ERR_W
• spi2::dma_int_raw::MST_TX_AFIFO_REMPTY_ERR_R
• spi2::dma_int_raw::MST_TX_AFIFO_REMPTY_ERR_W
• spi2::dma_int_raw::R
• spi2::dma_int_raw::SEG_MAGIC_ERR_R
• spi2::dma_int_raw::SEG_MAGIC_ERR_W
• spi2::dma_int_raw::SLV_BUF_ADDR_ERR_R
• spi2::dma_int_raw::SLV_BUF_ADDR_ERR_W
• spi2::dma_int_raw::SLV_CMD7_R
• spi2::dma_int_raw::SLV_CMD7_W
• spi2::dma_int_raw::SLV_CMD8_R
• spi2::dma_int_raw::SLV_CMD8_W
• spi2::dma_int_raw::SLV_CMD9_R
• spi2::dma_int_raw::SLV_CMD9_W
• spi2::dma_int_raw::SLV_CMDA_R
• spi2::dma_int_raw::SLV_CMDA_W
• spi2::dma_int_raw::SLV_CMD_ERR_R
• spi2::dma_int_raw::SLV_CMD_ERR_W
• spi2::dma_int_raw::SLV_EN_QPI_R
• spi2::dma_int_raw::SLV_EN_QPI_W
• spi2::dma_int_raw::SLV_EX_QPI_R
• spi2::dma_int_raw::SLV_EX_QPI_W
• spi2::dma_int_raw::SLV_RD_BUF_DONE_R
• spi2::dma_int_raw::SLV_RD_BUF_DONE_W
• spi2::dma_int_raw::SLV_RD_DMA_DONE_R
• spi2::dma_int_raw::SLV_RD_DMA_DONE_W
• spi2::dma_int_raw::SLV_WR_BUF_DONE_R
• spi2::dma_int_raw::SLV_WR_BUF_DONE_W
• spi2::dma_int_raw::SLV_WR_DMA_DONE_R
• spi2::dma_int_raw::SLV_WR_DMA_DONE_W
• spi2::dma_int_raw::TRANS_DONE_R
• spi2::dma_int_raw::TRANS_DONE_W
• spi2::dma_int_raw::W
• spi2::dma_int_set::APP1_INT_SET_W
• spi2::dma_int_set::APP2_INT_SET_W
• spi2::dma_int_set::DMA_INFIFO_FULL_ERR_INT_SET_W
• spi2::dma_int_set::DMA_OUTFIFO_EMPTY_ERR_INT_SET_W
• spi2::dma_int_set::DMA_SEG_TRANS_DONE_INT_SET_W
• spi2::dma_int_set::MST_RX_AFIFO_WFULL_ERR_INT_SET_W
• spi2::dma_int_set::MST_TX_AFIFO_REMPTY_ERR_INT_SET_W
• spi2::dma_int_set::SEG_MAGIC_ERR_INT_SET_W
• spi2::dma_int_set::SLV_BUF_ADDR_ERR_INT_SET_W
• spi2::dma_int_set::SLV_CMD7_INT_SET_W
• spi2::dma_int_set::SLV_CMD8_INT_SET_W
• spi2::dma_int_set::SLV_CMD9_INT_SET_W
• spi2::dma_int_set::SLV_CMDA_INT_SET_W
• spi2::dma_int_set::SLV_CMD_ERR_INT_SET_W
• spi2::dma_int_set::SLV_EN_QPI_INT_SET_W
• spi2::dma_int_set::SLV_EX_QPI_INT_SET_W
• spi2::dma_int_set::SLV_RD_BUF_DONE_INT_SET_W
• spi2::dma_int_set::SLV_RD_DMA_DONE_INT_SET_W
• spi2::dma_int_set::SLV_WR_BUF_DONE_INT_SET_W
• spi2::dma_int_set::SLV_WR_DMA_DONE_INT_SET_W
• spi2::dma_int_set::TRANS_DONE_INT_SET_W
• spi2::dma_int_set::W
• spi2::dma_int_st::APP1_R
• spi2::dma_int_st::APP2_R
• spi2::dma_int_st::DMA_INFIFO_FULL_ERR_R
• spi2::dma_int_st::DMA_OUTFIFO_EMPTY_ERR_R
• spi2::dma_int_st::DMA_SEG_TRANS_DONE_R
• spi2::dma_int_st::MST_RX_AFIFO_WFULL_ERR_R
• spi2::dma_int_st::MST_TX_AFIFO_REMPTY_ERR_R
• spi2::dma_int_st::R
• spi2::dma_int_st::SEG_MAGIC_ERR_R
• spi2::dma_int_st::SLV_BUF_ADDR_ERR_R
• spi2::dma_int_st::SLV_CMD7_R
• spi2::dma_int_st::SLV_CMD8_R
• spi2::dma_int_st::SLV_CMD9_R
• spi2::dma_int_st::SLV_CMDA_R
• spi2::dma_int_st::SLV_CMD_ERR_R
• spi2::dma_int_st::SLV_EN_QPI_R
• spi2::dma_int_st::SLV_EX_QPI_R
• spi2::dma_int_st::SLV_RD_BUF_DONE_R
• spi2::dma_int_st::SLV_RD_DMA_DONE_R
• spi2::dma_int_st::SLV_WR_BUF_DONE_R
• spi2::dma_int_st::SLV_WR_DMA_DONE_R
• spi2::dma_int_st::TRANS_DONE_R
• spi2::dout_mode::DOUT0_MODE_R
• spi2::dout_mode::DOUT0_MODE_W
• spi2::dout_mode::DOUT1_MODE_R
• spi2::dout_mode::DOUT1_MODE_W
• spi2::dout_mode::DOUT2_MODE_R
• spi2::dout_mode::DOUT2_MODE_W
• spi2::dout_mode::DOUT3_MODE_R
• spi2::dout_mode::DOUT3_MODE_W
• spi2::dout_mode::DOUT4_MODE_R
• spi2::dout_mode::DOUT5_MODE_R
• spi2::dout_mode::DOUT6_MODE_R
• spi2::dout_mode::DOUT7_MODE_R
• spi2::dout_mode::D_DQS_MODE_R
• spi2::dout_mode::R
• spi2::dout_mode::W
• spi2::misc::ADDR_DTR_EN_R
• spi2::misc::CK_DIS_R
• spi2::misc::CK_DIS_W
• spi2::misc::CK_IDLE_EDGE_R
• spi2::misc::CK_IDLE_EDGE_W
• spi2::misc::CLK_DATA_DTR_EN_R
• spi2::misc::CMD_DTR_EN_R
• spi2::misc::CS0_DIS_R
• spi2::misc::CS0_DIS_W
• spi2::misc::CS1_DIS_R
• spi2::misc::CS1_DIS_W
• spi2::misc::CS2_DIS_R
• spi2::misc::CS2_DIS_W
• spi2::misc::CS3_DIS_R
• spi2::misc::CS3_DIS_W
• spi2::misc::CS4_DIS_R
• spi2::misc::CS4_DIS_W
• spi2::misc::CS5_DIS_R
• spi2::misc::CS5_DIS_W
• spi2::misc::CS_KEEP_ACTIVE_R
• spi2::misc::CS_KEEP_ACTIVE_W
• spi2::misc::DATA_DTR_EN_R
• spi2::misc::DQS_IDLE_EDGE_R
• spi2::misc::MASTER_CS_POL_R
• spi2::misc::MASTER_CS_POL_W
• spi2::misc::QUAD_DIN_PIN_SWAP_R
• spi2::misc::QUAD_DIN_PIN_SWAP_W
• spi2::misc::R
• spi2::misc::SLAVE_CS_POL_R
• spi2::misc::SLAVE_CS_POL_W
• spi2::misc::W
• spi2::ms_dlen::MS_DATA_BITLEN_R
• spi2::ms_dlen::MS_DATA_BITLEN_W
• spi2::ms_dlen::R
• spi2::ms_dlen::W
• spi2::slave1::R
• spi2::slave1::SLV_DATA_BITLEN_R
• spi2::slave1::SLV_DATA_BITLEN_W
• spi2::slave1::SLV_LAST_ADDR_R
• spi2::slave1::SLV_LAST_ADDR_W
• spi2::slave1::SLV_LAST_COMMAND_R
• spi2::slave1::SLV_LAST_COMMAND_W
• spi2::slave1::W
• spi2::slave::CLK_MODE_13_R
• spi2::slave::CLK_MODE_13_W
• spi2::slave::CLK_MODE_R
• spi2::slave::CLK_MODE_W
• spi2::slave::DMA_SEG_MAGIC_VALUE_R
• spi2::slave::DMA_SEG_MAGIC_VALUE_W
• spi2::slave::MODE_R
• spi2::slave::MODE_W
• spi2::slave::MST_FD_WAIT_DMA_TX_DATA_R
• spi2::slave::MST_FD_WAIT_DMA_TX_DATA_W
• spi2::slave::R
• spi2::slave::RSCK_DATA_OUT_R
• spi2::slave::RSCK_DATA_OUT_W
• spi2::slave::SLV_RDBUF_BITLEN_EN_R
• spi2::slave::SLV_RDBUF_BITLEN_EN_W
• spi2::slave::SLV_RDDMA_BITLEN_EN_R
• spi2::slave::SLV_RDDMA_BITLEN_EN_W
• spi2::slave::SLV_WRBUF_BITLEN_EN_R
• spi2::slave::SLV_WRBUF_BITLEN_EN_W
• spi2::slave::SLV_WRDMA_BITLEN_EN_R
• spi2::slave::SLV_WRDMA_BITLEN_EN_W
• spi2::slave::SOFT_RESET_W
• spi2::slave::USR_CONF_R
• spi2::slave::USR_CONF_W
• spi2::slave::W
• spi2::user1::CS_HOLD_TIME_R
• spi2::user1::CS_HOLD_TIME_W
• spi2::user1::CS_SETUP_TIME_R
• spi2::user1::CS_SETUP_TIME_W
• spi2::user1::MST_WFULL_ERR_END_EN_R
• spi2::user1::MST_WFULL_ERR_END_EN_W
• spi2::user1::R
• spi2::user1::USR_ADDR_BITLEN_R
• spi2::user1::USR_ADDR_BITLEN_W
• spi2::user1::USR_DUMMY_CYCLELEN_R
• spi2::user1::USR_DUMMY_CYCLELEN_W
• spi2::user1::W
• spi2::user2::MST_REMPTY_ERR_END_EN_R
• spi2::user2::MST_REMPTY_ERR_END_EN_W
• spi2::user2::R
• spi2::user2::USR_COMMAND_BITLEN_R
• spi2::user2::USR_COMMAND_BITLEN_W
• spi2::user2::USR_COMMAND_VALUE_R
• spi2::user2::USR_COMMAND_VALUE_W
• spi2::user2::W
• spi2::user::CK_OUT_EDGE_R
• spi2::user::CK_OUT_EDGE_W
• spi2::user::CS_HOLD_R
• spi2::user::CS_HOLD_W
• spi2::user::CS_SETUP_R
• spi2::user::CS_SETUP_W
• spi2::user::DOUTDIN_R
• spi2::user::DOUTDIN_W
• spi2::user::FWRITE_DUAL_R
• spi2::user::FWRITE_DUAL_W
• spi2::user::FWRITE_OCT_R
• spi2::user::FWRITE_QUAD_R
• spi2::user::FWRITE_QUAD_W
• spi2::user::OPI_MODE_R
• spi2::user::QPI_MODE_R
• spi2::user::QPI_MODE_W
• spi2::user::R
• spi2::user::RSCK_I_EDGE_R
• spi2::user::RSCK_I_EDGE_W
• spi2::user::SIO_R
• spi2::user::SIO_W
• spi2::user::TSCK_I_EDGE_R
• spi2::user::TSCK_I_EDGE_W
• spi2::user::USR_ADDR_R
• spi2::user::USR_ADDR_W
• spi2::user::USR_COMMAND_R
• spi2::user::USR_COMMAND_W
• spi2::user::USR_CONF_NXT_R
• spi2::user::USR_CONF_NXT_W
• spi2::user::USR_DUMMY_IDLE_R
• spi2::user::USR_DUMMY_IDLE_W
• spi2::user::USR_DUMMY_R
• spi2::user::USR_DUMMY_W
• spi2::user::USR_MISO_HIGHPART_R
• spi2::user::USR_MISO_HIGHPART_W
• spi2::user::USR_MISO_R
• spi2::user::USR_MISO_W
• spi2::user::USR_MOSI_HIGHPART_R
• spi2::user::USR_MOSI_HIGHPART_W
• spi2::user::USR_MOSI_R
• spi2::user::USR_MOSI_W
• spi2::user::W
• spi2::w::BUF_R
• spi2::w::BUF_W
• spi2::w::R
• spi2::w::W
• systimer::COMP_LOAD
• systimer::CONF
• systimer::DATE
• systimer::INT_CLR
• systimer::INT_ENA
• systimer::INT_RAW
• systimer::INT_ST
• systimer::TARGET_CONF
• systimer::UNIT_LOAD
• systimer::UNIT_OP
• systimer::comp_load::LOAD_W
• systimer::comp_load::W
• systimer::conf::CLK_EN_R
• systimer::conf::CLK_EN_W
• systimer::conf::ETM_EN_R
• systimer::conf::ETM_EN_W
• systimer::conf::R
• systimer::conf::SYSTIMER_CLK_FO_R
• systimer::conf::SYSTIMER_CLK_FO_W
• systimer::conf::TARGET0_WORK_EN_R
• systimer::conf::TARGET0_WORK_EN_W
• systimer::conf::TARGET1_WORK_EN_R
• systimer::conf::TARGET1_WORK_EN_W
• systimer::conf::TARGET2_WORK_EN_R
• systimer::conf::TARGET2_WORK_EN_W
• systimer::conf::TIMER_UNIT0_CORE0_STALL_EN_R
• systimer::conf::TIMER_UNIT0_CORE0_STALL_EN_W
• systimer::conf::TIMER_UNIT0_CORE1_STALL_EN_R
• systimer::conf::TIMER_UNIT0_CORE1_STALL_EN_W
• systimer::conf::TIMER_UNIT0_WORK_EN_R
• systimer::conf::TIMER_UNIT0_WORK_EN_W
• systimer::conf::TIMER_UNIT1_CORE0_STALL_EN_R
• systimer::conf::TIMER_UNIT1_CORE0_STALL_EN_W
• systimer::conf::TIMER_UNIT1_CORE1_STALL_EN_R
• systimer::conf::TIMER_UNIT1_CORE1_STALL_EN_W
• systimer::conf::TIMER_UNIT1_WORK_EN_R
• systimer::conf::TIMER_UNIT1_WORK_EN_W
• systimer::conf::W
• systimer::date::DATE_R
• systimer::date::DATE_W
• systimer::date::R
• systimer::date::W
• systimer::int_clr::TARGET_W
• systimer::int_clr::W
• systimer::int_ena::R
• systimer::int_ena::TARGET_R
• systimer::int_ena::TARGET_W
• systimer::int_ena::W
• systimer::int_raw::R
• systimer::int_raw::TARGET_R
• systimer::int_raw::TARGET_W
• systimer::int_raw::W
• systimer::int_st::R
• systimer::int_st::TARGET_R
• systimer::real_target::HI
• systimer::real_target::LO
• systimer::real_target::hi::HI_RO_R
• systimer::real_target::hi::R
• systimer::real_target::lo::LO_RO_R
• systimer::real_target::lo::R
• systimer::target_conf::PERIOD_MODE_R
• systimer::target_conf::PERIOD_MODE_W
• systimer::target_conf::PERIOD_R
• systimer::target_conf::PERIOD_W
• systimer::target_conf::R
• systimer::target_conf::TIMER_UNIT_SEL_R
• systimer::target_conf::TIMER_UNIT_SEL_W
• systimer::target_conf::W
• systimer::trgt::HI
• systimer::trgt::LO
• systimer::trgt::hi::HI_R
• systimer::trgt::hi::HI_W
• systimer::trgt::hi::R
• systimer::trgt::hi::W
• systimer::trgt::lo::LO_R
• systimer::trgt::lo::LO_W
• systimer::trgt::lo::R
• systimer::trgt::lo::W
• systimer::unit_load::LOAD_W
• systimer::unit_load::W
• systimer::unit_op::R
• systimer::unit_op::UPDATE_W
• systimer::unit_op::VALUE_VALID_R
• systimer::unit_op::W
• systimer::unit_value::HI
• systimer::unit_value::LO
• systimer::unit_value::hi::R
• systimer::unit_value::hi::VALUE_HI_R
• systimer::unit_value::lo::R
• systimer::unit_value::lo::VALUE_LO_R
• systimer::unitload::HI
• systimer::unitload::LO
• systimer::unitload::hi::LOAD_HI_R
• systimer::unitload::hi::LOAD_HI_W
• systimer::unitload::hi::R
• systimer::unitload::hi::W
• systimer::unitload::lo::LOAD_LO_R
• systimer::unitload::lo::LOAD_LO_W
• systimer::unitload::lo::R
• systimer::unitload::lo::W
• tee::CLOCK_GATE
• tee::DATE
• tee::M_MODE_CTRL
• tee::clock_gate::CLK_EN_R
• tee::clock_gate::CLK_EN_W
• tee::clock_gate::R
• tee::clock_gate::W
• tee::date::DATE_R
• tee::date::DATE_W
• tee::date::R
• tee::date::W
• tee::m_mode_ctrl::MODE_R
• tee::m_mode_ctrl::MODE_W
• tee::m_mode_ctrl::R
• tee::m_mode_ctrl::W
• timg0::INT_CLR
• timg0::INT_ENA
• timg0::INT_RAW
• timg0::INT_ST
• timg0::NTIMERS_DATE
• timg0::REGCLK
• timg0::RTCCALICFG
• timg0::RTCCALICFG1
• timg0::RTCCALICFG2
• timg0::WDTCONFIG0
• timg0::WDTCONFIG1
• timg0::WDTCONFIG2
• timg0::WDTCONFIG3
• timg0::WDTCONFIG4
• timg0::WDTCONFIG5
• timg0::WDTFEED
• timg0::WDTWPROTECT
• timg0::int_clr::T_W
• timg0::int_clr::W
• timg0::int_clr::WDT_W
• timg0::int_ena::R
• timg0::int_ena::T_R
• timg0::int_ena::T_W
• timg0::int_ena::W
• timg0::int_ena::WDT_R
• timg0::int_ena::WDT_W
• timg0::int_raw::R
• timg0::int_raw::T_R
• timg0::int_raw::WDT_R
• timg0::int_st::R
• timg0::int_st::T_R
• timg0::int_st::WDT_R
• timg0::ntimers_date::NTIMGS_DATE_R
• timg0::ntimers_date::NTIMGS_DATE_W
• timg0::ntimers_date::R
• timg0::ntimers_date::W
• timg0::regclk::CLK_EN_R
• timg0::regclk::CLK_EN_W
• timg0::regclk::ETM_EN_R
• timg0::regclk::ETM_EN_W
• timg0::regclk::R
• timg0::regclk::TIMER_CLK_IS_ACTIVE_R
• timg0::regclk::TIMER_CLK_IS_ACTIVE_W
• timg0::regclk::W
• timg0::regclk::WDT_CLK_IS_ACTIVE_R
• timg0::regclk::WDT_CLK_IS_ACTIVE_W
• timg0::rtccalicfg1::R
• timg0::rtccalicfg1::RTC_CALI_CYCLING_DATA_VLD_R
• timg0::rtccalicfg1::RTC_CALI_VALUE_R
• timg0::rtccalicfg2::R
• timg0::rtccalicfg2::RTC_CALI_TIMEOUT_R
• timg0::rtccalicfg2::RTC_CALI_TIMEOUT_RST_CNT_R
• timg0::rtccalicfg2::RTC_CALI_TIMEOUT_RST_CNT_W
• timg0::rtccalicfg2::RTC_CALI_TIMEOUT_THRES_R
• timg0::rtccalicfg2::RTC_CALI_TIMEOUT_THRES_W
• timg0::rtccalicfg2::W
• timg0::rtccalicfg::R
• timg0::rtccalicfg::RTC_CALI_CLK_SEL_R
• timg0::rtccalicfg::RTC_CALI_CLK_SEL_W
• timg0::rtccalicfg::RTC_CALI_MAX_R
• timg0::rtccalicfg::RTC_CALI_MAX_W
• timg0::rtccalicfg::RTC_CALI_RDY_R
• timg0::rtccalicfg::RTC_CALI_START_CYCLING_R
• timg0::rtccalicfg::RTC_CALI_START_CYCLING_W
• timg0::rtccalicfg::RTC_CALI_START_R
• timg0::rtccalicfg::RTC_CALI_START_W
• timg0::rtccalicfg::W
• timg0::t::ALARMHI
• timg0::t::ALARMLO
• timg0::t::CONFIG
• timg0::t::HI
• timg0::t::LO
• timg0::t::LOAD
• timg0::t::LOADHI
• timg0::t::LOADLO
• timg0::t::UPDATE
• timg0::t::alarmhi::ALARM_HI_R
• timg0::t::alarmhi::ALARM_HI_W
• timg0::t::alarmhi::R
• timg0::t::alarmhi::W
• timg0::t::alarmlo::ALARM_LO_R
• timg0::t::alarmlo::ALARM_LO_W
• timg0::t::alarmlo::R
• timg0::t::alarmlo::W
• timg0::t::config::ALARM_EN_R
• timg0::t::config::ALARM_EN_W
• timg0::t::config::AUTORELOAD_R
• timg0::t::config::AUTORELOAD_W
• timg0::t::config::DIVCNT_RST_W
• timg0::t::config::DIVIDER_R
• timg0::t::config::DIVIDER_W
• timg0::t::config::EN_R
• timg0::t::config::EN_W
• timg0::t::config::INCREASE_R
• timg0::t::config::INCREASE_W
• timg0::t::config::R
• timg0::t::config::USE_XTAL_R
• timg0::t::config::USE_XTAL_W
• timg0::t::config::W
• timg0::t::hi::HI_R
• timg0::t::hi::R
• timg0::t::lo::LO_R
• timg0::t::lo::R
• timg0::t::load::LOAD_W
• timg0::t::load::W
• timg0::t::loadhi::LOAD_HI_R
• timg0::t::loadhi::LOAD_HI_W
• timg0::t::loadhi::R
• timg0::t::loadhi::W
• timg0::t::loadlo::LOAD_LO_R
• timg0::t::loadlo::LOAD_LO_W
• timg0::t::loadlo::R
• timg0::t::loadlo::W
• timg0::t::update::R
• timg0::t::update::UPDATE_R
• timg0::t::update::UPDATE_W
• timg0::t::update::W
• timg0::wdtconfig0::R
• timg0::wdtconfig0::W
• timg0::wdtconfig0::WDT_APPCPU_RESET_EN_R
• timg0::wdtconfig0::WDT_APPCPU_RESET_EN_W
• timg0::wdtconfig0::WDT_CONF_UPDATE_EN_W
• timg0::wdtconfig0::WDT_CPU_RESET_LENGTH_R
• timg0::wdtconfig0::WDT_CPU_RESET_LENGTH_W
• timg0::wdtconfig0::WDT_EN_R
• timg0::wdtconfig0::WDT_EN_W
• timg0::wdtconfig0::WDT_FLASHBOOT_MOD_EN_R
• timg0::wdtconfig0::WDT_FLASHBOOT_MOD_EN_W
• timg0::wdtconfig0::WDT_PROCPU_RESET_EN_R
• timg0::wdtconfig0::WDT_PROCPU_RESET_EN_W
• timg0::wdtconfig0::WDT_STG0_R
• timg0::wdtconfig0::WDT_STG0_W
• timg0::wdtconfig0::WDT_STG1_R
• timg0::wdtconfig0::WDT_STG1_W
• timg0::wdtconfig0::WDT_STG2_R
• timg0::wdtconfig0::WDT_STG2_W
• timg0::wdtconfig0::WDT_STG3_R
• timg0::wdtconfig0::WDT_STG3_W
• timg0::wdtconfig0::WDT_SYS_RESET_LENGTH_R
• timg0::wdtconfig0::WDT_SYS_RESET_LENGTH_W
• timg0::wdtconfig0::WDT_USE_XTAL_R
• timg0::wdtconfig0::WDT_USE_XTAL_W
• timg0::wdtconfig1::R
• timg0::wdtconfig1::W
• timg0::wdtconfig1::WDT_CLK_PRESCALE_R
• timg0::wdtconfig1::WDT_CLK_PRESCALE_W
• timg0::wdtconfig1::WDT_DIVCNT_RST_W
• timg0::wdtconfig2::R
• timg0::wdtconfig2::W
• timg0::wdtconfig2::WDT_STG0_HOLD_R
• timg0::wdtconfig2::WDT_STG0_HOLD_W
• timg0::wdtconfig3::R
• timg0::wdtconfig3::W
• timg0::wdtconfig3::WDT_STG1_HOLD_R
• timg0::wdtconfig3::WDT_STG1_HOLD_W
• timg0::wdtconfig4::R
• timg0::wdtconfig4::W
• timg0::wdtconfig4::WDT_STG2_HOLD_R
• timg0::wdtconfig4::WDT_STG2_HOLD_W
• timg0::wdtconfig5::R
• timg0::wdtconfig5::W
• timg0::wdtconfig5::WDT_STG3_HOLD_R
• timg0::wdtconfig5::WDT_STG3_HOLD_W
• timg0::wdtfeed::W
• timg0::wdtfeed::WDT_FEED_W
• timg0::wdtwprotect::R
• timg0::wdtwprotect::W
• timg0::wdtwprotect::WDT_WKEY_R
• timg0::wdtwprotect::WDT_WKEY_W
• trace::CLOCK_GATE
• trace::DATE
• trace::FIFO_STATUS
• trace::INTR_CLR
• trace::INTR_ENA
• trace::INTR_RAW
• trace::MEM_ADDR_UPDATE
• trace::MEM_CURRENT_ADDR
• trace::MEM_END_ADDR
• trace::MEM_START_ADDR
• trace::RESYNC_PROLONGED
• trace::TRIGGER
• trace::clock_gate::CLK_EN_R
• trace::clock_gate::CLK_EN_W
• trace::clock_gate::R
• trace::clock_gate::W
• trace::date::DATE_R
• trace::date::DATE_W
• trace::date::R
• trace::date::W
• trace::fifo_status::FIFO_EMPTY_R
• trace::fifo_status::R
• trace::fifo_status::WORK_STATUS_R
• trace::intr_clr::FIFO_OVERFLOW_INTR_CLR_W
• trace::intr_clr::MEM_FULL_INTR_CLR_W
• trace::intr_clr::W
• trace::intr_ena::FIFO_OVERFLOW_INTR_ENA_R
• trace::intr_ena::FIFO_OVERFLOW_INTR_ENA_W
• trace::intr_ena::MEM_FULL_INTR_ENA_R
• trace::intr_ena::MEM_FULL_INTR_ENA_W
• trace::intr_ena::R
• trace::intr_ena::W
• trace::intr_raw::FIFO_OVERFLOW_INTR_RAW_R
• trace::intr_raw::MEM_FULL_INTR_RAW_R
• trace::intr_raw::R
• trace::mem_addr_update::MEM_CURRENT_ADDR_UPDATE_W
• trace::mem_addr_update::W
• trace::mem_current_addr::MEM_CURRENT_ADDR_R
• trace::mem_current_addr::R
• trace::mem_end_addr::MEM_END_ADDR_R
• trace::mem_end_addr::MEM_END_ADDR_W
• trace::mem_end_addr::R
• trace::mem_end_addr::W
• trace::mem_start_addr::MEM_START_ADDR_R
• trace::mem_start_addr::MEM_START_ADDR_W
• trace::mem_start_addr::R
• trace::mem_start_addr::W
• trace::resync_prolonged::R
• trace::resync_prolonged::RESYNC_MODE_R
• trace::resync_prolonged::RESYNC_MODE_W
• trace::resync_prolonged::RESYNC_PROLONGED_R
• trace::resync_prolonged::RESYNC_PROLONGED_W
• trace::resync_prolonged::W
• trace::trigger::MEM_LOOP_R
• trace::trigger::MEM_LOOP_W
• trace::trigger::OFF_W
• trace::trigger::ON_W
• trace::trigger::R
• trace::trigger::RESTART_ENA_R
• trace::trigger::RESTART_ENA_W
• trace::trigger::W
• twai0::ARB_LOST_CAP
• twai0::BUS_TIMING_0
• twai0::BUS_TIMING_1
• twai0::CLOCK_DIVIDER
• twai0::CMD
• twai0::DATA_0
• twai0::DATA_1
• twai0::DATA_10
• twai0::DATA_11
• twai0::DATA_12
• twai0::DATA_2
• twai0::DATA_3
• twai0::DATA_4
• twai0::DATA_5
• twai0::DATA_6
• twai0::DATA_7
• twai0::DATA_8
• twai0::DATA_9
• twai0::ECO_CFG
• twai0::ERR_CODE_CAP
• twai0::ERR_WARNING_LIMIT
• twai0::HW_CFG
• twai0::HW_STANDBY_CNT
• twai0::IDLE_INTR_CNT
• twai0::INTERRUPT
• twai0::INTERRUPT_ENABLE
• twai0::MODE
• twai0::RX_ERR_CNT
• twai0::RX_MESSAGE_CNT
• twai0::STATUS
• twai0::SW_STANDBY_CFG
• twai0::TX_ERR_CNT
• twai0::arb_lost_cap::ARBITRATION_LOST_CAPTURE_R
• twai0::arb_lost_cap::R
• twai0::bus_timing_0::BAUD_PRESC_R
• twai0::bus_timing_0::BAUD_PRESC_W
• twai0::bus_timing_0::R
• twai0::bus_timing_0::SYNC_JUMP_WIDTH_R
• twai0::bus_timing_0::SYNC_JUMP_WIDTH_W
• twai0::bus_timing_0::W
• twai0::bus_timing_1::R
• twai0::bus_timing_1::TIME_SAMP_R
• twai0::bus_timing_1::TIME_SAMP_W
• twai0::bus_timing_1::TIME_SEG1_R
• twai0::bus_timing_1::TIME_SEG1_W
• twai0::bus_timing_1::TIME_SEG2_R
• twai0::bus_timing_1::TIME_SEG2_W
• twai0::bus_timing_1::W
• twai0::clock_divider::CD_R
• twai0::clock_divider::CD_W
• twai0::clock_divider::CLOCK_OFF_R
• twai0::clock_divider::CLOCK_OFF_W
• twai0::clock_divider::R
• twai0::clock_divider::W
• twai0::cmd::ABORT_TX_W
• twai0::cmd::CLEAR_DATA_OVERRUN_W
• twai0::cmd::RELEASE_BUF_W
• twai0::cmd::SELF_RX_REQ_W
• twai0::cmd::TX_REQ_W
• twai0::cmd::W
• twai0::data_0::R
• twai0::data_0::TX_BYTE_0_R
• twai0::data_0::TX_BYTE_0_W
• twai0::data_0::W
• twai0::data_10::R
• twai0::data_10::TX_BYTE_10_R
• twai0::data_10::TX_BYTE_10_W
• twai0::data_10::W
• twai0::data_11::R
• twai0::data_11::TX_BYTE_11_R
• twai0::data_11::TX_BYTE_11_W
• twai0::data_11::W
• twai0::data_12::R
• twai0::data_12::TX_BYTE_12_R
• twai0::data_12::TX_BYTE_12_W
• twai0::data_12::W
• twai0::data_1::R
• twai0::data_1::TX_BYTE_1_R
• twai0::data_1::TX_BYTE_1_W
• twai0::data_1::W
• twai0::data_2::R
• twai0::data_2::TX_BYTE_2_R
• twai0::data_2::TX_BYTE_2_W
• twai0::data_2::W
• twai0::data_3::R
• twai0::data_3::TX_BYTE_3_R
• twai0::data_3::TX_BYTE_3_W
• twai0::data_3::W
• twai0::data_4::R
• twai0::data_4::TX_BYTE_4_R
• twai0::data_4::TX_BYTE_4_W
• twai0::data_4::W
• twai0::data_5::R
• twai0::data_5::TX_BYTE_5_R
• twai0::data_5::TX_BYTE_5_W
• twai0::data_5::W
• twai0::data_6::R
• twai0::data_6::TX_BYTE_6_R
• twai0::data_6::TX_BYTE_6_W
• twai0::data_6::W
• twai0::data_7::R
• twai0::data_7::TX_BYTE_7_R
• twai0::data_7::TX_BYTE_7_W
• twai0::data_7::W
• twai0::data_8::R
• twai0::data_8::TX_BYTE_8_R
• twai0::data_8::TX_BYTE_8_W
• twai0::data_8::W
• twai0::data_9::DATA_9_R
• twai0::data_9::DATA_9_W
• twai0::data_9::R
• twai0::data_9::W
• twai0::eco_cfg::R
• twai0::eco_cfg::RDN_ENA_R
• twai0::eco_cfg::RDN_ENA_W
• twai0::eco_cfg::RDN_RESULT_R
• twai0::eco_cfg::W
• twai0::err_code_cap::ECC_DIRECTION_R
• twai0::err_code_cap::ERR_CAPTURE_CODE_SEGMENT_R
• twai0::err_code_cap::ERR_CAPTURE_CODE_TYPE_R
• twai0::err_code_cap::R
• twai0::err_warning_limit::ERR_WARNING_LIMIT_R
• twai0::err_warning_limit::ERR_WARNING_LIMIT_W
• twai0::err_warning_limit::R
• twai0::err_warning_limit::W
• twai0::hw_cfg::HW_STANDBY_EN_R
• twai0::hw_cfg::HW_STANDBY_EN_W
• twai0::hw_cfg::R
• twai0::hw_cfg::W
• twai0::hw_standby_cnt::R
• twai0::hw_standby_cnt::STANDBY_WAIT_CNT_R
• twai0::hw_standby_cnt::STANDBY_WAIT_CNT_W
• twai0::hw_standby_cnt::W
• twai0::idle_intr_cnt::IDLE_INTR_CNT_R
• twai0::idle_intr_cnt::IDLE_INTR_CNT_W
• twai0::idle_intr_cnt::R
• twai0::idle_intr_cnt::W
• twai0::interrupt::ARBITRATION_LOST_INT_ST_R
• twai0::interrupt::BUS_ERR_INT_ST_R
• twai0::interrupt::DATA_OVERRUN_INT_ST_R
• twai0::interrupt::ERR_PASSIVE_INT_ST_R
• twai0::interrupt::ERR_WARNING_INT_ST_R
• twai0::interrupt::IDLE_INT_ST_R
• twai0::interrupt::R
• twai0::interrupt::RECEIVE_INT_ST_R
• twai0::interrupt::TRANSMIT_INT_ST_R
• twai0::interrupt_enable::ARBITRATION_LOST_INT_ENA_R
• twai0::interrupt_enable::ARBITRATION_LOST_INT_ENA_W
• twai0::interrupt_enable::BUS_ERR_INT_ENA_R
• twai0::interrupt_enable::BUS_ERR_INT_ENA_W
• twai0::interrupt_enable::ERR_PASSIVE_INT_ENA_R
• twai0::interrupt_enable::ERR_PASSIVE_INT_ENA_W
• twai0::interrupt_enable::EXT_DATA_OVERRUN_INT_ENA_R
• twai0::interrupt_enable::EXT_DATA_OVERRUN_INT_ENA_W
• twai0::interrupt_enable::EXT_ERR_WARNING_INT_ENA_R
• twai0::interrupt_enable::EXT_ERR_WARNING_INT_ENA_W
• twai0::interrupt_enable::EXT_RECEIVE_INT_ENA_R
• twai0::interrupt_enable::EXT_RECEIVE_INT_ENA_W
• twai0::interrupt_enable::EXT_TRANSMIT_INT_ENA_R
• twai0::interrupt_enable::EXT_TRANSMIT_INT_ENA_W
• twai0::interrupt_enable::IDLE_INT_ENA_R
• twai0::interrupt_enable::R
• twai0::interrupt_enable::W
• twai0::mode::LISTEN_ONLY_MODE_R
• twai0::mode::LISTEN_ONLY_MODE_W
• twai0::mode::R
• twai0::mode::RESET_MODE_R
• twai0::mode::RESET_MODE_W
• twai0::mode::RX_FILTER_MODE_R
• twai0::mode::RX_FILTER_MODE_W
• twai0::mode::SELF_TEST_MODE_R
• twai0::mode::SELF_TEST_MODE_W
• twai0::mode::W
• twai0::rx_err_cnt::R
• twai0::rx_err_cnt::RX_ERR_CNT_R
• twai0::rx_err_cnt::RX_ERR_CNT_W
• twai0::rx_err_cnt::W
• twai0::rx_message_cnt::R
• twai0::rx_message_cnt::RX_MESSAGE_COUNTER_R
• twai0::status::BUS_OFF_ST_R
• twai0::status::ERR_R
• twai0::status::MISS_ST_R
• twai0::status::OVERRUN_R
• twai0::status::R
• twai0::status::RECEIVE_R
• twai0::status::RX_BUF_ST_R
• twai0::status::TRANSMISSION_COMPLETE_R
• twai0::status::TRANSMIT_R
• twai0::status::TX_BUF_ST_R
• twai0::sw_standby_cfg::R
• twai0::sw_standby_cfg::SW_STANDBY_CLR_R
• twai0::sw_standby_cfg::SW_STANDBY_CLR_W
• twai0::sw_standby_cfg::SW_STANDBY_EN_R
• twai0::sw_standby_cfg::SW_STANDBY_EN_W
• twai0::sw_standby_cfg::W
• twai0::tx_err_cnt::R
• twai0::tx_err_cnt::TX_ERR_CNT_R
• twai0::tx_err_cnt::TX_ERR_CNT_W
• twai0::tx_err_cnt::W
• uart0::AFIFO_STATUS
• uart0::AT_CMD_CHAR
• uart0::AT_CMD_GAPTOUT
• uart0::AT_CMD_POSTCNT
• uart0::AT_CMD_PRECNT
• uart0::CLKDIV
• uart0::CLK_CONF
• uart0::CONF0
• uart0::CONF1
• uart0::DATE
• uart0::FIFO
• uart0::FSM_STATUS
• uart0::HIGHPULSE
• uart0::HWFC_CONF
• uart0::ID
• uart0::IDLE_CONF
• uart0::INT_CLR
• uart0::INT_ENA
• uart0::INT_RAW
• uart0::INT_ST
• uart0::LOWPULSE
• uart0::MEM_CONF
• uart0::MEM_RX_STATUS
• uart0::MEM_TX_STATUS
• uart0::NEGPULSE
• uart0::POSPULSE
• uart0::REG_UPDATE
• uart0::RS485_CONF
• uart0::RXD_CNT
• uart0::RX_FILT
• uart0::SLEEP_CONF0
• uart0::SLEEP_CONF1
• uart0::SLEEP_CONF2
• uart0::STATUS
• uart0::SWFC_CONF0
• uart0::SWFC_CONF1
• uart0::TOUT_CONF
• uart0::TXBRK_CONF
• uart0::afifo_status::R
• uart0::afifo_status::RX_AFIFO_EMPTY_R
• uart0::afifo_status::RX_AFIFO_FULL_R
• uart0::afifo_status::TX_AFIFO_EMPTY_R
• uart0::afifo_status::TX_AFIFO_FULL_R
• uart0::at_cmd_char::AT_CMD_CHAR_R
• uart0::at_cmd_char::AT_CMD_CHAR_W
• uart0::at_cmd_char::CHAR_NUM_R
• uart0::at_cmd_char::CHAR_NUM_W
• uart0::at_cmd_char::R
• uart0::at_cmd_char::W
• uart0::at_cmd_gaptout::R
• uart0::at_cmd_gaptout::RX_GAP_TOUT_R
• uart0::at_cmd_gaptout::RX_GAP_TOUT_W
• uart0::at_cmd_gaptout::W
• uart0::at_cmd_postcnt::POST_IDLE_NUM_R
• uart0::at_cmd_postcnt::POST_IDLE_NUM_W
• uart0::at_cmd_postcnt::R
• uart0::at_cmd_postcnt::W
• uart0::at_cmd_precnt::PRE_IDLE_NUM_R
• uart0::at_cmd_precnt::PRE_IDLE_NUM_W
• uart0::at_cmd_precnt::R
• uart0::at_cmd_precnt::W
• uart0::clk_conf::R
• uart0::clk_conf::RST_CORE_R
• uart0::clk_conf::RST_CORE_W
• uart0::clk_conf::RX_RST_CORE_R
• uart0::clk_conf::RX_RST_CORE_W
• uart0::clk_conf::RX_SCLK_EN_R
• uart0::clk_conf::RX_SCLK_EN_W
• uart0::clk_conf::SCLK_DIV_A_R
• uart0::clk_conf::SCLK_DIV_A_W
• uart0::clk_conf::SCLK_DIV_B_R
• uart0::clk_conf::SCLK_DIV_B_W
• uart0::clk_conf::SCLK_DIV_NUM_R
• uart0::clk_conf::SCLK_DIV_NUM_W
• uart0::clk_conf::SCLK_EN_R
• uart0::clk_conf::SCLK_EN_W
• uart0::clk_conf::SCLK_SEL_R
• uart0::clk_conf::SCLK_SEL_W
• uart0::clk_conf::TX_RST_CORE_R
• uart0::clk_conf::TX_RST_CORE_W
• uart0::clk_conf::TX_SCLK_EN_R
• uart0::clk_conf::TX_SCLK_EN_W
• uart0::clk_conf::W
• uart0::clkdiv::CLKDIV_R
• uart0::clkdiv::CLKDIV_W
• uart0::clkdiv::FRAG_R
• uart0::clkdiv::FRAG_W
• uart0::clkdiv::R
• uart0::clkdiv::W
• uart0::conf0::AUTOBAUD_EN_R
• uart0::conf0::AUTOBAUD_EN_W
• uart0::conf0::BIT_NUM_R
• uart0::conf0::BIT_NUM_W
• uart0::conf0::DIS_RX_DAT_OVF_R
• uart0::conf0::DIS_RX_DAT_OVF_W
• uart0::conf0::ERR_WR_MASK_R
• uart0::conf0::ERR_WR_MASK_W
• uart0::conf0::IRDA_DPLX_R
• uart0::conf0::IRDA_DPLX_W
• uart0::conf0::IRDA_EN_R
• uart0::conf0::IRDA_EN_W
• uart0::conf0::IRDA_RX_INV_R
• uart0::conf0::IRDA_RX_INV_W
• uart0::conf0::IRDA_TX_EN_R
• uart0::conf0::IRDA_TX_EN_W
• uart0::conf0::IRDA_TX_INV_R
• uart0::conf0::IRDA_TX_INV_W
• uart0::conf0::IRDA_WCTL_R
• uart0::conf0::IRDA_WCTL_W
• uart0::conf0::LOOPBACK_R
• uart0::conf0::LOOPBACK_W
• uart0::conf0::MEM_CLK_EN_R
• uart0::conf0::MEM_CLK_EN_W
• uart0::conf0::PARITY_EN_R
• uart0::conf0::PARITY_EN_W
• uart0::conf0::PARITY_R
• uart0::conf0::PARITY_W
• uart0::conf0::R
• uart0::conf0::RXD_INV_R
• uart0::conf0::RXD_INV_W
• uart0::conf0::RXFIFO_RST_R
• uart0::conf0::RXFIFO_RST_W
• uart0::conf0::STOP_BIT_NUM_R
• uart0::conf0::STOP_BIT_NUM_W
• uart0::conf0::SW_RTS_R
• uart0::conf0::SW_RTS_W
• uart0::conf0::TXD_BRK_R
• uart0::conf0::TXD_BRK_W
• uart0::conf0::TXD_INV_R
• uart0::conf0::TXD_INV_W
• uart0::conf0::TXFIFO_RST_R
• uart0::conf0::TXFIFO_RST_W
• uart0::conf0::TX_FLOW_EN_R
• uart0::conf0::TX_FLOW_EN_W
• uart0::conf0::W
• uart0::conf1::CLK_EN_R
• uart0::conf1::CLK_EN_W
• uart0::conf1::CTS_INV_R
• uart0::conf1::CTS_INV_W
• uart0::conf1::DSR_INV_R
• uart0::conf1::DSR_INV_W
• uart0::conf1::DTR_INV_R
• uart0::conf1::DTR_INV_W
• uart0::conf1::R
• uart0::conf1::RTS_INV_R
• uart0::conf1::RTS_INV_W
• uart0::conf1::RXFIFO_FULL_THRHD_R
• uart0::conf1::RXFIFO_FULL_THRHD_W
• uart0::conf1::SW_DTR_R
• uart0::conf1::SW_DTR_W
• uart0::conf1::TXFIFO_EMPTY_THRHD_R
• uart0::conf1::TXFIFO_EMPTY_THRHD_W
• uart0::conf1::W
• uart0::date::DATE_R
• uart0::date::DATE_W
• uart0::date::R
• uart0::date::W
• uart0::fifo::R
• uart0::fifo::RXFIFO_RD_BYTE_R
• uart0::fifo::RXFIFO_RD_BYTE_W
• uart0::fifo::W
• uart0::fsm_status::R
• uart0::fsm_status::ST_URX_OUT_R
• uart0::fsm_status::ST_UTX_OUT_R
• uart0::highpulse::MIN_CNT_R
• uart0::highpulse::R
• uart0::hwfc_conf::R
• uart0::hwfc_conf::RX_FLOW_EN_R
• uart0::hwfc_conf::RX_FLOW_EN_W
• uart0::hwfc_conf::RX_FLOW_THRHD_R
• uart0::hwfc_conf::RX_FLOW_THRHD_W
• uart0::hwfc_conf::W
• uart0::id::ID_R
• uart0::id::ID_W
• uart0::id::R
• uart0::id::W
• uart0::idle_conf::R
• uart0::idle_conf::RX_IDLE_THRHD_R
• uart0::idle_conf::RX_IDLE_THRHD_W
• uart0::idle_conf::TX_IDLE_NUM_R
• uart0::idle_conf::TX_IDLE_NUM_W
• uart0::idle_conf::W
• uart0::int_clr::AT_CMD_CHAR_DET_W
• uart0::int_clr::BRK_DET_W
• uart0::int_clr::CTS_CHG_W
• uart0::int_clr::DSR_CHG_W
• uart0::int_clr::FRM_ERR_W
• uart0::int_clr::GLITCH_DET_W
• uart0::int_clr::PARITY_ERR_W
• uart0::int_clr::RS485_CLASH_W
• uart0::int_clr::RS485_FRM_ERR_W
• uart0::int_clr::RS485_PARITY_ERR_W
• uart0::int_clr::RXFIFO_FULL_W
• uart0::int_clr::RXFIFO_OVF_W
• uart0::int_clr::RXFIFO_TOUT_W
• uart0::int_clr::SW_XOFF_W
• uart0::int_clr::SW_XON_W
• uart0::int_clr::TXFIFO_EMPTY_W
• uart0::int_clr::TX_BRK_DONE_W
• uart0::int_clr::TX_BRK_IDLE_DONE_W
• uart0::int_clr::TX_DONE_W
• uart0::int_clr::W
• uart0::int_clr::WAKEUP_W
• uart0::int_ena::AT_CMD_CHAR_DET_R
• uart0::int_ena::AT_CMD_CHAR_DET_W
• uart0::int_ena::BRK_DET_R
• uart0::int_ena::BRK_DET_W
• uart0::int_ena::CTS_CHG_R
• uart0::int_ena::CTS_CHG_W
• uart0::int_ena::DSR_CHG_R
• uart0::int_ena::DSR_CHG_W
• uart0::int_ena::FRM_ERR_R
• uart0::int_ena::FRM_ERR_W
• uart0::int_ena::GLITCH_DET_R
• uart0::int_ena::GLITCH_DET_W
• uart0::int_ena::PARITY_ERR_R
• uart0::int_ena::PARITY_ERR_W
• uart0::int_ena::R
• uart0::int_ena::RS485_CLASH_R
• uart0::int_ena::RS485_CLASH_W
• uart0::int_ena::RS485_FRM_ERR_R
• uart0::int_ena::RS485_FRM_ERR_W
• uart0::int_ena::RS485_PARITY_ERR_R
• uart0::int_ena::RS485_PARITY_ERR_W
• uart0::int_ena::RXFIFO_FULL_R
• uart0::int_ena::RXFIFO_FULL_W
• uart0::int_ena::RXFIFO_OVF_R
• uart0::int_ena::RXFIFO_OVF_W
• uart0::int_ena::RXFIFO_TOUT_R
• uart0::int_ena::RXFIFO_TOUT_W
• uart0::int_ena::SW_XOFF_R
• uart0::int_ena::SW_XOFF_W
• uart0::int_ena::SW_XON_R
• uart0::int_ena::SW_XON_W
• uart0::int_ena::TXFIFO_EMPTY_R
• uart0::int_ena::TXFIFO_EMPTY_W
• uart0::int_ena::TX_BRK_DONE_R
• uart0::int_ena::TX_BRK_DONE_W
• uart0::int_ena::TX_BRK_IDLE_DONE_R
• uart0::int_ena::TX_BRK_IDLE_DONE_W
• uart0::int_ena::TX_DONE_R
• uart0::int_ena::TX_DONE_W
• uart0::int_ena::W
• uart0::int_ena::WAKEUP_R
• uart0::int_ena::WAKEUP_W
• uart0::int_raw::AT_CMD_CHAR_DET_R
• uart0::int_raw::AT_CMD_CHAR_DET_W
• uart0::int_raw::BRK_DET_R
• uart0::int_raw::BRK_DET_W
• uart0::int_raw::CTS_CHG_R
• uart0::int_raw::CTS_CHG_W
• uart0::int_raw::DSR_CHG_R
• uart0::int_raw::DSR_CHG_W
• uart0::int_raw::FRM_ERR_R
• uart0::int_raw::FRM_ERR_W
• uart0::int_raw::GLITCH_DET_R
• uart0::int_raw::GLITCH_DET_W
• uart0::int_raw::PARITY_ERR_R
• uart0::int_raw::PARITY_ERR_W
• uart0::int_raw::R
• uart0::int_raw::RS485_CLASH_R
• uart0::int_raw::RS485_CLASH_W
• uart0::int_raw::RS485_FRM_ERR_R
• uart0::int_raw::RS485_FRM_ERR_W
• uart0::int_raw::RS485_PARITY_ERR_R
• uart0::int_raw::RS485_PARITY_ERR_W
• uart0::int_raw::RXFIFO_FULL_R
• uart0::int_raw::RXFIFO_FULL_W
• uart0::int_raw::RXFIFO_OVF_R
• uart0::int_raw::RXFIFO_OVF_W
• uart0::int_raw::RXFIFO_TOUT_R
• uart0::int_raw::RXFIFO_TOUT_W
• uart0::int_raw::SW_XOFF_R
• uart0::int_raw::SW_XOFF_W
• uart0::int_raw::SW_XON_R
• uart0::int_raw::SW_XON_W
• uart0::int_raw::TXFIFO_EMPTY_R
• uart0::int_raw::TXFIFO_EMPTY_W
• uart0::int_raw::TX_BRK_DONE_R
• uart0::int_raw::TX_BRK_DONE_W
• uart0::int_raw::TX_BRK_IDLE_DONE_R
• uart0::int_raw::TX_BRK_IDLE_DONE_W
• uart0::int_raw::TX_DONE_R
• uart0::int_raw::TX_DONE_W
• uart0::int_raw::W
• uart0::int_raw::WAKEUP_R
• uart0::int_raw::WAKEUP_W
• uart0::int_st::AT_CMD_CHAR_DET_R
• uart0::int_st::BRK_DET_R
• uart0::int_st::CTS_CHG_R
• uart0::int_st::DSR_CHG_R
• uart0::int_st::FRM_ERR_R
• uart0::int_st::GLITCH_DET_R
• uart0::int_st::PARITY_ERR_R
• uart0::int_st::R
• uart0::int_st::RS485_CLASH_R
• uart0::int_st::RS485_FRM_ERR_R
• uart0::int_st::RS485_PARITY_ERR_R
• uart0::int_st::RXFIFO_FULL_R
• uart0::int_st::RXFIFO_OVF_R
• uart0::int_st::RXFIFO_TOUT_R
• uart0::int_st::SW_XOFF_R
• uart0::int_st::SW_XON_R
• uart0::int_st::TXFIFO_EMPTY_R
• uart0::int_st::TX_BRK_DONE_R
• uart0::int_st::TX_BRK_IDLE_DONE_R
• uart0::int_st::TX_DONE_R
• uart0::int_st::WAKEUP_R
• uart0::lowpulse::MIN_CNT_R
• uart0::lowpulse::R
• uart0::mem_conf::MEM_FORCE_PD_R
• uart0::mem_conf::MEM_FORCE_PD_W
• uart0::mem_conf::MEM_FORCE_PU_R
• uart0::mem_conf::MEM_FORCE_PU_W
• uart0::mem_conf::R
• uart0::mem_conf::W
• uart0::mem_rx_status::R
• uart0::mem_rx_status::RX_SRAM_RADDR_R
• uart0::mem_rx_status::RX_SRAM_WADDR_R
• uart0::mem_tx_status::R
• uart0::mem_tx_status::TX_SRAM_RADDR_R
• uart0::mem_tx_status::TX_SRAM_WADDR_R
• uart0::negpulse::NEGEDGE_MIN_CNT_R
• uart0::negpulse::R
• uart0::pospulse::POSEDGE_MIN_CNT_R
• uart0::pospulse::R
• uart0::reg_update::R
• uart0::reg_update::REG_UPDATE_R
• uart0::reg_update::REG_UPDATE_W
• uart0::reg_update::W
• uart0::rs485_conf::DL0_EN_R
• uart0::rs485_conf::DL0_EN_W
• uart0::rs485_conf::DL1_EN_R
• uart0::rs485_conf::DL1_EN_W
• uart0::rs485_conf::R
• uart0::rs485_conf::RS485RXBY_TX_EN_R
• uart0::rs485_conf::RS485RXBY_TX_EN_W
• uart0::rs485_conf::RS485TX_RX_EN_R
• uart0::rs485_conf::RS485TX_RX_EN_W
• uart0::rs485_conf::RS485_EN_R
• uart0::rs485_conf::RS485_EN_W
• uart0::rs485_conf::RS485_RX_DLY_NUM_R
• uart0::rs485_conf::RS485_RX_DLY_NUM_W
• uart0::rs485_conf::RS485_TX_DLY_NUM_R
• uart0::rs485_conf::RS485_TX_DLY_NUM_W
• uart0::rs485_conf::W
• uart0::rx_filt::GLITCH_FILT_EN_R
• uart0::rx_filt::GLITCH_FILT_EN_W
• uart0::rx_filt::GLITCH_FILT_R
• uart0::rx_filt::GLITCH_FILT_W
• uart0::rx_filt::R
• uart0::rx_filt::W
• uart0::rxd_cnt::R
• uart0::rxd_cnt::RXD_EDGE_CNT_R
• uart0::sleep_conf0::R
• uart0::sleep_conf0::W
• uart0::sleep_conf0::WK_CHAR1_R
• uart0::sleep_conf0::WK_CHAR1_W
• uart0::sleep_conf0::WK_CHAR2_R
• uart0::sleep_conf0::WK_CHAR2_W
• uart0::sleep_conf0::WK_CHAR3_R
• uart0::sleep_conf0::WK_CHAR3_W
• uart0::sleep_conf0::WK_CHAR4_R
• uart0::sleep_conf0::WK_CHAR4_W
• uart0::sleep_conf1::R
• uart0::sleep_conf1::W
• uart0::sleep_conf1::WK_CHAR0_R
• uart0::sleep_conf1::WK_CHAR0_W
• uart0::sleep_conf2::ACTIVE_THRESHOLD_R
• uart0::sleep_conf2::ACTIVE_THRESHOLD_W
• uart0::sleep_conf2::R
• uart0::sleep_conf2::RX_WAKE_UP_THRHD_R
• uart0::sleep_conf2::RX_WAKE_UP_THRHD_W
• uart0::sleep_conf2::W
• uart0::sleep_conf2::WK_CHAR_MASK_R
• uart0::sleep_conf2::WK_CHAR_MASK_W
• uart0::sleep_conf2::WK_CHAR_NUM_R
• uart0::sleep_conf2::WK_CHAR_NUM_W
• uart0::sleep_conf2::WK_MODE_SEL_R
• uart0::sleep_conf2::WK_MODE_SEL_W
• uart0::status::CTSN_R
• uart0::status::DSRN_R
• uart0::status::DTRN_R
• uart0::status::R
• uart0::status::RTSN_R
• uart0::status::RXD_R
• uart0::status::RXFIFO_CNT_R
• uart0::status::TXD_R
• uart0::status::TXFIFO_CNT_R
• uart0::swfc_conf0::FORCE_XOFF_R
• uart0::swfc_conf0::FORCE_XOFF_W
• uart0::swfc_conf0::FORCE_XON_R
• uart0::swfc_conf0::FORCE_XON_W
• uart0::swfc_conf0::R
• uart0::swfc_conf0::SEND_XOFF_R
• uart0::swfc_conf0::SEND_XOFF_W
• uart0::swfc_conf0::SEND_XON_R
• uart0::swfc_conf0::SEND_XON_W
• uart0::swfc_conf0::SW_FLOW_CON_EN_R
• uart0::swfc_conf0::SW_FLOW_CON_EN_W
• uart0::swfc_conf0::W
• uart0::swfc_conf0::XOFF_CHAR_R
• uart0::swfc_conf0::XOFF_CHAR_W
• uart0::swfc_conf0::XONOFF_DEL_R
• uart0::swfc_conf0::XONOFF_DEL_W
• uart0::swfc_conf0::XON_CHAR_R
• uart0::swfc_conf0::XON_CHAR_W
• uart0::swfc_conf0::XON_XOFF_STILL_SEND_R
• uart0::swfc_conf0::XON_XOFF_STILL_SEND_W
• uart0::swfc_conf1::R
• uart0::swfc_conf1::W
• uart0::swfc_conf1::XOFF_THRESHOLD_R
• uart0::swfc_conf1::XOFF_THRESHOLD_W
• uart0::swfc_conf1::XON_THRESHOLD_R
• uart0::swfc_conf1::XON_THRESHOLD_W
• uart0::tout_conf::R
• uart0::tout_conf::RX_TOUT_EN_R
• uart0::tout_conf::RX_TOUT_EN_W
• uart0::tout_conf::RX_TOUT_FLOW_DIS_R
• uart0::tout_conf::RX_TOUT_FLOW_DIS_W
• uart0::tout_conf::RX_TOUT_THRHD_R
• uart0::tout_conf::RX_TOUT_THRHD_W
• uart0::tout_conf::W
• uart0::txbrk_conf::R
• uart0::txbrk_conf::TX_BRK_NUM_R
• uart0::txbrk_conf::TX_BRK_NUM_W
• uart0::txbrk_conf::W
• uhci0::ACK_NUM
• uhci0::CONF0
• uhci0::CONF1
• uhci0::DATE
• uhci0::ESCAPE_CONF
• uhci0::ESC_CONF
• uhci0::HUNG_CONF
• uhci0::INT_CLR
• uhci0::INT_ENA
• uhci0::INT_RAW
• uhci0::INT_ST
• uhci0::PKT_THRES
• uhci0::QUICK_SENT
• uhci0::RX_HEAD
• uhci0::STATE0
• uhci0::STATE1
• uhci0::ack_num::ACK_NUM_R
• uhci0::ack_num::ACK_NUM_W
• uhci0::ack_num::LOAD_W
• uhci0::ack_num::R
• uhci0::ack_num::W
• uhci0::conf0::CLK_EN_R
• uhci0::conf0::CLK_EN_W
• uhci0::conf0::CRC_REC_EN_R
• uhci0::conf0::CRC_REC_EN_W
• uhci0::conf0::ENCODE_CRC_EN_R
• uhci0::conf0::ENCODE_CRC_EN_W
• uhci0::conf0::HEAD_EN_R
• uhci0::conf0::HEAD_EN_W
• uhci0::conf0::LEN_EOF_EN_R
• uhci0::conf0::LEN_EOF_EN_W
• uhci0::conf0::R
• uhci0::conf0::RX_RST_R
• uhci0::conf0::RX_RST_W
• uhci0::conf0::SEPER_EN_R
• uhci0::conf0::SEPER_EN_W
• uhci0::conf0::TX_RST_R
• uhci0::conf0::TX_RST_W
• uhci0::conf0::UART0_CE_R
• uhci0::conf0::UART0_CE_W
• uhci0::conf0::UART1_CE_R
• uhci0::conf0::UART1_CE_W
• uhci0::conf0::UART_IDLE_EOF_EN_R
• uhci0::conf0::UART_IDLE_EOF_EN_W
• uhci0::conf0::UART_RX_BRK_EOF_EN_R
• uhci0::conf0::UART_RX_BRK_EOF_EN_W
• uhci0::conf0::W
• uhci0::conf1::CHECK_SEQ_EN_R
• uhci0::conf1::CHECK_SEQ_EN_W
• uhci0::conf1::CHECK_SUM_EN_R
• uhci0::conf1::CHECK_SUM_EN_W
• uhci0::conf1::CRC_DISABLE_R
• uhci0::conf1::CRC_DISABLE_W
• uhci0::conf1::R
• uhci0::conf1::SAVE_HEAD_R
• uhci0::conf1::SAVE_HEAD_W
• uhci0::conf1::SW_START_W
• uhci0::conf1::TX_ACK_NUM_RE_R
• uhci0::conf1::TX_ACK_NUM_RE_W
• uhci0::conf1::TX_CHECK_SUM_RE_R
• uhci0::conf1::TX_CHECK_SUM_RE_W
• uhci0::conf1::W
• uhci0::conf1::WAIT_SW_START_R
• uhci0::conf1::WAIT_SW_START_W
• uhci0::date::DATE_R
• uhci0::date::DATE_W
• uhci0::date::R
• uhci0::date::W
• uhci0::esc_conf::R
• uhci0::esc_conf::SEPER_CHAR_R
• uhci0::esc_conf::SEPER_CHAR_W
• uhci0::esc_conf::SEPER_ESC_CHAR0_R
• uhci0::esc_conf::SEPER_ESC_CHAR0_W
• uhci0::esc_conf::SEPER_ESC_CHAR1_R
• uhci0::esc_conf::SEPER_ESC_CHAR1_W
• uhci0::esc_conf::W
• uhci0::escape_conf::R
• uhci0::escape_conf::RX_11_ESC_EN_R
• uhci0::escape_conf::RX_11_ESC_EN_W
• uhci0::escape_conf::RX_13_ESC_EN_R
• uhci0::escape_conf::RX_13_ESC_EN_W
• uhci0::escape_conf::RX_C0_ESC_EN_R
• uhci0::escape_conf::RX_C0_ESC_EN_W
• uhci0::escape_conf::RX_DB_ESC_EN_R
• uhci0::escape_conf::RX_DB_ESC_EN_W
• uhci0::escape_conf::TX_11_ESC_EN_R
• uhci0::escape_conf::TX_11_ESC_EN_W
• uhci0::escape_conf::TX_13_ESC_EN_R
• uhci0::escape_conf::TX_13_ESC_EN_W
• uhci0::escape_conf::TX_C0_ESC_EN_R
• uhci0::escape_conf::TX_C0_ESC_EN_W
• uhci0::escape_conf::TX_DB_ESC_EN_R
• uhci0::escape_conf::TX_DB_ESC_EN_W
• uhci0::escape_conf::W
• uhci0::hung_conf::R
• uhci0::hung_conf::RXFIFO_TIMEOUT_ENA_R
• uhci0::hung_conf::RXFIFO_TIMEOUT_ENA_W
• uhci0::hung_conf::RXFIFO_TIMEOUT_R
• uhci0::hung_conf::RXFIFO_TIMEOUT_SHIFT_R
• uhci0::hung_conf::RXFIFO_TIMEOUT_SHIFT_W
• uhci0::hung_conf::RXFIFO_TIMEOUT_W
• uhci0::hung_conf::TXFIFO_TIMEOUT_ENA_R
• uhci0::hung_conf::TXFIFO_TIMEOUT_ENA_W
• uhci0::hung_conf::TXFIFO_TIMEOUT_R
• uhci0::hung_conf::TXFIFO_TIMEOUT_SHIFT_R
• uhci0::hung_conf::TXFIFO_TIMEOUT_SHIFT_W
• uhci0::hung_conf::TXFIFO_TIMEOUT_W
• uhci0::hung_conf::W
• uhci0::int_clr::APP_CTRL0_W
• uhci0::int_clr::APP_CTRL1_W
• uhci0::int_clr::OUTLINK_EOF_ERR_W
• uhci0::int_clr::RX_HUNG_W
• uhci0::int_clr::RX_START_W
• uhci0::int_clr::SEND_A_REG_Q_W
• uhci0::int_clr::SEND_S_REG_Q_W
• uhci0::int_clr::TX_HUNG_W
• uhci0::int_clr::TX_START_W
• uhci0::int_clr::W
• uhci0::int_ena::APP_CTRL0_R
• uhci0::int_ena::APP_CTRL0_W
• uhci0::int_ena::APP_CTRL1_R
• uhci0::int_ena::APP_CTRL1_W
• uhci0::int_ena::OUTLINK_EOF_ERR_R
• uhci0::int_ena::OUTLINK_EOF_ERR_W
• uhci0::int_ena::R
• uhci0::int_ena::RX_HUNG_R
• uhci0::int_ena::RX_HUNG_W
• uhci0::int_ena::RX_START_R
• uhci0::int_ena::RX_START_W
• uhci0::int_ena::SEND_A_REG_Q_R
• uhci0::int_ena::SEND_A_REG_Q_W
• uhci0::int_ena::SEND_S_REG_Q_R
• uhci0::int_ena::SEND_S_REG_Q_W
• uhci0::int_ena::TX_HUNG_R
• uhci0::int_ena::TX_HUNG_W
• uhci0::int_ena::TX_START_R
• uhci0::int_ena::TX_START_W
• uhci0::int_ena::W
• uhci0::int_raw::APP_CTRL0_R
• uhci0::int_raw::APP_CTRL0_W
• uhci0::int_raw::APP_CTRL1_R
• uhci0::int_raw::APP_CTRL1_W
• uhci0::int_raw::OUT_EOF_R
• uhci0::int_raw::OUT_EOF_W
• uhci0::int_raw::R
• uhci0::int_raw::RX_HUNG_R
• uhci0::int_raw::RX_HUNG_W
• uhci0::int_raw::RX_START_R
• uhci0::int_raw::RX_START_W
• uhci0::int_raw::SEND_A_REG_Q_R
• uhci0::int_raw::SEND_A_REG_Q_W
• uhci0::int_raw::SEND_S_REG_Q_R
• uhci0::int_raw::SEND_S_REG_Q_W
• uhci0::int_raw::TX_HUNG_R
• uhci0::int_raw::TX_HUNG_W
• uhci0::int_raw::TX_START_R
• uhci0::int_raw::TX_START_W
• uhci0::int_raw::W
• uhci0::int_st::APP_CTRL0_R
• uhci0::int_st::APP_CTRL1_R
• uhci0::int_st::OUTLINK_EOF_ERR_R
• uhci0::int_st::R
• uhci0::int_st::RX_HUNG_R
• uhci0::int_st::RX_START_R
• uhci0::int_st::SEND_A_REG_Q_R
• uhci0::int_st::SEND_S_REG_Q_R
• uhci0::int_st::TX_HUNG_R
• uhci0::int_st::TX_START_R
• uhci0::pkt_thres::PKT_THRS_R
• uhci0::pkt_thres::PKT_THRS_W
• uhci0::pkt_thres::R
• uhci0::pkt_thres::W
• uhci0::quick_sent::ALWAYS_SEND_EN_R
• uhci0::quick_sent::ALWAYS_SEND_EN_W
• uhci0::quick_sent::ALWAYS_SEND_NUM_R
• uhci0::quick_sent::ALWAYS_SEND_NUM_W
• uhci0::quick_sent::R
• uhci0::quick_sent::SINGLE_SEND_EN_W
• uhci0::quick_sent::SINGLE_SEND_NUM_R
• uhci0::quick_sent::SINGLE_SEND_NUM_W
• uhci0::quick_sent::W
• uhci0::reg_q::WORD0
• uhci0::reg_q::WORD1
• uhci0::reg_q::word0::R
• uhci0::reg_q::word0::SEND_WORD_R
• uhci0::reg_q::word0::SEND_WORD_W
• uhci0::reg_q::word0::W
• uhci0::reg_q::word1::R
• uhci0::reg_q::word1::SEND_WORD_R
• uhci0::reg_q::word1::SEND_WORD_W
• uhci0::reg_q::word1::W
• uhci0::rx_head::R
• uhci0::rx_head::RX_HEAD_R
• uhci0::state0::DECODE_STATE_R
• uhci0::state0::R
• uhci0::state0::RX_ERR_CAUSE_R
• uhci0::state1::ENCODE_STATE_R
• uhci0::state1::R
• usb_device::BUS_RESET_ST
• usb_device::CHIP_RST
• usb_device::CONF0
• usb_device::CONFIG_UPDATE
• usb_device::DATE
• usb_device::EP1
• usb_device::EP1_CONF
• usb_device::FRAM_NUM
• usb_device::GET_LINE_CODE_W0
• usb_device::GET_LINE_CODE_W1
• usb_device::INT_CLR
• usb_device::INT_ENA
• usb_device::INT_RAW
• usb_device::INT_ST
• usb_device::IN_EP0_ST
• usb_device::IN_EP1_ST
• usb_device::IN_EP2_ST
• usb_device::IN_EP3_ST
• usb_device::JFIFO_ST
• usb_device::MEM_CONF
• usb_device::MISC_CONF
• usb_device::OUT_EP0_ST
• usb_device::OUT_EP1_ST
• usb_device::OUT_EP2_ST
• usb_device::SER_AFIFO_CONFIG
• usb_device::SET_LINE_CODE_W0
• usb_device::SET_LINE_CODE_W1
• usb_device::TEST
• usb_device::bus_reset_st::R
• usb_device::bus_reset_st::USB_BUS_RESET_ST_R
• usb_device::chip_rst::DTR_R
• usb_device::chip_rst::R
• usb_device::chip_rst::RTS_R
• usb_device::chip_rst::USB_UART_CHIP_RST_DIS_R
• usb_device::chip_rst::USB_UART_CHIP_RST_DIS_W
• usb_device::chip_rst::W
• usb_device::conf0::DM_PULLDOWN_R
• usb_device::conf0::DM_PULLDOWN_W
• usb_device::conf0::DM_PULLUP_R
• usb_device::conf0::DM_PULLUP_W
• usb_device::conf0::DP_PULLDOWN_R
• usb_device::conf0::DP_PULLDOWN_W
• usb_device::conf0::DP_PULLUP_R
• usb_device::conf0::DP_PULLUP_W
• usb_device::conf0::EXCHG_PINS_OVERRIDE_R
• usb_device::conf0::EXCHG_PINS_OVERRIDE_W
• usb_device::conf0::EXCHG_PINS_R
• usb_device::conf0::EXCHG_PINS_W
• usb_device::conf0::PAD_PULL_OVERRIDE_R
• usb_device::conf0::PAD_PULL_OVERRIDE_W
• usb_device::conf0::PHY_SEL_R
• usb_device::conf0::PHY_SEL_W
• usb_device::conf0::PULLUP_VALUE_R
• usb_device::conf0::PULLUP_VALUE_W
• usb_device::conf0::R
• usb_device::conf0::USB_JTAG_BRIDGE_EN_R
• usb_device::conf0::USB_JTAG_BRIDGE_EN_W
• usb_device::conf0::USB_PAD_ENABLE_R
• usb_device::conf0::USB_PAD_ENABLE_W
• usb_device::conf0::VREFH_R
• usb_device::conf0::VREFH_W
• usb_device::conf0::VREFL_R
• usb_device::conf0::VREFL_W
• usb_device::conf0::VREF_OVERRIDE_R
• usb_device::conf0::VREF_OVERRIDE_W
• usb_device::conf0::W
• usb_device::config_update::CONFIG_UPDATE_W
• usb_device::config_update::W
• usb_device::date::DATE_R
• usb_device::date::DATE_W
• usb_device::date::R
• usb_device::date::W
• usb_device::ep1::R
• usb_device::ep1::RDWR_BYTE_R
• usb_device::ep1::RDWR_BYTE_W
• usb_device::ep1::W
• usb_device::ep1_conf::R
• usb_device::ep1_conf::SERIAL_IN_EP_DATA_FREE_R
• usb_device::ep1_conf::SERIAL_OUT_EP_DATA_AVAIL_R
• usb_device::ep1_conf::W
• usb_device::ep1_conf::WR_DONE_W
• usb_device::fram_num::R
• usb_device::fram_num::SOF_FRAME_INDEX_R
• usb_device::get_line_code_w0::GET_DW_DTE_RATE_R
• usb_device::get_line_code_w0::GET_DW_DTE_RATE_W
• usb_device::get_line_code_w0::R
• usb_device::get_line_code_w0::W
• usb_device::get_line_code_w1::GET_BCHAR_FORMAT_R
• usb_device::get_line_code_w1::GET_BCHAR_FORMAT_W
• usb_device::get_line_code_w1::GET_BDATA_BITS_R
• usb_device::get_line_code_w1::GET_BDATA_BITS_W
• usb_device::get_line_code_w1::GET_BPARITY_TYPE_R
• usb_device::get_line_code_w1::GET_BPARITY_TYPE_W
• usb_device::get_line_code_w1::R
• usb_device::get_line_code_w1::W
• usb_device::in_ep0_st::IN_EP0_RD_ADDR_R
• usb_device::in_ep0_st::IN_EP0_STATE_R
• usb_device::in_ep0_st::IN_EP0_WR_ADDR_R
• usb_device::in_ep0_st::R
• usb_device::in_ep1_st::IN_EP1_RD_ADDR_R
• usb_device::in_ep1_st::IN_EP1_STATE_R
• usb_device::in_ep1_st::IN_EP1_WR_ADDR_R
• usb_device::in_ep1_st::R
• usb_device::in_ep2_st::IN_EP2_RD_ADDR_R
• usb_device::in_ep2_st::IN_EP2_STATE_R
• usb_device::in_ep2_st::IN_EP2_WR_ADDR_R
• usb_device::in_ep2_st::R
• usb_device::in_ep3_st::IN_EP3_RD_ADDR_R
• usb_device::in_ep3_st::IN_EP3_STATE_R
• usb_device::in_ep3_st::IN_EP3_WR_ADDR_R
• usb_device::in_ep3_st::R
• usb_device::int_clr::CRC16_ERR_W
• usb_device::int_clr::CRC5_ERR_W
• usb_device::int_clr::DTR_CHG_W
• usb_device::int_clr::GET_LINE_CODE_W
• usb_device::int_clr::IN_TOKEN_REC_IN_EP1_W
• usb_device::int_clr::JTAG_IN_FLUSH_W
• usb_device::int_clr::OUT_EP1_ZERO_PAYLOAD_W
• usb_device::int_clr::OUT_EP2_ZERO_PAYLOAD_W
• usb_device::int_clr::PID_ERR_W
• usb_device::int_clr::RTS_CHG_W
• usb_device::int_clr::SERIAL_IN_EMPTY_W
• usb_device::int_clr::SERIAL_OUT_RECV_PKT_W
• usb_device::int_clr::SET_LINE_CODE_W
• usb_device::int_clr::SOF_W
• usb_device::int_clr::STUFF_ERR_W
• usb_device::int_clr::USB_BUS_RESET_W
• usb_device::int_clr::W
• usb_device::int_ena::CRC16_ERR_R
• usb_device::int_ena::CRC16_ERR_W
• usb_device::int_ena::CRC5_ERR_R
• usb_device::int_ena::CRC5_ERR_W
• usb_device::int_ena::DTR_CHG_R
• usb_device::int_ena::DTR_CHG_W
• usb_device::int_ena::GET_LINE_CODE_R
• usb_device::int_ena::GET_LINE_CODE_W
• usb_device::int_ena::IN_TOKEN_REC_IN_EP1_R
• usb_device::int_ena::IN_TOKEN_REC_IN_EP1_W
• usb_device::int_ena::JTAG_IN_FLUSH_R
• usb_device::int_ena::JTAG_IN_FLUSH_W
• usb_device::int_ena::OUT_EP1_ZERO_PAYLOAD_R
• usb_device::int_ena::OUT_EP1_ZERO_PAYLOAD_W
• usb_device::int_ena::OUT_EP2_ZERO_PAYLOAD_R
• usb_device::int_ena::OUT_EP2_ZERO_PAYLOAD_W
• usb_device::int_ena::PID_ERR_R
• usb_device::int_ena::PID_ERR_W
• usb_device::int_ena::R
• usb_device::int_ena::RTS_CHG_R
• usb_device::int_ena::RTS_CHG_W
• usb_device::int_ena::SERIAL_IN_EMPTY_R
• usb_device::int_ena::SERIAL_IN_EMPTY_W
• usb_device::int_ena::SERIAL_OUT_RECV_PKT_R
• usb_device::int_ena::SERIAL_OUT_RECV_PKT_W
• usb_device::int_ena::SET_LINE_CODE_R
• usb_device::int_ena::SET_LINE_CODE_W
• usb_device::int_ena::SOF_R
• usb_device::int_ena::SOF_W
• usb_device::int_ena::STUFF_ERR_R
• usb_device::int_ena::STUFF_ERR_W
• usb_device::int_ena::USB_BUS_RESET_R
• usb_device::int_ena::USB_BUS_RESET_W
• usb_device::int_ena::W
• usb_device::int_raw::CRC16_ERR_R
• usb_device::int_raw::CRC16_ERR_W
• usb_device::int_raw::CRC5_ERR_R
• usb_device::int_raw::CRC5_ERR_W
• usb_device::int_raw::DTR_CHG_R
• usb_device::int_raw::DTR_CHG_W
• usb_device::int_raw::GET_LINE_CODE_R
• usb_device::int_raw::GET_LINE_CODE_W
• usb_device::int_raw::IN_TOKEN_REC_IN_EP1_R
• usb_device::int_raw::IN_TOKEN_REC_IN_EP1_W
• usb_device::int_raw::JTAG_IN_FLUSH_R
• usb_device::int_raw::JTAG_IN_FLUSH_W
• usb_device::int_raw::OUT_EP1_ZERO_PAYLOAD_R
• usb_device::int_raw::OUT_EP1_ZERO_PAYLOAD_W
• usb_device::int_raw::OUT_EP2_ZERO_PAYLOAD_R
• usb_device::int_raw::OUT_EP2_ZERO_PAYLOAD_W
• usb_device::int_raw::PID_ERR_R
• usb_device::int_raw::PID_ERR_W
• usb_device::int_raw::R
• usb_device::int_raw::RTS_CHG_R
• usb_device::int_raw::RTS_CHG_W
• usb_device::int_raw::SERIAL_IN_EMPTY_R
• usb_device::int_raw::SERIAL_IN_EMPTY_W
• usb_device::int_raw::SERIAL_OUT_RECV_PKT_R
• usb_device::int_raw::SERIAL_OUT_RECV_PKT_W
• usb_device::int_raw::SET_LINE_CODE_R
• usb_device::int_raw::SET_LINE_CODE_W
• usb_device::int_raw::SOF_R
• usb_device::int_raw::SOF_W
• usb_device::int_raw::STUFF_ERR_R
• usb_device::int_raw::STUFF_ERR_W
• usb_device::int_raw::USB_BUS_RESET_R
• usb_device::int_raw::USB_BUS_RESET_W
• usb_device::int_raw::W
• usb_device::int_st::CRC16_ERR_R
• usb_device::int_st::CRC5_ERR_R
• usb_device::int_st::DTR_CHG_R
• usb_device::int_st::GET_LINE_CODE_R
• usb_device::int_st::IN_TOKEN_REC_IN_EP1_R
• usb_device::int_st::JTAG_IN_FLUSH_R
• usb_device::int_st::OUT_EP1_ZERO_PAYLOAD_R
• usb_device::int_st::OUT_EP2_ZERO_PAYLOAD_R
• usb_device::int_st::PID_ERR_R
• usb_device::int_st::R
• usb_device::int_st::RTS_CHG_R
• usb_device::int_st::SERIAL_IN_EMPTY_R
• usb_device::int_st::SERIAL_OUT_RECV_PKT_R
• usb_device::int_st::SET_LINE_CODE_R
• usb_device::int_st::SOF_R
• usb_device::int_st::STUFF_ERR_R
• usb_device::int_st::USB_BUS_RESET_R
• usb_device::jfifo_st::IN_FIFO_CNT_R
• usb_device::jfifo_st::IN_FIFO_EMPTY_R
• usb_device::jfifo_st::IN_FIFO_FULL_R
• usb_device::jfifo_st::IN_FIFO_RESET_R
• usb_device::jfifo_st::IN_FIFO_RESET_W
• usb_device::jfifo_st::OUT_FIFO_CNT_R
• usb_device::jfifo_st::OUT_FIFO_EMPTY_R
• usb_device::jfifo_st::OUT_FIFO_FULL_R
• usb_device::jfifo_st::OUT_FIFO_RESET_R
• usb_device::jfifo_st::OUT_FIFO_RESET_W
• usb_device::jfifo_st::R
• usb_device::jfifo_st::W
• usb_device::mem_conf::R
• usb_device::mem_conf::USB_MEM_CLK_EN_R
• usb_device::mem_conf::USB_MEM_CLK_EN_W
• usb_device::mem_conf::USB_MEM_PD_R
• usb_device::mem_conf::USB_MEM_PD_W
• usb_device::mem_conf::W
• usb_device::misc_conf::CLK_EN_R
• usb_device::misc_conf::CLK_EN_W
• usb_device::misc_conf::R
• usb_device::misc_conf::W
• usb_device::out_ep0_st::OUT_EP0_RD_ADDR_R
• usb_device::out_ep0_st::OUT_EP0_STATE_R
• usb_device::out_ep0_st::OUT_EP0_WR_ADDR_R
• usb_device::out_ep0_st::R
• usb_device::out_ep1_st::OUT_EP1_RD_ADDR_R
• usb_device::out_ep1_st::OUT_EP1_REC_DATA_CNT_R
• usb_device::out_ep1_st::OUT_EP1_STATE_R
• usb_device::out_ep1_st::OUT_EP1_WR_ADDR_R
• usb_device::out_ep1_st::R
• usb_device::out_ep2_st::OUT_EP2_RD_ADDR_R
• usb_device::out_ep2_st::OUT_EP2_STATE_R
• usb_device::out_ep2_st::OUT_EP2_WR_ADDR_R
• usb_device::out_ep2_st::R
• usb_device::ser_afifo_config::R
• usb_device::ser_afifo_config::SERIAL_IN_AFIFO_RESET_RD_R
• usb_device::ser_afifo_config::SERIAL_IN_AFIFO_RESET_RD_W
• usb_device::ser_afifo_config::SERIAL_IN_AFIFO_RESET_WR_R
• usb_device::ser_afifo_config::SERIAL_IN_AFIFO_RESET_WR_W
• usb_device::ser_afifo_config::SERIAL_IN_AFIFO_WFULL_R
• usb_device::ser_afifo_config::SERIAL_OUT_AFIFO_REMPTY_R
• usb_device::ser_afifo_config::SERIAL_OUT_AFIFO_RESET_RD_R
• usb_device::ser_afifo_config::SERIAL_OUT_AFIFO_RESET_RD_W
• usb_device::ser_afifo_config::SERIAL_OUT_AFIFO_RESET_WR_R
• usb_device::ser_afifo_config::SERIAL_OUT_AFIFO_RESET_WR_W
• usb_device::ser_afifo_config::W
• usb_device::set_line_code_w0::DW_DTE_RATE_R
• usb_device::set_line_code_w0::R
• usb_device::set_line_code_w1::BCHAR_FORMAT_R
• usb_device::set_line_code_w1::BDATA_BITS_R
• usb_device::set_line_code_w1::BPARITY_TYPE_R
• usb_device::set_line_code_w1::R
• usb_device::test::R
• usb_device::test::TEST_ENABLE_R
• usb_device::test::TEST_ENABLE_W
• usb_device::test::TEST_RX_DM_R
• usb_device::test::TEST_RX_DP_R
• usb_device::test::TEST_RX_RCV_R
• usb_device::test::TEST_TX_DM_R
• usb_device::test::TEST_TX_DM_W
• usb_device::test::TEST_TX_DP_R
• usb_device::test::TEST_TX_DP_W
• usb_device::test::TEST_USB_OE_R
• usb_device::test::TEST_USB_OE_W
• usb_device::test::W

Constants

• NVIC_PRIO_BITS