Type Alias esp32c6::rmt::int_ena::W

pub type W = W<INT_ENA_SPEC>;

Register INT_ENA writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub unsafe fn ch_tx_end<const O: u8>( &mut self ) -> CH_TX_END_W<'_, INT_ENA_SPEC, O>

The interrupt enable bit for CH[0-1]_TX_END_INT.

pub fn ch0_tx_end(&mut self) -> CH_TX_END_W<'_, INT_ENA_SPEC, 0>

Bit 0 - The interrupt enable bit for CH0_TX_END_INT.

pub fn ch1_tx_end(&mut self) -> CH_TX_END_W<'_, INT_ENA_SPEC, 1>

Bit 1 - The interrupt enable bit for CH1_TX_END_INT.

pub unsafe fn ch_rx_end<const O: u8>( &mut self ) -> CH_RX_END_W<'_, INT_ENA_SPEC, O>

The interrupt enable bit for CH2_RX_END_INT.

pub fn ch2_rx_end(&mut self) -> CH_RX_END_W<'_, INT_ENA_SPEC, 2>

Bit 2 - The interrupt enable bit for CH2_RX_END_INT.

pub fn ch3_rx_end(&mut self) -> CH_RX_END_W<'_, INT_ENA_SPEC, 3>

Bit 3 - The interrupt enable bit for CH2_RX_END_INT.

pub unsafe fn ch_tx_err<const O: u8>( &mut self ) -> CH_TX_ERR_W<'_, INT_ENA_SPEC, O>

The interrupt enable bit for CH4_ERR_INT.

pub fn ch0_tx_err(&mut self) -> CH_TX_ERR_W<'_, INT_ENA_SPEC, 4>

Bit 4 - The interrupt enable bit for CH4_ERR_INT.

pub fn ch1_tx_err(&mut self) -> CH_TX_ERR_W<'_, INT_ENA_SPEC, 5>

Bit 5 - The interrupt enable bit for CH4_ERR_INT.

pub unsafe fn ch_rx_err<const O: u8>( &mut self ) -> CH_RX_ERR_W<'_, INT_ENA_SPEC, O>

The interrupt enable bit for CH6_ERR_INT.

pub fn ch2_rx_err(&mut self) -> CH_RX_ERR_W<'_, INT_ENA_SPEC, 6>

Bit 6 - The interrupt enable bit for CH6_ERR_INT.

pub fn ch3_rx_err(&mut self) -> CH_RX_ERR_W<'_, INT_ENA_SPEC, 7>

Bit 7 - The interrupt enable bit for CH6_ERR_INT.

pub unsafe fn ch_tx_thr_event<const O: u8>( &mut self ) -> CH_TX_THR_EVENT_W<'_, INT_ENA_SPEC, O>

The interrupt enable bit for CH[0-1]_TX_THR_EVENT_INT.

pub fn ch0_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<'_, INT_ENA_SPEC, 8>

Bit 8 - The interrupt enable bit for CH0_TX_THR_EVENT_INT.

pub fn ch1_tx_thr_event(&mut self) -> CH_TX_THR_EVENT_W<'_, INT_ENA_SPEC, 9>

Bit 9 - The interrupt enable bit for CH1_TX_THR_EVENT_INT.

pub unsafe fn ch_rx_thr_event<const O: u8>( &mut self ) -> CH_RX_THR_EVENT_W<'_, INT_ENA_SPEC, O>

The interrupt enable bit for CH2_RX_THR_EVENT_INT.

pub fn ch2_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<'_, INT_ENA_SPEC, 10>

Bit 10 - The interrupt enable bit for CH2_RX_THR_EVENT_INT.

pub fn ch3_rx_thr_event(&mut self) -> CH_RX_THR_EVENT_W<'_, INT_ENA_SPEC, 11>

Bit 11 - The interrupt enable bit for CH2_RX_THR_EVENT_INT.

pub unsafe fn ch_x_loop<const O: u8>( &mut self ) -> CH_X_LOOP_W<'_, INT_ENA_SPEC, O>

The interrupt enable bit for CH[0-1]_TX_LOOP_INT.

pub fn ch0_x_loop(&mut self) -> CH_X_LOOP_W<'_, INT_ENA_SPEC, 12>

Bit 12 - The interrupt enable bit for CH0_TX_LOOP_INT.

pub fn ch1_x_loop(&mut self) -> CH_X_LOOP_W<'_, INT_ENA_SPEC, 13>

Bit 13 - The interrupt enable bit for CH1_TX_LOOP_INT.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual