Module esp32c6::spi1::spi_mem_ctrl

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Expand description

SPI1 control register.

Structs

Type Aliases

  • R
    Register SPI_MEM_CTRL reader
  • SPI_MEM_D_POL_R
    Field SPI_MEM_D_POL reader - The bit is used to set MOSI line polarity, 1: high 0, low
  • SPI_MEM_D_POL_W
    Field SPI_MEM_D_POL writer - The bit is used to set MOSI line polarity, 1: high 0, low
  • SPI_MEM_FADDR_OCT_R
    Field SPI_MEM_FADDR_OCT reader - Apply 8 signals during address phase 1:enable 0: disable
  • SPI_MEM_FASTRD_MODE_R
    Field SPI_MEM_FASTRD_MODE reader - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
  • SPI_MEM_FASTRD_MODE_W
    Field SPI_MEM_FASTRD_MODE writer - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
  • SPI_MEM_FCMD_OCT_R
    Field SPI_MEM_FCMD_OCT reader - Apply 8 signals during command phase 1:enable 0: disable
  • SPI_MEM_FCMD_QUAD_R
    Field SPI_MEM_FCMD_QUAD reader - Apply 4 signals during command phase 1:enable 0: disable
  • SPI_MEM_FCMD_QUAD_W
    Field SPI_MEM_FCMD_QUAD writer - Apply 4 signals during command phase 1:enable 0: disable
  • SPI_MEM_FCS_CRC_EN_R
    Field SPI_MEM_FCS_CRC_EN reader - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.
  • SPI_MEM_FDIN_OCT_R
    Field SPI_MEM_FDIN_OCT reader - Apply 8 signals during read-data phase 1:enable 0: disable
  • SPI_MEM_FDOUT_OCT_R
    Field SPI_MEM_FDOUT_OCT reader - Apply 8 signals during write-data phase 1:enable 0: disable
  • SPI_MEM_FDUMMY_RIN_R
    Field SPI_MEM_FDUMMY_RIN reader - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller.
  • SPI_MEM_FDUMMY_RIN_W
    Field SPI_MEM_FDUMMY_RIN writer - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller.
  • SPI_MEM_FDUMMY_WOUT_R
    Field SPI_MEM_FDUMMY_WOUT reader - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller.
  • SPI_MEM_FDUMMY_WOUT_W
    Field SPI_MEM_FDUMMY_WOUT writer - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller.
  • SPI_MEM_FREAD_DIO_R
    Field SPI_MEM_FREAD_DIO reader - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
  • SPI_MEM_FREAD_DIO_W
    Field SPI_MEM_FREAD_DIO writer - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
  • SPI_MEM_FREAD_DUAL_R
    Field SPI_MEM_FREAD_DUAL reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
  • SPI_MEM_FREAD_DUAL_W
    Field SPI_MEM_FREAD_DUAL writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
  • SPI_MEM_FREAD_QIO_R
    Field SPI_MEM_FREAD_QIO reader - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
  • SPI_MEM_FREAD_QIO_W
    Field SPI_MEM_FREAD_QIO writer - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
  • SPI_MEM_FREAD_QUAD_R
    Field SPI_MEM_FREAD_QUAD reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
  • SPI_MEM_FREAD_QUAD_W
    Field SPI_MEM_FREAD_QUAD writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
  • SPI_MEM_Q_POL_R
    Field SPI_MEM_Q_POL reader - The bit is used to set MISO line polarity, 1: high 0, low
  • SPI_MEM_Q_POL_W
    Field SPI_MEM_Q_POL writer - The bit is used to set MISO line polarity, 1: high 0, low
  • SPI_MEM_RESANDRES_R
    Field SPI_MEM_RESANDRES reader - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.
  • SPI_MEM_RESANDRES_W
    Field SPI_MEM_RESANDRES writer - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.
  • SPI_MEM_TX_CRC_EN_R
    Field SPI_MEM_TX_CRC_EN reader - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
  • SPI_MEM_WP_R
    Field SPI_MEM_WP reader - Write protect signal output when SPI is idle. 1: output high, 0: output low.
  • SPI_MEM_WP_W
    Field SPI_MEM_WP writer - Write protect signal output when SPI is idle. 1: output high, 0: output low.
  • SPI_MEM_WRSR_2B_R
    Field SPI_MEM_WRSR_2B reader - two bytes data will be written to status register when it is set. 1: enable 0: disable.
  • SPI_MEM_WRSR_2B_W
    Field SPI_MEM_WRSR_2B writer - two bytes data will be written to status register when it is set. 1: enable 0: disable.
  • W
    Register SPI_MEM_CTRL writer