Type Alias esp32c6::spi0::spi_mem_ctrl::W

pub type W = W<SPI_MEM_CTRL_SPEC>;

Register SPI_MEM_CTRL writer

Aliased Type

struct W { /* private fields */ }

Implementations

impl W

pub fn spi_mem_wdummy_always_out( &mut self ) -> SPI_MEM_WDUMMY_ALWAYS_OUT_W<'_, SPI_MEM_CTRL_SPEC, 1>

Bit 1 - In the dummy phase of an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller.

pub fn spi_mem_fdummy_rin( &mut self ) -> SPI_MEM_FDUMMY_RIN_W<'_, SPI_MEM_CTRL_SPEC, 2>

Bit 2 - In an MSPI read data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the first half part of dummy phase. It is used to mask invalid SPI_DQS in the half part of dummy phase.

pub fn spi_mem_fdummy_wout( &mut self ) -> SPI_MEM_FDUMMY_WOUT_W<'_, SPI_MEM_CTRL_SPEC, 3>

Bit 3 - In an MSPI write data transfer when accesses to flash, the level of SPI_IO[7:0] is output by the MSPI controller in the second half part of dummy phase. It is used to pre-drive flash.

pub fn spi_mem_fcmd_quad( &mut self ) -> SPI_MEM_FCMD_QUAD_W<'_, SPI_MEM_CTRL_SPEC, 8>

Bit 8 - Apply 4 signals during command phase 1:enable 0: disable

pub fn spi_mem_fastrd_mode( &mut self ) -> SPI_MEM_FASTRD_MODE_W<'_, SPI_MEM_CTRL_SPEC, 13>

Bit 13 - This bit enable the bits: SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QOUT and SPI_MEM_FREAD_DOUT. 1: enable 0: disable.

pub fn spi_mem_fread_dual( &mut self ) -> SPI_MEM_FREAD_DUAL_W<'_, SPI_MEM_CTRL_SPEC, 14>

Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.

pub fn spi_mem_q_pol(&mut self) -> SPI_MEM_Q_POL_W<'_, SPI_MEM_CTRL_SPEC, 18>

Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low

pub fn spi_mem_d_pol(&mut self) -> SPI_MEM_D_POL_W<'_, SPI_MEM_CTRL_SPEC, 19>

Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low

pub fn spi_mem_fread_quad( &mut self ) -> SPI_MEM_FREAD_QUAD_W<'_, SPI_MEM_CTRL_SPEC, 20>

Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable.

pub fn spi_mem_wp(&mut self) -> SPI_MEM_WP_W<'_, SPI_MEM_CTRL_SPEC, 21>

Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low.

pub fn spi_mem_fread_dio( &mut self ) -> SPI_MEM_FREAD_DIO_W<'_, SPI_MEM_CTRL_SPEC, 23>

Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.

pub fn spi_mem_fread_qio( &mut self ) -> SPI_MEM_FREAD_QIO_W<'_, SPI_MEM_CTRL_SPEC, 24>

Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.

pub fn spi_mem_data_ie_always_on( &mut self ) -> SPI_MEM_DATA_IE_ALWAYS_ON_W<'_, SPI_MEM_CTRL_SPEC, 31>

Bit 31 - When accesses to flash, 1: the IE signals of pads connected to SPI_IO[7:0] are always 1. 0: Others.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Safety

Passing incorrect value can cause undefined behaviour. See reference manual