Type Alias esp32c6::ledc::timer_conf::W
source · pub type W = W<TIMER_CONF_SPEC>;Expand description
Register TIMER%s_CONF writer
Implementations§
source§impl W
impl W
sourcepub fn duty_res(&mut self) -> DUTY_RES_W<'_, TIMER_CONF_SPEC, 0>
pub fn duty_res(&mut self) -> DUTY_RES_W<'_, TIMER_CONF_SPEC, 0>
Bits 0:4 - This register is used to control the range of the counter in timer %s.
sourcepub fn clk_div(&mut self) -> CLK_DIV_W<'_, TIMER_CONF_SPEC, 5>
pub fn clk_div(&mut self) -> CLK_DIV_W<'_, TIMER_CONF_SPEC, 5>
Bits 5:22 - This register is used to configure the divisor for the divider in timer %s. The least significant eight bits represent the fractional part.
sourcepub fn pause(&mut self) -> PAUSE_W<'_, TIMER_CONF_SPEC, 23>
pub fn pause(&mut self) -> PAUSE_W<'_, TIMER_CONF_SPEC, 23>
Bit 23 - This bit is used to suspend the counter in timer %s.
sourcepub fn rst(&mut self) -> RST_W<'_, TIMER_CONF_SPEC, 24>
pub fn rst(&mut self) -> RST_W<'_, TIMER_CONF_SPEC, 24>
Bit 24 - This bit is used to reset timer %s. The counter will show 0 after reset.
sourcepub fn tick_sel(&mut self) -> TICK_SEL_W<'_, TIMER_CONF_SPEC, 25>
pub fn tick_sel(&mut self) -> TICK_SEL_W<'_, TIMER_CONF_SPEC, 25>
Bit 25 - This bit is used to select clock for timer %s. When this bit is set to 1 LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not accurate. 1’h0: SLOW_CLK 1’h1: REF_TICK
sourcepub fn para_up(&mut self) -> PARA_UP_W<'_, TIMER_CONF_SPEC, 26>
pub fn para_up(&mut self) -> PARA_UP_W<'_, TIMER_CONF_SPEC, 26>
Bit 26 - Set this bit to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.