Type Alias esp32c6::spi0::spi_smem_ddr::R

pub type R = R<SPI_SMEM_DDR_SPEC>;

Register SPI_SMEM_DDR reader

Implementations

impl R

pub fn en(&self) -> EN_R

Bit 0 - 1: in DDR mode, 0 in SDR mode

pub fn spi_smem_var_dummy(&self) -> SPI_SMEM_VAR_DUMMY_R

Bit 1 - Set the bit to enable variable dummy cycle in spi DDR mode.

pub fn rdat_swp(&self) -> RDAT_SWP_R

Bit 2 - Set the bit to reorder rx data of the word in spi DDR mode.

pub fn wdat_swp(&self) -> WDAT_SWP_R

Bit 3 - Set the bit to reorder tx data of the word in spi DDR mode.

pub fn cmd_dis(&self) -> CMD_DIS_R

Bit 4 - the bit is used to disable dual edge in command phase when DDR mode.

pub fn spi_smem_outminbytelen(&self) -> SPI_SMEM_OUTMINBYTELEN_R

Bits 5:11 - It is the minimum output data length in the DDR psram.

pub fn spi_smem_tx_ddr_msk_en(&self) -> SPI_SMEM_TX_DDR_MSK_EN_R

Bit 12 - Set this bit to mask the first or the last byte in SPI0 ECC DDR write mode, when accesses to external RAM.

pub fn spi_smem_rx_ddr_msk_en(&self) -> SPI_SMEM_RX_DDR_MSK_EN_R

Bit 13 - Set this bit to mask the first or the last byte in SPI0 ECC DDR read mode, when accesses to external RAM.

pub fn spi_smem_usr_ddr_dqs_thd(&self) -> SPI_SMEM_USR_DDR_DQS_THD_R

Bits 14:20 - The delay number of data strobe which from memory based on SPI clock.

pub fn dqs_loop(&self) -> DQS_LOOP_R

Bit 21 - 1: Do not need the input of SPI_DQS signal, SPI0 starts to receive data when spi0_slv_st is in SPI_MEM_DIN state. It is used when there is no SPI_DQS signal or SPI_DQS signal is not stable. 0: SPI0 starts to store data at the positive and negative edge of SPI_DQS.

pub fn spi_smem_clk_diff_en(&self) -> SPI_SMEM_CLK_DIFF_EN_R

Bit 24 - Set this bit to enable the differential SPI_CLK#.

pub fn spi_smem_dqs_ca_in(&self) -> SPI_SMEM_DQS_CA_IN_R

Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.

pub fn spi_smem_hyperbus_dummy_2x(&self) -> SPI_SMEM_HYPERBUS_DUMMY_2X_R

Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.

pub fn spi_smem_clk_diff_inv(&self) -> SPI_SMEM_CLK_DIFF_INV_R

Bit 28 - Set this bit to invert SPI_DIFF when accesses to external RAM. .

pub fn spi_smem_octa_ram_addr(&self) -> SPI_SMEM_OCTA_RAM_ADDR_R

Bit 29 - Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6’d0, spi_usr_addr_value[3:1], 1’b0}.

pub fn spi_smem_hyperbus_ca(&self) -> SPI_SMEM_HYPERBUS_CA_R

Bit 30 - Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13’d0, spi_usr_addr_value[3:1]}.