Struct esp32c6::spi0::spi_mem_axi_err_addr::R

pub struct R(_);

Register SPI_MEM_AXI_ERR_ADDR reader

Implementations

impl R

pub fn spi_mem_axi_err_addr(&self) -> SPI_MEM_AXI_ERR_ADDR_R

Bits 0:25 - This bits show the first AXI write/read invalid error or AXI write flash error address. It is cleared by when SPI_MEM_AXI_WADDR_ERR_INT_CLR, SPI_MEM_AXI_WR_FLASH_ERR_IN_CLR or SPI_MEM_AXI_RADDR_ERR_IN_CLR bit is set.

pub fn spi_mem_all_fifo_empty(&self) -> SPI_MEM_ALL_FIFO_EMPTY_R

Bit 26 - The empty status of all AFIFO and SYNC_FIFO in MSPI module. 1: All AXI transfers and SPI0 transfers are done. 0: Others.

pub fn spi_rdata_afifo_rempty(&self) -> SPI_RDATA_AFIFO_REMPTY_R

Bit 27 - 1: RDATA_AFIFO is empty. 0: At least one AXI read transfer is pending.

pub fn spi_raddr_afifo_rempty(&self) -> SPI_RADDR_AFIFO_REMPTY_R

Bit 28 - 1: AXI_RADDR_CTL_AFIFO is empty. 0: At least one AXI read transfer is pending.

pub fn spi_wdata_afifo_rempty(&self) -> SPI_WDATA_AFIFO_REMPTY_R

Bit 29 - 1: WDATA_AFIFO is empty. 0: At least one AXI write transfer is pending.

pub fn spi_wblen_afifo_rempty(&self) -> SPI_WBLEN_AFIFO_REMPTY_R

Bit 30 - 1: WBLEN_AFIFO is empty. 0: At least one AXI write transfer is pending.

pub fn spi_all_axi_trans_afifo_empty(&self) -> SPI_ALL_AXI_TRANS_AFIFO_EMPTY_R

Bit 31 - This bit is set when WADDR_AFIFO, WBLEN_AFIFO, WDATA_AFIFO, AXI_RADDR_CTL_AFIFO and RDATA_AFIFO are empty and spi0_mst_st is IDLE.

Methods from Deref<Target = R<SPI_MEM_AXI_ERR_ADDR_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<SPI_MEM_AXI_ERR_ADDR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<SPI_MEM_AXI_ERR_ADDR_SPEC>> for R

fn from(reader: R<SPI_MEM_AXI_ERR_ADDR_SPEC>) -> Self

Converts to this type from the input type.